Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
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Source (jump to first uncovered line)
1
//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file handles ELF-specific object emission, converting LLVM's internal
10
// fixups into the appropriate relocations.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "MCTargetDesc/AArch64FixupKinds.h"
15
#include "MCTargetDesc/AArch64MCExpr.h"
16
#include "MCTargetDesc/AArch64MCTargetDesc.h"
17
#include "llvm/BinaryFormat/ELF.h"
18
#include "llvm/MC/MCContext.h"
19
#include "llvm/MC/MCELFObjectWriter.h"
20
#include "llvm/MC/MCFixup.h"
21
#include "llvm/MC/MCObjectWriter.h"
22
#include "llvm/MC/MCValue.h"
23
#include "llvm/Support/ErrorHandling.h"
24
#include <cassert>
25
#include <cstdint>
26
27
using namespace llvm;
28
29
namespace {
30
31
class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
32
public:
33
  AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
34
35
4.31k
  ~AArch64ELFObjectWriter() override = default;
36
37
protected:
38
  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
39
                        const MCFixup &Fixup, bool IsPCRel) const override;
40
  bool IsILP32;
41
};
42
43
} // end anonymous namespace
44
45
AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
46
    : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
47
                              /*HasRelocationAddend*/ true),
48
4.31k
      IsILP32(IsILP32) {}
49
50
#define R_CLS(rtype)                                                           \
51
895
  IsILP32 ? 
ELF::R_AARCH64_P32_81
##rtype :
ELF::R_AARCH64_826
##rtype
52
#define BAD_ILP32_MOV(lp64rtype)                                               \
53
12
  "ILP32 absolute MOV relocation not "                                         \
54
12
  "supported (LP64 eqv: " #lp64rtype ")"
55
56
// assumes IsILP32 is true
57
static bool isNonILP32reloc(const MCFixup &Fixup,
58
                            AArch64MCExpr::VariantKind RefKind,
59
85
                            MCContext &Ctx) {
60
85
  if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
61
73
    return false;
62
12
  switch (RefKind) {
63
12
  case AArch64MCExpr::VK_ABS_G3:
64
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
65
1
    return true;
66
12
  case AArch64MCExpr::VK_ABS_G2:
67
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
68
1
    return true;
69
12
  case AArch64MCExpr::VK_ABS_G2_S:
70
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
71
1
    return true;
72
12
  case AArch64MCExpr::VK_ABS_G2_NC:
73
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
74
1
    return true;
75
12
  case AArch64MCExpr::VK_ABS_G1_S:
76
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
77
1
    return true;
78
12
  case AArch64MCExpr::VK_ABS_G1_NC:
79
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
80
1
    return true;
81
12
  case AArch64MCExpr::VK_DTPREL_G2:
82
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
83
1
    return true;
84
12
  case AArch64MCExpr::VK_DTPREL_G1_NC:
85
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
86
1
    return true;
87
12
  case AArch64MCExpr::VK_TPREL_G2:
88
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
89
1
    return true;
90
12
  case AArch64MCExpr::VK_TPREL_G1_NC:
91
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
92
1
    return true;
93
12
  case AArch64MCExpr::VK_GOTTPREL_G1:
94
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
95
1
    return true;
96
12
  case AArch64MCExpr::VK_GOTTPREL_G0_NC:
97
1
    Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
98
1
    return true;
99
12
  default:
100
0
    return false;
101
0
  }
102
0
  return false;
103
0
}
104
105
unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
106
                                              const MCValue &Target,
107
                                              const MCFixup &Fixup,
108
1.22k
                                              bool IsPCRel) const {
109
1.22k
  AArch64MCExpr::VariantKind RefKind =
110
1.22k
      static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
111
1.22k
  AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
112
1.22k
  bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
113
1.22k
114
1.22k
  assert((!Target.getSymA() ||
115
1.22k
          Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
116
1.22k
         "Should only be expression-level modifiers here");
117
1.22k
118
1.22k
  assert((!Target.getSymB() ||
119
1.22k
          Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
120
1.22k
         "Should only be expression-level modifiers here");
121
1.22k
122
1.22k
  if (IsPCRel) {
123
362
    switch ((unsigned)Fixup.getKind()) {
124
362
    case FK_Data_1:
125
1
      Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
126
1
      return ELF::R_AARCH64_NONE;
127
362
    case FK_Data_2:
128
6
      return R_CLS(PREL16);
129
362
    case FK_Data_4:
130
67
      return R_CLS(PREL32);
131
362
    case FK_Data_8:
132
8
      if (IsILP32) {
133
1
        Ctx.reportError(Fixup.getLoc(),
134
1
                        "ILP32 8 byte PC relative data "
135
1
                        "relocation not supported (LP64 eqv: PREL64)");
136
1
        return ELF::R_AARCH64_NONE;
137
1
      } else
138
7
        return ELF::R_AARCH64_PREL64;
139
11
    case AArch64::fixup_aarch64_pcrel_adr_imm21:
140
11
      if (SymLoc != AArch64MCExpr::VK_ABS)
141
0
        Ctx.reportError(Fixup.getLoc(),
142
0
                        "invalid symbol kind for ADR relocation");
143
11
      return R_CLS(ADR_PREL_LO21);
144
166
    case AArch64::fixup_aarch64_pcrel_adrp_imm21:
145
166
      if (SymLoc == AArch64MCExpr::VK_ABS && 
!IsNC106
)
146
103
        return R_CLS(ADR_PREL_PG_HI21);
147
63
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC3
) {
148
3
        if (IsILP32) {
149
0
          Ctx.reportError(Fixup.getLoc(),
150
0
                          "invalid fixup for 32-bit pcrel ADRP instruction "
151
0
                          "VK_ABS VK_NC");
152
0
          return ELF::R_AARCH64_NONE;
153
3
        } else {
154
3
          return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
155
3
        }
156
60
      }
157
60
      if (SymLoc == AArch64MCExpr::VK_GOT && 
!IsNC20
)
158
20
        return R_CLS(ADR_GOT_PAGE);
159
40
      if (SymLoc == AArch64MCExpr::VK_GOTTPREL && 
!IsNC16
)
160
16
        return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
161
24
      if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
162
24
        return R_CLS(TLSDESC_ADR_PAGE21);
163
0
      Ctx.reportError(Fixup.getLoc(),
164
0
                      "invalid symbol kind for ADRP relocation");
165
0
      return ELF::R_AARCH64_NONE;
166
12
    case AArch64::fixup_aarch64_pcrel_branch26:
167
12
      return R_CLS(JUMP26);
168
50
    case AArch64::fixup_aarch64_pcrel_call26:
169
50
      return R_CLS(CALL26);
170
20
    case AArch64::fixup_aarch64_ldr_pcrel_imm19:
171
20
      if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
172
4
        return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
173
16
      if (SymLoc == AArch64MCExpr::VK_GOT)
174
4
        return R_CLS(GOT_LD_PREL19);
175
12
      return R_CLS(LD_PREL_LO19);
176
12
    case AArch64::fixup_aarch64_pcrel_branch14:
177
8
      return R_CLS(TSTBR14);
178
12
    case AArch64::fixup_aarch64_pcrel_branch19:
179
8
      return R_CLS(CONDBR19);
180
12
    default:
181
5
      Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
182
5
      return ELF::R_AARCH64_NONE;
183
858
    }
184
858
  } else {
185
858
    if (IsILP32 && 
isNonILP32reloc(Fixup, RefKind, Ctx)85
)
186
12
      return ELF::R_AARCH64_NONE;
187
846
    switch ((unsigned)Fixup.getKind()) {
188
846
    case FK_NONE:
189
4
      return ELF::R_AARCH64_NONE;
190
846
    case FK_Data_1:
191
1
      Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
192
1
      return ELF::R_AARCH64_NONE;
193
846
    case FK_Data_2:
194
7
      return R_CLS(ABS16);
195
846
    case FK_Data_4:
196
148
      return R_CLS(ABS32);
197
846
    case FK_Data_8:
198
94
      if (IsILP32) {
199
1
        Ctx.reportError(Fixup.getLoc(),
200
1
                        "ILP32 8 byte absolute data "
201
1
                        "relocation not supported (LP64 eqv: ABS64)");
202
1
        return ELF::R_AARCH64_NONE;
203
1
      } else
204
93
        return ELF::R_AARCH64_ABS64;
205
121
    case AArch64::fixup_aarch64_add_imm12:
206
121
      if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
207
8
        return R_CLS(TLSLD_ADD_DTPREL_HI12);
208
113
      if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
209
16
        return R_CLS(TLSLE_ADD_TPREL_HI12);
210
97
      if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
211
11
        return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
212
86
      if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
213
8
        return R_CLS(TLSLD_ADD_DTPREL_LO12);
214
78
      if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
215
14
        return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
216
64
      if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
217
8
        return R_CLS(TLSLE_ADD_TPREL_LO12);
218
56
      if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
219
24
        return R_CLS(TLSDESC_ADD_LO12);
220
32
      if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
221
32
        return R_CLS(ADD_ABS_LO12_NC);
222
0
223
0
      Ctx.reportError(Fixup.getLoc(),
224
0
                      "invalid fixup for add (uimm12) instruction");
225
0
      return ELF::R_AARCH64_NONE;
226
48
    case AArch64::fixup_aarch64_ldst_imm12_scale1:
227
48
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC21
)
228
21
        return R_CLS(LDST8_ABS_LO12_NC);
229
27
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
!IsNC13
)
230
6
        return R_CLS(TLSLD_LDST8_DTPREL_LO12);
231
21
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
IsNC7
)
232
7
        return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
233
14
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
!IsNC13
)
234
6
        return R_CLS(TLSLE_LDST8_TPREL_LO12);
235
8
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
IsNC7
)
236
7
        return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
237
1
238
1
      Ctx.reportError(Fixup.getLoc(),
239
1
                      "invalid fixup for 8-bit load/store instruction");
240
1
      return ELF::R_AARCH64_NONE;
241
47
    case AArch64::fixup_aarch64_ldst_imm12_scale2:
242
47
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC21
)
243
21
        return R_CLS(LDST16_ABS_LO12_NC);
244
26
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
!IsNC12
)
245
6
        return R_CLS(TLSLD_LDST16_DTPREL_LO12);
246
20
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
IsNC6
)
247
6
        return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
248
14
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
!IsNC13
)
249
6
        return R_CLS(TLSLE_LDST16_TPREL_LO12);
250
8
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
IsNC7
)
251
7
        return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
252
1
253
1
      Ctx.reportError(Fixup.getLoc(),
254
1
                      "invalid fixup for 16-bit load/store instruction");
255
1
      return ELF::R_AARCH64_NONE;
256
46
    case AArch64::fixup_aarch64_ldst_imm12_scale4:
257
46
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC18
)
258
18
        return R_CLS(LDST32_ABS_LO12_NC);
259
28
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
!IsNC10
)
260
4
        return R_CLS(TLSLD_LDST32_DTPREL_LO12);
261
24
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
IsNC6
)
262
6
        return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
263
18
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
!IsNC11
)
264
4
        return R_CLS(TLSLE_LDST32_TPREL_LO12);
265
14
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
IsNC7
)
266
7
        return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
267
7
      if (SymLoc == AArch64MCExpr::VK_GOT && 
IsNC2
) {
268
2
        if (IsILP32) {
269
2
          return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
270
2
        } else {
271
0
          Ctx.reportError(Fixup.getLoc(),
272
0
                          "LP64 4 byte unchecked GOT load/store relocation "
273
0
                          "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
274
0
          return ELF::R_AARCH64_NONE;
275
0
        }
276
5
      }
277
5
      if (SymLoc == AArch64MCExpr::VK_GOT && 
!IsNC0
) {
278
0
        if (IsILP32) {
279
0
          Ctx.reportError(Fixup.getLoc(),
280
0
                          "ILP32 4 byte checked GOT load/store relocation "
281
0
                          "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
282
0
        } else {
283
0
          Ctx.reportError(Fixup.getLoc(),
284
0
                          "LP64 4 byte checked GOT load/store relocation "
285
0
                          "not supported (unchecked/ILP32 eqv: "
286
0
                          "LD32_GOT_LO12_NC)");
287
0
        }
288
0
        return ELF::R_AARCH64_NONE;
289
0
      }
290
5
      if (SymLoc == AArch64MCExpr::VK_GOTTPREL && 
IsNC3
) {
291
3
        if (IsILP32) {
292
2
          return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
293
2
        } else {
294
1
          Ctx.reportError(Fixup.getLoc(),
295
1
                          "LP64 32-bit load/store "
296
1
                          "relocation not supported (ILP32 eqv: "
297
1
                          "TLSIE_LD32_GOTTPREL_LO12_NC)");
298
1
          return ELF::R_AARCH64_NONE;
299
1
        }
300
2
      }
301
2
      if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
302
2
        if (IsILP32) {
303
2
          return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
304
2
        } else {
305
0
          Ctx.reportError(Fixup.getLoc(),
306
0
                          "LP64 4 byte TLSDESC load/store relocation "
307
0
                          "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
308
0
          return ELF::R_AARCH64_NONE;
309
0
        }
310
0
      }
311
0
312
0
      Ctx.reportError(Fixup.getLoc(),
313
0
                      "invalid fixup for 32-bit load/store instruction "
314
0
                      "fixup_aarch64_ldst_imm12_scale4");
315
0
      return ELF::R_AARCH64_NONE;
316
145
    case AArch64::fixup_aarch64_ldst_imm12_scale8:
317
145
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC28
)
318
28
        return R_CLS(LDST64_ABS_LO12_NC);
319
117
      if (SymLoc == AArch64MCExpr::VK_GOT && 
IsNC61
) {
320
61
        if (!IsILP32) {
321
59
          return ELF::R_AARCH64_LD64_GOT_LO12_NC;
322
59
        } else {
323
2
          Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
324
2
                                          "relocation not supported (LP64 eqv: "
325
2
                                          "LD64_GOT_LO12_NC)");
326
2
          return ELF::R_AARCH64_NONE;
327
2
        }
328
56
      }
329
56
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
!IsNC8
)
330
4
        return R_CLS(TLSLD_LDST64_DTPREL_LO12);
331
52
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
IsNC4
)
332
4
        return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
333
48
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
!IsNC9
)
334
4
        return R_CLS(TLSLE_LDST64_TPREL_LO12);
335
44
      if (SymLoc == AArch64MCExpr::VK_TPREL && 
IsNC5
)
336
5
        return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
337
39
      if (SymLoc == AArch64MCExpr::VK_GOTTPREL && 
IsNC18
) {
338
18
        if (!IsILP32) {
339
14
          return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
340
14
        } else {
341
4
          Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
342
4
                                          "relocation not supported (LP64 eqv: "
343
4
                                          "TLSIE_LD64_GOTTPREL_LO12_NC)");
344
4
          return ELF::R_AARCH64_NONE;
345
4
        }
346
21
      }
347
21
      if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
348
21
        if (!IsILP32) {
349
21
          return ELF::R_AARCH64_TLSDESC_LD64_LO12;
350
21
        } else {
351
0
          Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
352
0
                                          "relocation not supported (LP64 eqv: "
353
0
                                          "TLSDESC_LD64_LO12)");
354
0
          return ELF::R_AARCH64_NONE;
355
0
        }
356
0
      }
357
0
      Ctx.reportError(Fixup.getLoc(),
358
0
                      "invalid fixup for 64-bit load/store instruction");
359
0
      return ELF::R_AARCH64_NONE;
360
21
    case AArch64::fixup_aarch64_ldst_imm12_scale16:
361
21
      if (SymLoc == AArch64MCExpr::VK_ABS && 
IsNC8
)
362
8
        return R_CLS(LDST128_ABS_LO12_NC);
363
13
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
!IsNC6
)
364
3
        return R_CLS(TLSLD_LDST128_DTPREL_LO12);
365
10
      if (SymLoc == AArch64MCExpr::VK_DTPREL && 
IsNC3
)
366
3
        return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
367
7
      if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
368
3
        return R_CLS(TLSLE_LDST128_TPREL_LO12);
369
4
      if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
370
4
        return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
371
0
372
0
      Ctx.reportError(Fixup.getLoc(),
373
0
                      "invalid fixup for 128-bit load/store instruction");
374
0
      return ELF::R_AARCH64_NONE;
375
0
    // ILP32 case not reached here, tested with isNonILP32reloc
376
145
    case AArch64::fixup_aarch64_movw:
377
145
      if (RefKind == AArch64MCExpr::VK_ABS_G3)
378
8
        return ELF::R_AARCH64_MOVW_UABS_G3;
379
137
      if (RefKind == AArch64MCExpr::VK_ABS_G2)
380
4
        return ELF::R_AARCH64_MOVW_UABS_G2;
381
133
      if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
382
7
        return ELF::R_AARCH64_MOVW_SABS_G2;
383
126
      if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
384
5
        return ELF::R_AARCH64_MOVW_UABS_G2_NC;
385
121
      if (RefKind == AArch64MCExpr::VK_ABS_G1)
386
5
        return R_CLS(MOVW_UABS_G1);
387
116
      if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
388
6
        return ELF::R_AARCH64_MOVW_SABS_G1;
389
110
      if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
390
5
        return ELF::R_AARCH64_MOVW_UABS_G1_NC;
391
105
      if (RefKind == AArch64MCExpr::VK_ABS_G0)
392
4
        return R_CLS(MOVW_UABS_G0);
393
101
      if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
394
6
        return R_CLS(MOVW_SABS_G0);
395
95
      if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
396
5
        return R_CLS(MOVW_UABS_G0_NC);
397
90
      if (RefKind == AArch64MCExpr::VK_PREL_G3)
398
5
        return ELF::R_AARCH64_MOVW_PREL_G3;
399
85
      if (RefKind == AArch64MCExpr::VK_PREL_G2)
400
6
        return ELF::R_AARCH64_MOVW_PREL_G2;
401
79
      if (RefKind == AArch64MCExpr::VK_PREL_G2_NC)
402
3
        return ELF::R_AARCH64_MOVW_PREL_G2_NC;
403
76
      if (RefKind == AArch64MCExpr::VK_PREL_G1)
404
5
        return R_CLS(MOVW_PREL_G1);
405
71
      if (RefKind == AArch64MCExpr::VK_PREL_G1_NC)
406
3
        return ELF::R_AARCH64_MOVW_PREL_G1_NC;
407
68
      if (RefKind == AArch64MCExpr::VK_PREL_G0)
408
5
        return R_CLS(MOVW_PREL_G0);
409
63
      if (RefKind == AArch64MCExpr::VK_PREL_G0_NC)
410
3
        return R_CLS(MOVW_PREL_G0_NC);
411
60
      if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
412
6
        return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
413
54
      if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
414
7
        return R_CLS(TLSLD_MOVW_DTPREL_G1);
415
47
      if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
416
4
        return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
417
43
      if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
418
7
        return R_CLS(TLSLD_MOVW_DTPREL_G0);
419
36
      if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
420
4
        return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
421
32
      if (RefKind == AArch64MCExpr::VK_TPREL_G2)
422
4
        return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
423
28
      if (RefKind == AArch64MCExpr::VK_TPREL_G1)
424
7
        return R_CLS(TLSLE_MOVW_TPREL_G1);
425
21
      if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
426
4
        return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
427
17
      if (RefKind == AArch64MCExpr::VK_TPREL_G0)
428
7
        return R_CLS(TLSLE_MOVW_TPREL_G0);
429
10
      if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
430
4
        return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
431
6
      if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
432
3
        return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
433
3
      if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
434
3
        return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
435
0
      Ctx.reportError(Fixup.getLoc(),
436
0
                      "invalid fixup for movz/movk instruction");
437
0
      return ELF::R_AARCH64_NONE;
438
19
    case AArch64::fixup_aarch64_tlsdesc_call:
439
19
      return R_CLS(TLSDESC_CALL);
440
0
    default:
441
0
      Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
442
0
      return ELF::R_AARCH64_NONE;
443
0
    }
444
0
  }
445
0
446
0
  llvm_unreachable("Unimplemented fixup -> relocation");
447
0
}
448
449
std::unique_ptr<MCObjectTargetWriter>
450
4.31k
llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
451
4.31k
  return llvm::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
452
4.31k
}