Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
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//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AArch64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
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#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "../Utils/AArch64BaseInfo.h"
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namespace llvm {
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class AArch64InstPrinter : public MCInstPrinter {
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public:
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  AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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                     const MCRegisterInfo &MRI);
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  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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                 const MCSubtargetInfo &STI) override;
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  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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  // Autogenerated by tblgen.
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  virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
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                                raw_ostream &O);
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  virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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                               raw_ostream &O);
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  virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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                                       unsigned PrintMethodIdx,
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                                       const MCSubtargetInfo &STI,
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                                       raw_ostream &O);
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  virtual StringRef getRegName(unsigned RegNo) const {
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    return getRegisterName(RegNo);
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  }
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  static const char *getRegisterName(unsigned RegNo,
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                                     unsigned AltIdx = AArch64::NoRegAltName);
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protected:
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  bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
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                     raw_ostream &O);
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  // Operand printers
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  void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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                    raw_ostream &O);
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  void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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                raw_ostream &O);
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  void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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                   raw_ostream &O);
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  template <typename T> void printImmSVE(T Value, raw_ostream &O);
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  void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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                           raw_ostream &O);
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  template <int Amount>
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  void printPostIncOperand(const MCInst *MI, unsigned OpNo,
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<64>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<32>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<16>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<8>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<1>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<4>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<2>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<48>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<24>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<3>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<12>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
void llvm::AArch64InstPrinter::printPostIncOperand<6>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                           const MCSubtargetInfo &STI, raw_ostream &O) {
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    printPostIncOperand(MI, OpNo, Amount, O);
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  }
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  void printVRegOperand(const MCInst *MI, unsigned OpNo,
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                        const MCSubtargetInfo &STI, raw_ostream &O);
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  void printSysCROperand(const MCInst *MI, unsigned OpNo,
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                         const MCSubtargetInfo &STI, raw_ostream &O);
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  void printAddSubImm(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  template <typename T>
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  void printLogicalImm(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O);
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  void printShifter(const MCInst *MI, unsigned OpNum,
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                    const MCSubtargetInfo &STI, raw_ostream &O);
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  void printShiftedRegister(const MCInst *MI, unsigned OpNum,
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                            const MCSubtargetInfo &STI, raw_ostream &O);
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  void printExtendedRegister(const MCInst *MI, unsigned OpNum,
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                             const MCSubtargetInfo &STI, raw_ostream &O);
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  void printArithExtend(const MCInst *MI, unsigned OpNum,
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                        const MCSubtargetInfo &STI, raw_ostream &O);
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  void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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                      char SrcRegKind, unsigned Width);
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  template <char SrcRegKind, unsigned Width>
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  void printMemExtend(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)119, 8u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)120, 8u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)119, 64u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)120, 64u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)119, 16u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)120, 16u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)119, 128u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)120, 128u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)119, 32u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
void llvm::AArch64InstPrinter::printMemExtend<(char)120, 32u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                      const MCSubtargetInfo &STI, raw_ostream &O) {
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    printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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  }
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  template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix>
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  void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
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                               const MCSubtargetInfo &STI, raw_ostream &O);
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  void printCondCode(const MCInst *MI, unsigned OpNum,
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                     const MCSubtargetInfo &STI, raw_ostream &O);
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  void printInverseCondCode(const MCInst *MI, unsigned OpNum,
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                            const MCSubtargetInfo &STI, raw_ostream &O);
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  void printAlignedLabel(const MCInst *MI, unsigned OpNum,
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                         const MCSubtargetInfo &STI, raw_ostream &O);
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  void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
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                         raw_ostream &O);
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  void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
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                        raw_ostream &O);
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  template <int Scale>
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  void printUImm12Offset(const MCInst *MI, unsigned OpNum,
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
void llvm::AArch64InstPrinter::printUImm12Offset<1>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
void llvm::AArch64InstPrinter::printUImm12Offset<8>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
void llvm::AArch64InstPrinter::printUImm12Offset<2>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
void llvm::AArch64InstPrinter::printUImm12Offset<16>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
void llvm::AArch64InstPrinter::printUImm12Offset<4>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
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                         const MCSubtargetInfo &STI, raw_ostream &O) {
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    printUImm12Offset(MI, OpNum, Scale, O);
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  }
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  template <int BitWidth>
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  void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
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                        const MCSubtargetInfo &STI, raw_ostream &O) {
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    printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
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  }
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  void printAMNoIndex(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  template <int Scale>
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  void printImmScale(const MCInst *MI, unsigned OpNum,
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                     const MCSubtargetInfo &STI, raw_ostream &O);
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  template <bool IsSVEPrefetch = false>
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  void printPrefetchOp(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O);
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  void printPSBHintOp(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  void printBTIHintOp(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  void printFPImmOperand(const MCInst *MI, unsigned OpNum,
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                         const MCSubtargetInfo &STI, raw_ostream &O);
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  void printVectorList(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O,
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                       StringRef LayoutSuffix);
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  /// Print a list of vector registers where the type suffix is implicit
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  /// (i.e. attached to the instruction rather than the registers).
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  void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
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                                      const MCSubtargetInfo &STI,
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                                      raw_ostream &O);
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  template <unsigned NumLanes, char LaneKind>
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  void printTypedVectorList(const MCInst *MI, unsigned OpNum,
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                            const MCSubtargetInfo &STI, raw_ostream &O);
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  void printVectorIndex(const MCInst *MI, unsigned OpNum,
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                        const MCSubtargetInfo &STI, raw_ostream &O);
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  void printAdrpLabel(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  void printBarrierOption(const MCInst *MI, unsigned OpNum,
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                          const MCSubtargetInfo &STI, raw_ostream &O);
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  void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
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                              const MCSubtargetInfo &STI, raw_ostream &O);
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  void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
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                              const MCSubtargetInfo &STI, raw_ostream &O);
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  void printSystemPStateField(const MCInst *MI, unsigned OpNum,
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                              const MCSubtargetInfo &STI, raw_ostream &O);
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  void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
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                              const MCSubtargetInfo &STI, raw_ostream &O);
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  template<int64_t Angle, int64_t Remainder>
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  void printComplexRotationOp(const MCInst *MI, unsigned OpNo,
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                            const MCSubtargetInfo &STI, raw_ostream &O);
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  template<unsigned size>
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  void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
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                                    const MCSubtargetInfo &STI,
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                                    raw_ostream &O);
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  template <typename T>
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  void printImm8OptLsl(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O);
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  template <typename T>
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  void printSVELogicalImm(const MCInst *MI, unsigned OpNum,
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                          const MCSubtargetInfo &STI, raw_ostream &O);
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  void printSVEPattern(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O);
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  template <char = 0>
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  void printSVERegOp(const MCInst *MI, unsigned OpNum,
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                    const MCSubtargetInfo &STI, raw_ostream &O);
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  void printGPR64as32(const MCInst *MI, unsigned OpNum,
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                      const MCSubtargetInfo &STI, raw_ostream &O);
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  template <int Width>
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  void printZPRasFPR(const MCInst *MI, unsigned OpNum,
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                     const MCSubtargetInfo &STI, raw_ostream &O);
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  template <unsigned ImmIs0, unsigned ImmIs1>
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  void printExactFPImm(const MCInst *MI, unsigned OpNum,
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                       const MCSubtargetInfo &STI, raw_ostream &O);
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};
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class AArch64AppleInstPrinter : public AArch64InstPrinter {
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public:
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  AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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                          const MCRegisterInfo &MRI);
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  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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                 const MCSubtargetInfo &STI) override;
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  void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
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                        raw_ostream &O) override;
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  bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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                       raw_ostream &O) override;
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  void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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                               unsigned PrintMethodIdx,
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                               const MCSubtargetInfo &STI,
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                               raw_ostream &O) override;
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  StringRef getRegName(unsigned RegNo) const override {
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    return getRegisterName(RegNo);
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  }
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  static const char *getRegisterName(unsigned RegNo,
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                                     unsigned AltIdx = AArch64::NoRegAltName);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H