Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file provides AArch64 specific target descriptions.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "AArch64MCTargetDesc.h"
14
#include "AArch64ELFStreamer.h"
15
#include "AArch64MCAsmInfo.h"
16
#include "AArch64WinCOFFStreamer.h"
17
#include "MCTargetDesc/AArch64AddressingModes.h"
18
#include "MCTargetDesc/AArch64InstPrinter.h"
19
#include "TargetInfo/AArch64TargetInfo.h"
20
#include "llvm/DebugInfo/CodeView/CodeView.h"
21
#include "llvm/MC/MCAsmBackend.h"
22
#include "llvm/MC/MCCodeEmitter.h"
23
#include "llvm/MC/MCInstrAnalysis.h"
24
#include "llvm/MC/MCInstrInfo.h"
25
#include "llvm/MC/MCObjectWriter.h"
26
#include "llvm/MC/MCRegisterInfo.h"
27
#include "llvm/MC/MCStreamer.h"
28
#include "llvm/MC/MCSubtargetInfo.h"
29
#include "llvm/Support/Endian.h"
30
#include "llvm/Support/ErrorHandling.h"
31
#include "llvm/Support/TargetRegistry.h"
32
33
using namespace llvm;
34
35
#define GET_INSTRINFO_MC_DESC
36
#define GET_INSTRINFO_MC_HELPERS
37
#include "AArch64GenInstrInfo.inc"
38
39
#define GET_SUBTARGETINFO_MC_DESC
40
#include "AArch64GenSubtargetInfo.inc"
41
42
#define GET_REGINFO_MC_DESC
43
#include "AArch64GenRegisterInfo.inc"
44
45
14.5k
static MCInstrInfo *createAArch64MCInstrInfo() {
46
14.5k
  MCInstrInfo *X = new MCInstrInfo();
47
14.5k
  InitAArch64MCInstrInfo(X);
48
14.5k
  return X;
49
14.5k
}
50
51
static MCSubtargetInfo *
52
14.3k
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
53
14.3k
  if (CPU.empty())
54
6.55k
    CPU = "generic";
55
14.3k
56
14.3k
  return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
57
14.3k
}
58
59
23.4k
void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
60
23.4k
  // Mapping from CodeView to MC register id.
61
23.4k
  static const struct {
62
23.4k
    codeview::RegisterId CVReg;
63
23.4k
    MCPhysReg Reg;
64
23.4k
  } RegMap[] = {
65
23.4k
      {codeview::RegisterId::ARM64_W0, AArch64::W0},
66
23.4k
      {codeview::RegisterId::ARM64_W1, AArch64::W1},
67
23.4k
      {codeview::RegisterId::ARM64_W2, AArch64::W2},
68
23.4k
      {codeview::RegisterId::ARM64_W3, AArch64::W3},
69
23.4k
      {codeview::RegisterId::ARM64_W4, AArch64::W4},
70
23.4k
      {codeview::RegisterId::ARM64_W5, AArch64::W5},
71
23.4k
      {codeview::RegisterId::ARM64_W6, AArch64::W6},
72
23.4k
      {codeview::RegisterId::ARM64_W7, AArch64::W7},
73
23.4k
      {codeview::RegisterId::ARM64_W8, AArch64::W8},
74
23.4k
      {codeview::RegisterId::ARM64_W9, AArch64::W9},
75
23.4k
      {codeview::RegisterId::ARM64_W10, AArch64::W10},
76
23.4k
      {codeview::RegisterId::ARM64_W11, AArch64::W11},
77
23.4k
      {codeview::RegisterId::ARM64_W12, AArch64::W12},
78
23.4k
      {codeview::RegisterId::ARM64_W13, AArch64::W13},
79
23.4k
      {codeview::RegisterId::ARM64_W14, AArch64::W14},
80
23.4k
      {codeview::RegisterId::ARM64_W15, AArch64::W15},
81
23.4k
      {codeview::RegisterId::ARM64_W16, AArch64::W16},
82
23.4k
      {codeview::RegisterId::ARM64_W17, AArch64::W17},
83
23.4k
      {codeview::RegisterId::ARM64_W18, AArch64::W18},
84
23.4k
      {codeview::RegisterId::ARM64_W19, AArch64::W19},
85
23.4k
      {codeview::RegisterId::ARM64_W20, AArch64::W20},
86
23.4k
      {codeview::RegisterId::ARM64_W21, AArch64::W21},
87
23.4k
      {codeview::RegisterId::ARM64_W22, AArch64::W22},
88
23.4k
      {codeview::RegisterId::ARM64_W23, AArch64::W23},
89
23.4k
      {codeview::RegisterId::ARM64_W24, AArch64::W24},
90
23.4k
      {codeview::RegisterId::ARM64_W25, AArch64::W25},
91
23.4k
      {codeview::RegisterId::ARM64_W26, AArch64::W26},
92
23.4k
      {codeview::RegisterId::ARM64_W27, AArch64::W27},
93
23.4k
      {codeview::RegisterId::ARM64_W28, AArch64::W28},
94
23.4k
      {codeview::RegisterId::ARM64_W29, AArch64::W29},
95
23.4k
      {codeview::RegisterId::ARM64_W30, AArch64::W30},
96
23.4k
      {codeview::RegisterId::ARM64_WZR, AArch64::WZR},
97
23.4k
      {codeview::RegisterId::ARM64_X0, AArch64::X0},
98
23.4k
      {codeview::RegisterId::ARM64_X1, AArch64::X1},
99
23.4k
      {codeview::RegisterId::ARM64_X2, AArch64::X2},
100
23.4k
      {codeview::RegisterId::ARM64_X3, AArch64::X3},
101
23.4k
      {codeview::RegisterId::ARM64_X4, AArch64::X4},
102
23.4k
      {codeview::RegisterId::ARM64_X5, AArch64::X5},
103
23.4k
      {codeview::RegisterId::ARM64_X6, AArch64::X6},
104
23.4k
      {codeview::RegisterId::ARM64_X7, AArch64::X7},
105
23.4k
      {codeview::RegisterId::ARM64_X8, AArch64::X8},
106
23.4k
      {codeview::RegisterId::ARM64_X9, AArch64::X9},
107
23.4k
      {codeview::RegisterId::ARM64_X10, AArch64::X10},
108
23.4k
      {codeview::RegisterId::ARM64_X11, AArch64::X11},
109
23.4k
      {codeview::RegisterId::ARM64_X12, AArch64::X12},
110
23.4k
      {codeview::RegisterId::ARM64_X13, AArch64::X13},
111
23.4k
      {codeview::RegisterId::ARM64_X14, AArch64::X14},
112
23.4k
      {codeview::RegisterId::ARM64_X15, AArch64::X15},
113
23.4k
      {codeview::RegisterId::ARM64_X16, AArch64::X16},
114
23.4k
      {codeview::RegisterId::ARM64_X17, AArch64::X17},
115
23.4k
      {codeview::RegisterId::ARM64_X18, AArch64::X18},
116
23.4k
      {codeview::RegisterId::ARM64_X19, AArch64::X19},
117
23.4k
      {codeview::RegisterId::ARM64_X20, AArch64::X20},
118
23.4k
      {codeview::RegisterId::ARM64_X21, AArch64::X21},
119
23.4k
      {codeview::RegisterId::ARM64_X22, AArch64::X22},
120
23.4k
      {codeview::RegisterId::ARM64_X23, AArch64::X23},
121
23.4k
      {codeview::RegisterId::ARM64_X24, AArch64::X24},
122
23.4k
      {codeview::RegisterId::ARM64_X25, AArch64::X25},
123
23.4k
      {codeview::RegisterId::ARM64_X26, AArch64::X26},
124
23.4k
      {codeview::RegisterId::ARM64_X27, AArch64::X27},
125
23.4k
      {codeview::RegisterId::ARM64_X28, AArch64::X28},
126
23.4k
      {codeview::RegisterId::ARM64_FP, AArch64::FP},
127
23.4k
      {codeview::RegisterId::ARM64_LR, AArch64::LR},
128
23.4k
      {codeview::RegisterId::ARM64_SP, AArch64::SP},
129
23.4k
      {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
130
23.4k
      {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV},
131
23.4k
      {codeview::RegisterId::ARM64_S0, AArch64::S0},
132
23.4k
      {codeview::RegisterId::ARM64_S1, AArch64::S1},
133
23.4k
      {codeview::RegisterId::ARM64_S2, AArch64::S2},
134
23.4k
      {codeview::RegisterId::ARM64_S3, AArch64::S3},
135
23.4k
      {codeview::RegisterId::ARM64_S4, AArch64::S4},
136
23.4k
      {codeview::RegisterId::ARM64_S5, AArch64::S5},
137
23.4k
      {codeview::RegisterId::ARM64_S6, AArch64::S6},
138
23.4k
      {codeview::RegisterId::ARM64_S7, AArch64::S7},
139
23.4k
      {codeview::RegisterId::ARM64_S8, AArch64::S8},
140
23.4k
      {codeview::RegisterId::ARM64_S9, AArch64::S9},
141
23.4k
      {codeview::RegisterId::ARM64_S10, AArch64::S10},
142
23.4k
      {codeview::RegisterId::ARM64_S11, AArch64::S11},
143
23.4k
      {codeview::RegisterId::ARM64_S12, AArch64::S12},
144
23.4k
      {codeview::RegisterId::ARM64_S13, AArch64::S13},
145
23.4k
      {codeview::RegisterId::ARM64_S14, AArch64::S14},
146
23.4k
      {codeview::RegisterId::ARM64_S15, AArch64::S15},
147
23.4k
      {codeview::RegisterId::ARM64_S16, AArch64::S16},
148
23.4k
      {codeview::RegisterId::ARM64_S17, AArch64::S17},
149
23.4k
      {codeview::RegisterId::ARM64_S18, AArch64::S18},
150
23.4k
      {codeview::RegisterId::ARM64_S19, AArch64::S19},
151
23.4k
      {codeview::RegisterId::ARM64_S20, AArch64::S20},
152
23.4k
      {codeview::RegisterId::ARM64_S21, AArch64::S21},
153
23.4k
      {codeview::RegisterId::ARM64_S22, AArch64::S22},
154
23.4k
      {codeview::RegisterId::ARM64_S23, AArch64::S23},
155
23.4k
      {codeview::RegisterId::ARM64_S24, AArch64::S24},
156
23.4k
      {codeview::RegisterId::ARM64_S25, AArch64::S25},
157
23.4k
      {codeview::RegisterId::ARM64_S26, AArch64::S26},
158
23.4k
      {codeview::RegisterId::ARM64_S27, AArch64::S27},
159
23.4k
      {codeview::RegisterId::ARM64_S28, AArch64::S28},
160
23.4k
      {codeview::RegisterId::ARM64_S29, AArch64::S29},
161
23.4k
      {codeview::RegisterId::ARM64_S30, AArch64::S30},
162
23.4k
      {codeview::RegisterId::ARM64_S31, AArch64::S31},
163
23.4k
      {codeview::RegisterId::ARM64_D0, AArch64::D0},
164
23.4k
      {codeview::RegisterId::ARM64_D1, AArch64::D1},
165
23.4k
      {codeview::RegisterId::ARM64_D2, AArch64::D2},
166
23.4k
      {codeview::RegisterId::ARM64_D3, AArch64::D3},
167
23.4k
      {codeview::RegisterId::ARM64_D4, AArch64::D4},
168
23.4k
      {codeview::RegisterId::ARM64_D5, AArch64::D5},
169
23.4k
      {codeview::RegisterId::ARM64_D6, AArch64::D6},
170
23.4k
      {codeview::RegisterId::ARM64_D7, AArch64::D7},
171
23.4k
      {codeview::RegisterId::ARM64_D8, AArch64::D8},
172
23.4k
      {codeview::RegisterId::ARM64_D9, AArch64::D9},
173
23.4k
      {codeview::RegisterId::ARM64_D10, AArch64::D10},
174
23.4k
      {codeview::RegisterId::ARM64_D11, AArch64::D11},
175
23.4k
      {codeview::RegisterId::ARM64_D12, AArch64::D12},
176
23.4k
      {codeview::RegisterId::ARM64_D13, AArch64::D13},
177
23.4k
      {codeview::RegisterId::ARM64_D14, AArch64::D14},
178
23.4k
      {codeview::RegisterId::ARM64_D15, AArch64::D15},
179
23.4k
      {codeview::RegisterId::ARM64_D16, AArch64::D16},
180
23.4k
      {codeview::RegisterId::ARM64_D17, AArch64::D17},
181
23.4k
      {codeview::RegisterId::ARM64_D18, AArch64::D18},
182
23.4k
      {codeview::RegisterId::ARM64_D19, AArch64::D19},
183
23.4k
      {codeview::RegisterId::ARM64_D20, AArch64::D20},
184
23.4k
      {codeview::RegisterId::ARM64_D21, AArch64::D21},
185
23.4k
      {codeview::RegisterId::ARM64_D22, AArch64::D22},
186
23.4k
      {codeview::RegisterId::ARM64_D23, AArch64::D23},
187
23.4k
      {codeview::RegisterId::ARM64_D24, AArch64::D24},
188
23.4k
      {codeview::RegisterId::ARM64_D25, AArch64::D25},
189
23.4k
      {codeview::RegisterId::ARM64_D26, AArch64::D26},
190
23.4k
      {codeview::RegisterId::ARM64_D27, AArch64::D27},
191
23.4k
      {codeview::RegisterId::ARM64_D28, AArch64::D28},
192
23.4k
      {codeview::RegisterId::ARM64_D29, AArch64::D29},
193
23.4k
      {codeview::RegisterId::ARM64_D30, AArch64::D30},
194
23.4k
      {codeview::RegisterId::ARM64_D31, AArch64::D31},
195
23.4k
      {codeview::RegisterId::ARM64_Q0, AArch64::Q0},
196
23.4k
      {codeview::RegisterId::ARM64_Q1, AArch64::Q1},
197
23.4k
      {codeview::RegisterId::ARM64_Q2, AArch64::Q2},
198
23.4k
      {codeview::RegisterId::ARM64_Q3, AArch64::Q3},
199
23.4k
      {codeview::RegisterId::ARM64_Q4, AArch64::Q4},
200
23.4k
      {codeview::RegisterId::ARM64_Q5, AArch64::Q5},
201
23.4k
      {codeview::RegisterId::ARM64_Q6, AArch64::Q6},
202
23.4k
      {codeview::RegisterId::ARM64_Q7, AArch64::Q7},
203
23.4k
      {codeview::RegisterId::ARM64_Q8, AArch64::Q8},
204
23.4k
      {codeview::RegisterId::ARM64_Q9, AArch64::Q9},
205
23.4k
      {codeview::RegisterId::ARM64_Q10, AArch64::Q10},
206
23.4k
      {codeview::RegisterId::ARM64_Q11, AArch64::Q11},
207
23.4k
      {codeview::RegisterId::ARM64_Q12, AArch64::Q12},
208
23.4k
      {codeview::RegisterId::ARM64_Q13, AArch64::Q13},
209
23.4k
      {codeview::RegisterId::ARM64_Q14, AArch64::Q14},
210
23.4k
      {codeview::RegisterId::ARM64_Q15, AArch64::Q15},
211
23.4k
      {codeview::RegisterId::ARM64_Q16, AArch64::Q16},
212
23.4k
      {codeview::RegisterId::ARM64_Q17, AArch64::Q17},
213
23.4k
      {codeview::RegisterId::ARM64_Q18, AArch64::Q18},
214
23.4k
      {codeview::RegisterId::ARM64_Q19, AArch64::Q19},
215
23.4k
      {codeview::RegisterId::ARM64_Q20, AArch64::Q20},
216
23.4k
      {codeview::RegisterId::ARM64_Q21, AArch64::Q21},
217
23.4k
      {codeview::RegisterId::ARM64_Q22, AArch64::Q22},
218
23.4k
      {codeview::RegisterId::ARM64_Q23, AArch64::Q23},
219
23.4k
      {codeview::RegisterId::ARM64_Q24, AArch64::Q24},
220
23.4k
      {codeview::RegisterId::ARM64_Q25, AArch64::Q25},
221
23.4k
      {codeview::RegisterId::ARM64_Q26, AArch64::Q26},
222
23.4k
      {codeview::RegisterId::ARM64_Q27, AArch64::Q27},
223
23.4k
      {codeview::RegisterId::ARM64_Q28, AArch64::Q28},
224
23.4k
      {codeview::RegisterId::ARM64_Q29, AArch64::Q29},
225
23.4k
      {codeview::RegisterId::ARM64_Q30, AArch64::Q30},
226
23.4k
      {codeview::RegisterId::ARM64_Q31, AArch64::Q31},
227
23.4k
228
23.4k
  };
229
3.82M
  for (unsigned I = 0; I < array_lengthof(RegMap); 
++I3.80M
)
230
3.80M
    MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
231
23.4k
}
232
233
14.3k
static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
234
14.3k
  MCRegisterInfo *X = new MCRegisterInfo();
235
14.3k
  InitAArch64MCRegisterInfo(X, AArch64::LR);
236
14.3k
  AArch64_MC::initLLVMToCVRegMapping(X);
237
14.3k
  return X;
238
14.3k
}
239
240
static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
241
14.3k
                                         const Triple &TheTriple) {
242
14.3k
  MCAsmInfo *MAI;
243
14.3k
  if (TheTriple.isOSBinFormatMachO())
244
7.92k
    MAI = new AArch64MCAsmInfoDarwin();
245
6.43k
  else if (TheTriple.isWindowsMSVCEnvironment())
246
111
    MAI = new AArch64MCAsmInfoMicrosoftCOFF();
247
6.32k
  else if (TheTriple.isOSBinFormatCOFF())
248
19
    MAI = new AArch64MCAsmInfoGNUCOFF();
249
6.30k
  else {
250
6.30k
    assert(TheTriple.isOSBinFormatELF() && "Invalid target");
251
6.30k
    MAI = new AArch64MCAsmInfoELF(TheTriple);
252
6.30k
  }
253
14.3k
254
14.3k
  // Initial state of the frame pointer is SP.
255
14.3k
  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
256
14.3k
  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
257
14.3k
  MAI->addInitialFrameState(Inst);
258
14.3k
259
14.3k
  return MAI;
260
14.3k
}
261
262
static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
263
                                                 unsigned SyntaxVariant,
264
                                                 const MCAsmInfo &MAI,
265
                                                 const MCInstrInfo &MII,
266
4.64k
                                                 const MCRegisterInfo &MRI) {
267
4.64k
  if (SyntaxVariant == 0)
268
4.19k
    return new AArch64InstPrinter(MAI, MII, MRI);
269
447
  if (SyntaxVariant == 1)
270
447
    return new AArch64AppleInstPrinter(MAI, MII, MRI);
271
0
272
0
  return nullptr;
273
0
}
274
275
static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
276
                                     std::unique_ptr<MCAsmBackend> &&TAB,
277
                                     std::unique_ptr<MCObjectWriter> &&OW,
278
                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
279
1.29k
                                     bool RelaxAll) {
280
1.29k
  return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
281
1.29k
                                  std::move(Emitter), RelaxAll);
282
1.29k
}
283
284
static MCStreamer *createMachOStreamer(MCContext &Ctx,
285
                                       std::unique_ptr<MCAsmBackend> &&TAB,
286
                                       std::unique_ptr<MCObjectWriter> &&OW,
287
                                       std::unique_ptr<MCCodeEmitter> &&Emitter,
288
                                       bool RelaxAll,
289
7.33k
                                       bool DWARFMustBeAtTheEnd) {
290
7.33k
  return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
291
7.33k
                             std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
292
7.33k
                             /*LabelSections*/ true);
293
7.33k
}
294
295
static MCStreamer *
296
createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
297
                      std::unique_ptr<MCObjectWriter> &&OW,
298
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
299
31
                      bool IncrementalLinkerCompatible) {
300
31
  return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
301
31
                                      std::move(Emitter), RelaxAll,
302
31
                                      IncrementalLinkerCompatible);
303
31
}
304
305
namespace {
306
307
class AArch64MCInstrAnalysis : public MCInstrAnalysis {
308
public:
309
1.22k
  AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
310
311
  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
312
275
                      uint64_t &Target) const override {
313
275
    // Search for a PC-relative argument.
314
275
    // This will handle instructions like bcc (where the first argument is the
315
275
    // condition code) and cbz (where it is a register).
316
275
    const auto &Desc = Info->get(Inst.getOpcode());
317
409
    for (unsigned i = 0, e = Inst.getNumOperands(); i != e; 
i++134
) {
318
371
      if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
319
237
        int64_t Imm = Inst.getOperand(i).getImm() * 4;
320
237
        Target = Addr + Imm;
321
237
        return true;
322
237
      }
323
371
    }
324
275
    
return false38
;
325
275
  }
326
327
  std::vector<std::pair<uint64_t, uint64_t>>
328
  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
329
                 uint64_t GotPltSectionVA,
330
27
                 const Triple &TargetTriple) const override {
331
27
    // Do a lightweight parsing of PLT entries.
332
27
    std::vector<std::pair<uint64_t, uint64_t>> Result;
333
307
    for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
334
280
         Byte += 4) {
335
280
      uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
336
280
      uint64_t Off = 0;
337
280
      // Check for optional bti c that prefixes adrp in BTI enabled entries
338
280
      if (Insn == 0xd503245f) {
339
18
         Off = 4;
340
18
         Insn = support::endian::read32le(PltContents.data() + Byte + Off);
341
18
      }
342
280
      // Check for adrp.
343
280
      if ((Insn & 0x9f000000) != 0x90000000)
344
217
        continue;
345
63
      Off += 4;
346
63
      uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
347
63
            (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
348
63
      uint32_t Insn2 =
349
63
          support::endian::read32le(PltContents.data() + Byte + Off);
350
63
      // Check for: ldr Xt, [Xn, #pimm].
351
63
      if (Insn2 >> 22 == 0x3e5) {
352
63
        Imm += ((Insn2 >> 10) & 0xfff) << 3;
353
63
        Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
354
63
        Byte += 4;
355
63
      }
356
63
    }
357
27
    return Result;
358
27
  }
359
};
360
361
} // end anonymous namespace
362
363
1.22k
static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
364
1.22k
  return new AArch64MCInstrAnalysis(Info);
365
1.22k
}
366
367
// Force static initialization.
368
96.4k
extern "C" void LLVMInitializeAArch64TargetMC() {
369
96.4k
  for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
370
96.4k
                    &getTheAArch64_32Target(), &getTheARM64Target(),
371
482k
                    &getTheARM64_32Target()}) {
372
482k
    // Register the MC asm info.
373
482k
    RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
374
482k
375
482k
    // Register the MC instruction info.
376
482k
    TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
377
482k
378
482k
    // Register the MC register info.
379
482k
    TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
380
482k
381
482k
    // Register the MC subtarget info.
382
482k
    TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
383
482k
384
482k
    // Register the MC instruction analyzer.
385
482k
    TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
386
482k
387
482k
    // Register the MC Code Emitter
388
482k
    TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
389
482k
390
482k
    // Register the obj streamers.
391
482k
    TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
392
482k
    TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
393
482k
    TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
394
482k
395
482k
    // Register the obj target streamer.
396
482k
    TargetRegistry::RegisterObjectTargetStreamer(
397
482k
        *T, createAArch64ObjectTargetStreamer);
398
482k
399
482k
    // Register the asm streamer.
400
482k
    TargetRegistry::RegisterAsmTargetStreamer(*T,
401
482k
                                              createAArch64AsmTargetStreamer);
402
482k
    // Register the MCInstPrinter.
403
482k
    TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
404
482k
  }
405
96.4k
406
96.4k
  // Register the asm backend.
407
96.4k
  for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
408
96.4k
                    &getTheARM64Target(), &getTheARM64_32Target()})
409
385k
    TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
410
96.4k
  TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
411
96.4k
                                       createAArch64beAsmBackend);
412
96.4k
}