Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
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//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for AArch64.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64BaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Regex.h"
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using namespace llvm;
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namespace llvm {
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  namespace AArch64AT {
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#define GET_AT_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64DB {
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#define GET_DB_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64DC {
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#define GET_DC_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64IC {
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#define GET_IC_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64ISB {
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#define GET_ISB_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64TSB {
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#define GET_TSB_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64PRCTX {
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#define GET_PRCTX_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64PRFM {
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#define GET_PRFM_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64SVEPRFM {
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#define GET_SVEPRFM_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64SVEPredPattern {
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#define GET_SVEPREDPAT_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64ExactFPImm {
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#define GET_EXACTFPIMM_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64PState {
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#define GET_PSTATE_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64PSBHint {
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#define GET_PSB_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64BTIHint {
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#define GET_BTI_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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namespace llvm {
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  namespace AArch64SysReg {
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#define GET_SYSREG_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}
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uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
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  // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
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  Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
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  std::string UpperName = Name.upper();
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  SmallVector<StringRef, 5> Ops;
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  if (!GenericRegPattern.match(UpperName, &Ops))
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    return -1;
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  uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
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  uint32_t Bits;
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  Ops[1].getAsInteger(10, Op0);
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  Ops[2].getAsInteger(10, Op1);
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  Ops[3].getAsInteger(10, CRn);
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  Ops[4].getAsInteger(10, CRm);
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  Ops[5].getAsInteger(10, Op2);
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  Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
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  return Bits;
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}
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std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
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  assert(Bits < 0x10000);
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  uint32_t Op0 = (Bits >> 14) & 0x3;
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  uint32_t Op1 = (Bits >> 11) & 0x7;
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  uint32_t CRn = (Bits >> 7) & 0xf;
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  uint32_t CRm = (Bits >> 3) & 0xf;
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  uint32_t Op2 = Bits & 0x7;
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  return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
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         utostr(CRm) + "_" + utostr(Op2);
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}
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namespace llvm {
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  namespace AArch64TLBI {
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#define GET_TLBI_IMPL
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#include "AArch64GenSystemOperands.inc"
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  }
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}