Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
Line
Count
Source (jump to first uncovered line)
1
//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains small standalone helper functions and enum definitions for
10
// the AArch64 target useful for the compiler back-end and the MC libraries.
11
// As such, it deliberately does not include references to LLVM core
12
// code gen types, passes, etc..
13
//
14
//===----------------------------------------------------------------------===//
15
16
#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17
#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19
// FIXME: Is it easiest to fix this layering violation by moving the .inc
20
// #includes from AArch64MCTargetDesc.h to here?
21
#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22
#include "llvm/ADT/STLExtras.h"
23
#include "llvm/ADT/StringSwitch.h"
24
#include "llvm/MC/SubtargetFeature.h"
25
#include "llvm/Support/ErrorHandling.h"
26
27
namespace llvm {
28
29
496
inline static unsigned getWRegFromXReg(unsigned Reg) {
30
496
  switch (Reg) {
31
496
  
case AArch64::X0: return AArch64::W0115
;
32
496
  
case AArch64::X1: return AArch64::W126
;
33
496
  
case AArch64::X2: return AArch64::W27
;
34
496
  
case AArch64::X3: return AArch64::W36
;
35
496
  
case AArch64::X4: return AArch64::W40
;
36
496
  
case AArch64::X5: return AArch64::W52
;
37
496
  
case AArch64::X6: return AArch64::W60
;
38
496
  
case AArch64::X7: return AArch64::W70
;
39
496
  
case AArch64::X8: return AArch64::W818
;
40
496
  
case AArch64::X9: return AArch64::W95
;
41
496
  
case AArch64::X10: return AArch64::W102
;
42
496
  
case AArch64::X11: return AArch64::W110
;
43
496
  
case AArch64::X12: return AArch64::W120
;
44
496
  
case AArch64::X13: return AArch64::W130
;
45
496
  
case AArch64::X14: return AArch64::W140
;
46
496
  
case AArch64::X15: return AArch64::W150
;
47
496
  
case AArch64::X16: return AArch64::W160
;
48
496
  
case AArch64::X17: return AArch64::W170
;
49
496
  
case AArch64::X18: return AArch64::W180
;
50
496
  
case AArch64::X19: return AArch64::W190
;
51
496
  
case AArch64::X20: return AArch64::W203
;
52
496
  
case AArch64::X21: return AArch64::W210
;
53
496
  
case AArch64::X22: return AArch64::W221
;
54
496
  
case AArch64::X23: return AArch64::W230
;
55
496
  
case AArch64::X24: return AArch64::W240
;
56
496
  
case AArch64::X25: return AArch64::W250
;
57
496
  
case AArch64::X26: return AArch64::W260
;
58
496
  
case AArch64::X27: return AArch64::W270
;
59
496
  
case AArch64::X28: return AArch64::W280
;
60
496
  
case AArch64::FP: return AArch64::W290
;
61
496
  
case AArch64::LR: return AArch64::W305
;
62
496
  
case AArch64::SP: return AArch64::WSP1
;
63
496
  
case AArch64::XZR: return AArch64::WZR18
;
64
287
  }
65
287
  // For anything else, return it unchanged.
66
287
  return Reg;
67
287
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::getWRegFromXReg(unsigned int)
AArch64AsmPrinter.cpp:llvm::getWRegFromXReg(unsigned int)
Line
Count
Source
29
24
inline static unsigned getWRegFromXReg(unsigned Reg) {
30
24
  switch (Reg) {
31
24
  
case AArch64::X0: return AArch64::W01
;
32
24
  
case AArch64::X1: return AArch64::W10
;
33
24
  
case AArch64::X2: return AArch64::W20
;
34
24
  
case AArch64::X3: return AArch64::W30
;
35
24
  
case AArch64::X4: return AArch64::W40
;
36
24
  
case AArch64::X5: return AArch64::W50
;
37
24
  
case AArch64::X6: return AArch64::W60
;
38
24
  
case AArch64::X7: return AArch64::W70
;
39
24
  
case AArch64::X8: return AArch64::W80
;
40
24
  
case AArch64::X9: return AArch64::W90
;
41
24
  
case AArch64::X10: return AArch64::W100
;
42
24
  
case AArch64::X11: return AArch64::W110
;
43
24
  
case AArch64::X12: return AArch64::W120
;
44
24
  
case AArch64::X13: return AArch64::W130
;
45
24
  
case AArch64::X14: return AArch64::W140
;
46
24
  
case AArch64::X15: return AArch64::W150
;
47
24
  
case AArch64::X16: return AArch64::W160
;
48
24
  
case AArch64::X17: return AArch64::W170
;
49
24
  
case AArch64::X18: return AArch64::W180
;
50
24
  
case AArch64::X19: return AArch64::W190
;
51
24
  
case AArch64::X20: return AArch64::W200
;
52
24
  
case AArch64::X21: return AArch64::W210
;
53
24
  
case AArch64::X22: return AArch64::W220
;
54
24
  
case AArch64::X23: return AArch64::W230
;
55
24
  
case AArch64::X24: return AArch64::W240
;
56
24
  
case AArch64::X25: return AArch64::W250
;
57
24
  
case AArch64::X26: return AArch64::W260
;
58
24
  
case AArch64::X27: return AArch64::W270
;
59
24
  
case AArch64::X28: return AArch64::W280
;
60
24
  
case AArch64::FP: return AArch64::W290
;
61
24
  
case AArch64::LR: return AArch64::W300
;
62
24
  
case AArch64::SP: return AArch64::WSP0
;
63
24
  
case AArch64::XZR: return AArch64::WZR0
;
64
23
  }
65
23
  // For anything else, return it unchanged.
66
23
  return Reg;
67
23
}
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::getWRegFromXReg(unsigned int)
AArch64AsmParser.cpp:llvm::getWRegFromXReg(unsigned int)
Line
Count
Source
29
8
inline static unsigned getWRegFromXReg(unsigned Reg) {
30
8
  switch (Reg) {
31
8
  
case AArch64::X0: return AArch64::W01
;
32
8
  
case AArch64::X1: return AArch64::W12
;
33
8
  
case AArch64::X2: return AArch64::W21
;
34
8
  
case AArch64::X3: return AArch64::W31
;
35
8
  
case AArch64::X4: return AArch64::W40
;
36
8
  
case AArch64::X5: return AArch64::W51
;
37
8
  
case AArch64::X6: return AArch64::W60
;
38
8
  
case AArch64::X7: return AArch64::W70
;
39
8
  
case AArch64::X8: return AArch64::W80
;
40
8
  
case AArch64::X9: return AArch64::W90
;
41
8
  
case AArch64::X10: return AArch64::W100
;
42
8
  
case AArch64::X11: return AArch64::W110
;
43
8
  
case AArch64::X12: return AArch64::W120
;
44
8
  
case AArch64::X13: return AArch64::W130
;
45
8
  
case AArch64::X14: return AArch64::W140
;
46
8
  
case AArch64::X15: return AArch64::W150
;
47
8
  
case AArch64::X16: return AArch64::W160
;
48
8
  
case AArch64::X17: return AArch64::W170
;
49
8
  
case AArch64::X18: return AArch64::W180
;
50
8
  
case AArch64::X19: return AArch64::W190
;
51
8
  
case AArch64::X20: return AArch64::W200
;
52
8
  
case AArch64::X21: return AArch64::W210
;
53
8
  
case AArch64::X22: return AArch64::W220
;
54
8
  
case AArch64::X23: return AArch64::W230
;
55
8
  
case AArch64::X24: return AArch64::W240
;
56
8
  
case AArch64::X25: return AArch64::W250
;
57
8
  
case AArch64::X26: return AArch64::W260
;
58
8
  
case AArch64::X27: return AArch64::W270
;
59
8
  
case AArch64::X28: return AArch64::W280
;
60
8
  
case AArch64::FP: return AArch64::W290
;
61
8
  
case AArch64::LR: return AArch64::W300
;
62
8
  
case AArch64::SP: return AArch64::WSP1
;
63
8
  
case AArch64::XZR: return AArch64::WZR1
;
64
0
  }
65
0
  // For anything else, return it unchanged.
66
0
  return Reg;
67
0
}
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::getWRegFromXReg(unsigned int)
AArch64InstPrinter.cpp:llvm::getWRegFromXReg(unsigned int)
Line
Count
Source
29
464
inline static unsigned getWRegFromXReg(unsigned Reg) {
30
464
  switch (Reg) {
31
464
  
case AArch64::X0: return AArch64::W0113
;
32
464
  
case AArch64::X1: return AArch64::W124
;
33
464
  
case AArch64::X2: return AArch64::W26
;
34
464
  
case AArch64::X3: return AArch64::W35
;
35
464
  
case AArch64::X4: return AArch64::W40
;
36
464
  
case AArch64::X5: return AArch64::W51
;
37
464
  
case AArch64::X6: return AArch64::W60
;
38
464
  
case AArch64::X7: return AArch64::W70
;
39
464
  
case AArch64::X8: return AArch64::W818
;
40
464
  
case AArch64::X9: return AArch64::W95
;
41
464
  
case AArch64::X10: return AArch64::W102
;
42
464
  
case AArch64::X11: return AArch64::W110
;
43
464
  
case AArch64::X12: return AArch64::W120
;
44
464
  
case AArch64::X13: return AArch64::W130
;
45
464
  
case AArch64::X14: return AArch64::W140
;
46
464
  
case AArch64::X15: return AArch64::W150
;
47
464
  
case AArch64::X16: return AArch64::W160
;
48
464
  
case AArch64::X17: return AArch64::W170
;
49
464
  
case AArch64::X18: return AArch64::W180
;
50
464
  
case AArch64::X19: return AArch64::W190
;
51
464
  
case AArch64::X20: return AArch64::W203
;
52
464
  
case AArch64::X21: return AArch64::W210
;
53
464
  
case AArch64::X22: return AArch64::W221
;
54
464
  
case AArch64::X23: return AArch64::W230
;
55
464
  
case AArch64::X24: return AArch64::W240
;
56
464
  
case AArch64::X25: return AArch64::W250
;
57
464
  
case AArch64::X26: return AArch64::W260
;
58
464
  
case AArch64::X27: return AArch64::W270
;
59
464
  
case AArch64::X28: return AArch64::W280
;
60
464
  
case AArch64::FP: return AArch64::W290
;
61
464
  
case AArch64::LR: return AArch64::W305
;
62
464
  
case AArch64::SP: return AArch64::WSP0
;
63
464
  
case AArch64::XZR: return AArch64::WZR17
;
64
264
  }
65
264
  // For anything else, return it unchanged.
66
264
  return Reg;
67
264
}
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::getWRegFromXReg(unsigned int)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::getWRegFromXReg(unsigned int)
68
69
251k
inline static unsigned getXRegFromWReg(unsigned Reg) {
70
251k
  switch (Reg) {
71
251k
  
case AArch64::W0: return AArch64::X0148
;
72
251k
  
case AArch64::W1: return AArch64::X121
;
73
251k
  
case AArch64::W2: return AArch64::X24
;
74
251k
  
case AArch64::W3: return AArch64::X31
;
75
251k
  
case AArch64::W4: return AArch64::X40
;
76
251k
  
case AArch64::W5: return AArch64::X50
;
77
251k
  
case AArch64::W6: return AArch64::X60
;
78
251k
  
case AArch64::W7: return AArch64::X70
;
79
251k
  
case AArch64::W8: return AArch64::X83
;
80
251k
  
case AArch64::W9: return AArch64::X90
;
81
251k
  
case AArch64::W10: return AArch64::X102
;
82
251k
  
case AArch64::W11: return AArch64::X110
;
83
251k
  
case AArch64::W12: return AArch64::X120
;
84
251k
  
case AArch64::W13: return AArch64::X130
;
85
251k
  
case AArch64::W14: return AArch64::X140
;
86
251k
  
case AArch64::W15: return AArch64::X150
;
87
251k
  
case AArch64::W16: return AArch64::X160
;
88
251k
  
case AArch64::W17: return AArch64::X170
;
89
251k
  
case AArch64::W18: return AArch64::X180
;
90
251k
  
case AArch64::W19: return AArch64::X1926.5k
;
91
251k
  
case AArch64::W20: return AArch64::X2026.5k
;
92
251k
  
case AArch64::W21: return AArch64::X2118.5k
;
93
251k
  
case AArch64::W22: return AArch64::X2218.5k
;
94
251k
  
case AArch64::W23: return AArch64::X2312.7k
;
95
251k
  
case AArch64::W24: return AArch64::X2412.7k
;
96
251k
  
case AArch64::W25: return AArch64::X259.89k
;
97
251k
  
case AArch64::W26: return AArch64::X269.89k
;
98
251k
  
case AArch64::W27: return AArch64::X277.49k
;
99
251k
  
case AArch64::W28: return AArch64::X287.49k
;
100
251k
  
case AArch64::W29: return AArch64::FP60.6k
;
101
251k
  
case AArch64::W30: return AArch64::LR30.4k
;
102
251k
  
case AArch64::WSP: return AArch64::SP0
;
103
251k
  
case AArch64::WZR: return AArch64::XZR28
;
104
9.32k
  }
105
9.32k
  // For anything else, return it unchanged.
106
9.32k
  return Reg;
107
9.32k
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::getXRegFromWReg(unsigned int)
AArch64AsmPrinter.cpp:llvm::getXRegFromWReg(unsigned int)
Line
Count
Source
69
38
inline static unsigned getXRegFromWReg(unsigned Reg) {
70
38
  switch (Reg) {
71
38
  
case AArch64::W0: return AArch64::X04
;
72
38
  
case AArch64::W1: return AArch64::X11
;
73
38
  
case AArch64::W2: return AArch64::X20
;
74
38
  
case AArch64::W3: return AArch64::X30
;
75
38
  
case AArch64::W4: return AArch64::X40
;
76
38
  
case AArch64::W5: return AArch64::X50
;
77
38
  
case AArch64::W6: return AArch64::X60
;
78
38
  
case AArch64::W7: return AArch64::X70
;
79
38
  
case AArch64::W8: return AArch64::X83
;
80
38
  
case AArch64::W9: return AArch64::X90
;
81
38
  
case AArch64::W10: return AArch64::X102
;
82
38
  
case AArch64::W11: return AArch64::X110
;
83
38
  
case AArch64::W12: return AArch64::X120
;
84
38
  
case AArch64::W13: return AArch64::X130
;
85
38
  
case AArch64::W14: return AArch64::X140
;
86
38
  
case AArch64::W15: return AArch64::X150
;
87
38
  
case AArch64::W16: return AArch64::X160
;
88
38
  
case AArch64::W17: return AArch64::X170
;
89
38
  
case AArch64::W18: return AArch64::X180
;
90
38
  
case AArch64::W19: return AArch64::X190
;
91
38
  
case AArch64::W20: return AArch64::X200
;
92
38
  
case AArch64::W21: return AArch64::X210
;
93
38
  
case AArch64::W22: return AArch64::X220
;
94
38
  
case AArch64::W23: return AArch64::X230
;
95
38
  
case AArch64::W24: return AArch64::X240
;
96
38
  
case AArch64::W25: return AArch64::X250
;
97
38
  
case AArch64::W26: return AArch64::X260
;
98
38
  
case AArch64::W27: return AArch64::X270
;
99
38
  
case AArch64::W28: return AArch64::X280
;
100
38
  
case AArch64::W29: return AArch64::FP0
;
101
38
  
case AArch64::W30: return AArch64::LR0
;
102
38
  
case AArch64::WSP: return AArch64::SP0
;
103
38
  
case AArch64::WZR: return AArch64::XZR4
;
104
24
  }
105
24
  // For anything else, return it unchanged.
106
24
  return Reg;
107
24
}
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::getXRegFromWReg(unsigned int)
AArch64AsmParser.cpp:llvm::getXRegFromWReg(unsigned int)
Line
Count
Source
69
197
inline static unsigned getXRegFromWReg(unsigned Reg) {
70
197
  switch (Reg) {
71
197
  
case AArch64::W0: return AArch64::X0144
;
72
197
  
case AArch64::W1: return AArch64::X119
;
73
197
  
case AArch64::W2: return AArch64::X24
;
74
197
  
case AArch64::W3: return AArch64::X31
;
75
197
  
case AArch64::W4: return AArch64::X40
;
76
197
  
case AArch64::W5: return AArch64::X50
;
77
197
  
case AArch64::W6: return AArch64::X60
;
78
197
  
case AArch64::W7: return AArch64::X70
;
79
197
  
case AArch64::W8: return AArch64::X80
;
80
197
  
case AArch64::W9: return AArch64::X90
;
81
197
  
case AArch64::W10: return AArch64::X100
;
82
197
  
case AArch64::W11: return AArch64::X110
;
83
197
  
case AArch64::W12: return AArch64::X120
;
84
197
  
case AArch64::W13: return AArch64::X130
;
85
197
  
case AArch64::W14: return AArch64::X140
;
86
197
  
case AArch64::W15: return AArch64::X150
;
87
197
  
case AArch64::W16: return AArch64::X160
;
88
197
  
case AArch64::W17: return AArch64::X170
;
89
197
  
case AArch64::W18: return AArch64::X180
;
90
197
  
case AArch64::W19: return AArch64::X190
;
91
197
  
case AArch64::W20: return AArch64::X200
;
92
197
  
case AArch64::W21: return AArch64::X210
;
93
197
  
case AArch64::W22: return AArch64::X220
;
94
197
  
case AArch64::W23: return AArch64::X230
;
95
197
  
case AArch64::W24: return AArch64::X240
;
96
197
  
case AArch64::W25: return AArch64::X250
;
97
197
  
case AArch64::W26: return AArch64::X260
;
98
197
  
case AArch64::W27: return AArch64::X270
;
99
197
  
case AArch64::W28: return AArch64::X280
;
100
197
  
case AArch64::W29: return AArch64::FP0
;
101
197
  
case AArch64::W30: return AArch64::LR1
;
102
197
  
case AArch64::WSP: return AArch64::SP0
;
103
197
  
case AArch64::WZR: return AArch64::XZR24
;
104
4
  }
105
4
  // For anything else, return it unchanged.
106
4
  return Reg;
107
4
}
AArch64AsmBackend.cpp:llvm::getXRegFromWReg(unsigned int)
Line
Count
Source
69
250k
inline static unsigned getXRegFromWReg(unsigned Reg) {
70
250k
  switch (Reg) {
71
250k
  
case AArch64::W0: return AArch64::X00
;
72
250k
  
case AArch64::W1: return AArch64::X11
;
73
250k
  
case AArch64::W2: return AArch64::X20
;
74
250k
  
case AArch64::W3: return AArch64::X30
;
75
250k
  
case AArch64::W4: return AArch64::X40
;
76
250k
  
case AArch64::W5: return AArch64::X50
;
77
250k
  
case AArch64::W6: return AArch64::X60
;
78
250k
  
case AArch64::W7: return AArch64::X70
;
79
250k
  
case AArch64::W8: return AArch64::X80
;
80
250k
  
case AArch64::W9: return AArch64::X90
;
81
250k
  
case AArch64::W10: return AArch64::X100
;
82
250k
  
case AArch64::W11: return AArch64::X110
;
83
250k
  
case AArch64::W12: return AArch64::X120
;
84
250k
  
case AArch64::W13: return AArch64::X130
;
85
250k
  
case AArch64::W14: return AArch64::X140
;
86
250k
  
case AArch64::W15: return AArch64::X150
;
87
250k
  
case AArch64::W16: return AArch64::X160
;
88
250k
  
case AArch64::W17: return AArch64::X170
;
89
250k
  
case AArch64::W18: return AArch64::X180
;
90
250k
  
case AArch64::W19: return AArch64::X1926.5k
;
91
250k
  
case AArch64::W20: return AArch64::X2026.5k
;
92
250k
  
case AArch64::W21: return AArch64::X2118.5k
;
93
250k
  
case AArch64::W22: return AArch64::X2218.5k
;
94
250k
  
case AArch64::W23: return AArch64::X2312.7k
;
95
250k
  
case AArch64::W24: return AArch64::X2412.7k
;
96
250k
  
case AArch64::W25: return AArch64::X259.89k
;
97
250k
  
case AArch64::W26: return AArch64::X269.89k
;
98
250k
  
case AArch64::W27: return AArch64::X277.49k
;
99
250k
  
case AArch64::W28: return AArch64::X287.49k
;
100
250k
  
case AArch64::W29: return AArch64::FP60.6k
;
101
250k
  
case AArch64::W30: return AArch64::LR30.4k
;
102
250k
  
case AArch64::WSP: return AArch64::SP0
;
103
250k
  
case AArch64::WZR: return AArch64::XZR0
;
104
9.29k
  }
105
9.29k
  // For anything else, return it unchanged.
106
9.29k
  return Reg;
107
9.29k
}
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::getXRegFromWReg(unsigned int)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::getXRegFromWReg(unsigned int)
108
109
0
static inline unsigned getBRegFromDReg(unsigned Reg) {
110
0
  switch (Reg) {
111
0
  case AArch64::D0:  return AArch64::B0;
112
0
  case AArch64::D1:  return AArch64::B1;
113
0
  case AArch64::D2:  return AArch64::B2;
114
0
  case AArch64::D3:  return AArch64::B3;
115
0
  case AArch64::D4:  return AArch64::B4;
116
0
  case AArch64::D5:  return AArch64::B5;
117
0
  case AArch64::D6:  return AArch64::B6;
118
0
  case AArch64::D7:  return AArch64::B7;
119
0
  case AArch64::D8:  return AArch64::B8;
120
0
  case AArch64::D9:  return AArch64::B9;
121
0
  case AArch64::D10: return AArch64::B10;
122
0
  case AArch64::D11: return AArch64::B11;
123
0
  case AArch64::D12: return AArch64::B12;
124
0
  case AArch64::D13: return AArch64::B13;
125
0
  case AArch64::D14: return AArch64::B14;
126
0
  case AArch64::D15: return AArch64::B15;
127
0
  case AArch64::D16: return AArch64::B16;
128
0
  case AArch64::D17: return AArch64::B17;
129
0
  case AArch64::D18: return AArch64::B18;
130
0
  case AArch64::D19: return AArch64::B19;
131
0
  case AArch64::D20: return AArch64::B20;
132
0
  case AArch64::D21: return AArch64::B21;
133
0
  case AArch64::D22: return AArch64::B22;
134
0
  case AArch64::D23: return AArch64::B23;
135
0
  case AArch64::D24: return AArch64::B24;
136
0
  case AArch64::D25: return AArch64::B25;
137
0
  case AArch64::D26: return AArch64::B26;
138
0
  case AArch64::D27: return AArch64::B27;
139
0
  case AArch64::D28: return AArch64::B28;
140
0
  case AArch64::D29: return AArch64::B29;
141
0
  case AArch64::D30: return AArch64::B30;
142
0
  case AArch64::D31: return AArch64::B31;
143
0
  }
144
0
  // For anything else, return it unchanged.
145
0
  return Reg;
146
0
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::getBRegFromDReg(unsigned int)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::getBRegFromDReg(unsigned int)
147
148
149
9.62k
static inline unsigned getDRegFromBReg(unsigned Reg) {
150
9.62k
  switch (Reg) {
151
9.62k
  
case AArch64::B0: return AArch64::D00
;
152
9.62k
  
case AArch64::B1: return AArch64::D10
;
153
9.62k
  
case AArch64::B2: return AArch64::D20
;
154
9.62k
  
case AArch64::B3: return AArch64::D30
;
155
9.62k
  
case AArch64::B4: return AArch64::D40
;
156
9.62k
  
case AArch64::B5: return AArch64::D50
;
157
9.62k
  
case AArch64::B6: return AArch64::D60
;
158
9.62k
  
case AArch64::B7: return AArch64::D70
;
159
9.62k
  
case AArch64::B8: return AArch64::D82.51k
;
160
9.62k
  
case AArch64::B9: return AArch64::D92.51k
;
161
9.62k
  
case AArch64::B10: return AArch64::D101.02k
;
162
9.62k
  
case AArch64::B11: return AArch64::D111.02k
;
163
9.62k
  
case AArch64::B12: return AArch64::D12643
;
164
9.62k
  
case AArch64::B13: return AArch64::D13643
;
165
9.62k
  
case AArch64::B14: return AArch64::D14464
;
166
9.62k
  
case AArch64::B15: return AArch64::D15464
;
167
9.62k
  
case AArch64::B16: return AArch64::D160
;
168
9.62k
  
case AArch64::B17: return AArch64::D170
;
169
9.62k
  
case AArch64::B18: return AArch64::D180
;
170
9.62k
  
case AArch64::B19: return AArch64::D190
;
171
9.62k
  
case AArch64::B20: return AArch64::D200
;
172
9.62k
  
case AArch64::B21: return AArch64::D210
;
173
9.62k
  
case AArch64::B22: return AArch64::D220
;
174
9.62k
  
case AArch64::B23: return AArch64::D230
;
175
9.62k
  
case AArch64::B24: return AArch64::D240
;
176
9.62k
  
case AArch64::B25: return AArch64::D250
;
177
9.62k
  
case AArch64::B26: return AArch64::D260
;
178
9.62k
  
case AArch64::B27: return AArch64::D270
;
179
9.62k
  
case AArch64::B28: return AArch64::D280
;
180
9.62k
  
case AArch64::B29: return AArch64::D290
;
181
9.62k
  
case AArch64::B30: return AArch64::D300
;
182
9.62k
  
case AArch64::B31: return AArch64::D310
;
183
332
  }
184
332
  // For anything else, return it unchanged.
185
332
  return Reg;
186
332
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::getDRegFromBReg(unsigned int)
AArch64AsmBackend.cpp:llvm::getDRegFromBReg(unsigned int)
Line
Count
Source
149
9.62k
static inline unsigned getDRegFromBReg(unsigned Reg) {
150
9.62k
  switch (Reg) {
151
9.62k
  
case AArch64::B0: return AArch64::D00
;
152
9.62k
  
case AArch64::B1: return AArch64::D10
;
153
9.62k
  
case AArch64::B2: return AArch64::D20
;
154
9.62k
  
case AArch64::B3: return AArch64::D30
;
155
9.62k
  
case AArch64::B4: return AArch64::D40
;
156
9.62k
  
case AArch64::B5: return AArch64::D50
;
157
9.62k
  
case AArch64::B6: return AArch64::D60
;
158
9.62k
  
case AArch64::B7: return AArch64::D70
;
159
9.62k
  
case AArch64::B8: return AArch64::D82.51k
;
160
9.62k
  
case AArch64::B9: return AArch64::D92.51k
;
161
9.62k
  
case AArch64::B10: return AArch64::D101.02k
;
162
9.62k
  
case AArch64::B11: return AArch64::D111.02k
;
163
9.62k
  
case AArch64::B12: return AArch64::D12643
;
164
9.62k
  
case AArch64::B13: return AArch64::D13643
;
165
9.62k
  
case AArch64::B14: return AArch64::D14464
;
166
9.62k
  
case AArch64::B15: return AArch64::D15464
;
167
9.62k
  
case AArch64::B16: return AArch64::D160
;
168
9.62k
  
case AArch64::B17: return AArch64::D170
;
169
9.62k
  
case AArch64::B18: return AArch64::D180
;
170
9.62k
  
case AArch64::B19: return AArch64::D190
;
171
9.62k
  
case AArch64::B20: return AArch64::D200
;
172
9.62k
  
case AArch64::B21: return AArch64::D210
;
173
9.62k
  
case AArch64::B22: return AArch64::D220
;
174
9.62k
  
case AArch64::B23: return AArch64::D230
;
175
9.62k
  
case AArch64::B24: return AArch64::D240
;
176
9.62k
  
case AArch64::B25: return AArch64::D250
;
177
9.62k
  
case AArch64::B26: return AArch64::D260
;
178
9.62k
  
case AArch64::B27: return AArch64::D270
;
179
9.62k
  
case AArch64::B28: return AArch64::D280
;
180
9.62k
  
case AArch64::B29: return AArch64::D290
;
181
9.62k
  
case AArch64::B30: return AArch64::D300
;
182
9.62k
  
case AArch64::B31: return AArch64::D310
;
183
332
  }
184
332
  // For anything else, return it unchanged.
185
332
  return Reg;
186
332
}
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::getDRegFromBReg(unsigned int)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::getDRegFromBReg(unsigned int)
187
188
18.3M
static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
189
18.3M
  switch (Opcode) {
190
18.3M
  
case AArch64::LDADDAB: 2.70k
case AArch64::LDADDAH:
191
2.70k
  case AArch64::LDADDAW:   case AArch64::LDADDAX:
192
2.70k
  case AArch64::LDADDALB:  case AArch64::LDADDALH:
193
2.70k
  case AArch64::LDADDALW:  case AArch64::LDADDALX:
194
2.70k
  case AArch64::LDCLRAB:   case AArch64::LDCLRAH:
195
2.70k
  case AArch64::LDCLRAW:   case AArch64::LDCLRAX:
196
2.70k
  case AArch64::LDCLRALB:  case AArch64::LDCLRALH:
197
2.70k
  case AArch64::LDCLRALW:  case AArch64::LDCLRALX:
198
2.70k
  case AArch64::LDEORAB:   case AArch64::LDEORAH:
199
2.70k
  case AArch64::LDEORAW:   case AArch64::LDEORAX:
200
2.70k
  case AArch64::LDEORALB:  case AArch64::LDEORALH:
201
2.70k
  case AArch64::LDEORALW:  case AArch64::LDEORALX:
202
2.70k
  case AArch64::LDSETAB:   case AArch64::LDSETAH:
203
2.70k
  case AArch64::LDSETAW:   case AArch64::LDSETAX:
204
2.70k
  case AArch64::LDSETALB:  case AArch64::LDSETALH:
205
2.70k
  case AArch64::LDSETALW:  case AArch64::LDSETALX:
206
2.70k
  case AArch64::LDSMAXAB:  case AArch64::LDSMAXAH:
207
2.70k
  case AArch64::LDSMAXAW:  case AArch64::LDSMAXAX:
208
2.70k
  case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
209
2.70k
  case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
210
2.70k
  case AArch64::LDSMINAB:  case AArch64::LDSMINAH:
211
2.70k
  case AArch64::LDSMINAW:  case AArch64::LDSMINAX:
212
2.70k
  case AArch64::LDSMINALB: case AArch64::LDSMINALH:
213
2.70k
  case AArch64::LDSMINALW: case AArch64::LDSMINALX:
214
2.70k
  case AArch64::LDUMAXAB:  case AArch64::LDUMAXAH:
215
2.70k
  case AArch64::LDUMAXAW:  case AArch64::LDUMAXAX:
216
2.70k
  case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
217
2.70k
  case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
218
2.70k
  case AArch64::LDUMINAB:  case AArch64::LDUMINAH:
219
2.70k
  case AArch64::LDUMINAW:  case AArch64::LDUMINAX:
220
2.70k
  case AArch64::LDUMINALB: case AArch64::LDUMINALH:
221
2.70k
  case AArch64::LDUMINALW: case AArch64::LDUMINALX:
222
2.70k
  case AArch64::SWPAB:     case AArch64::SWPAH:
223
2.70k
  case AArch64::SWPAW:     case AArch64::SWPAX:
224
2.70k
  case AArch64::SWPALB:    case AArch64::SWPALH:
225
2.70k
  case AArch64::SWPALW:    case AArch64::SWPALX:
226
2.70k
    return true;
227
18.3M
  }
228
18.3M
  return false;
229
18.3M
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
AArch64DeadRegisterDefinitionsPass.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Line
Count
Source
188
18.2M
static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
189
18.2M
  switch (Opcode) {
190
18.2M
  
case AArch64::LDADDAB: 1.02k
case AArch64::LDADDAH:
191
1.02k
  case AArch64::LDADDAW:   case AArch64::LDADDAX:
192
1.02k
  case AArch64::LDADDALB:  case AArch64::LDADDALH:
193
1.02k
  case AArch64::LDADDALW:  case AArch64::LDADDALX:
194
1.02k
  case AArch64::LDCLRAB:   case AArch64::LDCLRAH:
195
1.02k
  case AArch64::LDCLRAW:   case AArch64::LDCLRAX:
196
1.02k
  case AArch64::LDCLRALB:  case AArch64::LDCLRALH:
197
1.02k
  case AArch64::LDCLRALW:  case AArch64::LDCLRALX:
198
1.02k
  case AArch64::LDEORAB:   case AArch64::LDEORAH:
199
1.02k
  case AArch64::LDEORAW:   case AArch64::LDEORAX:
200
1.02k
  case AArch64::LDEORALB:  case AArch64::LDEORALH:
201
1.02k
  case AArch64::LDEORALW:  case AArch64::LDEORALX:
202
1.02k
  case AArch64::LDSETAB:   case AArch64::LDSETAH:
203
1.02k
  case AArch64::LDSETAW:   case AArch64::LDSETAX:
204
1.02k
  case AArch64::LDSETALB:  case AArch64::LDSETALH:
205
1.02k
  case AArch64::LDSETALW:  case AArch64::LDSETALX:
206
1.02k
  case AArch64::LDSMAXAB:  case AArch64::LDSMAXAH:
207
1.02k
  case AArch64::LDSMAXAW:  case AArch64::LDSMAXAX:
208
1.02k
  case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
209
1.02k
  case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
210
1.02k
  case AArch64::LDSMINAB:  case AArch64::LDSMINAH:
211
1.02k
  case AArch64::LDSMINAW:  case AArch64::LDSMINAX:
212
1.02k
  case AArch64::LDSMINALB: case AArch64::LDSMINALH:
213
1.02k
  case AArch64::LDSMINALW: case AArch64::LDSMINALX:
214
1.02k
  case AArch64::LDUMAXAB:  case AArch64::LDUMAXAH:
215
1.02k
  case AArch64::LDUMAXAW:  case AArch64::LDUMAXAX:
216
1.02k
  case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
217
1.02k
  case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
218
1.02k
  case AArch64::LDUMINAB:  case AArch64::LDUMINAH:
219
1.02k
  case AArch64::LDUMINAW:  case AArch64::LDUMINAX:
220
1.02k
  case AArch64::LDUMINALB: case AArch64::LDUMINALH:
221
1.02k
  case AArch64::LDUMINALW: case AArch64::LDUMINALX:
222
1.02k
  case AArch64::SWPAB:     case AArch64::SWPAH:
223
1.02k
  case AArch64::SWPAW:     case AArch64::SWPAX:
224
1.02k
  case AArch64::SWPALB:    case AArch64::SWPALH:
225
1.02k
  case AArch64::SWPALW:    case AArch64::SWPALX:
226
1.02k
    return true;
227
18.2M
  }
228
18.2M
  return false;
229
18.2M
}
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
AArch64InstPrinter.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Line
Count
Source
188
139k
static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
189
139k
  switch (Opcode) {
190
139k
  
case AArch64::LDADDAB: 1.68k
case AArch64::LDADDAH:
191
1.68k
  case AArch64::LDADDAW:   case AArch64::LDADDAX:
192
1.68k
  case AArch64::LDADDALB:  case AArch64::LDADDALH:
193
1.68k
  case AArch64::LDADDALW:  case AArch64::LDADDALX:
194
1.68k
  case AArch64::LDCLRAB:   case AArch64::LDCLRAH:
195
1.68k
  case AArch64::LDCLRAW:   case AArch64::LDCLRAX:
196
1.68k
  case AArch64::LDCLRALB:  case AArch64::LDCLRALH:
197
1.68k
  case AArch64::LDCLRALW:  case AArch64::LDCLRALX:
198
1.68k
  case AArch64::LDEORAB:   case AArch64::LDEORAH:
199
1.68k
  case AArch64::LDEORAW:   case AArch64::LDEORAX:
200
1.68k
  case AArch64::LDEORALB:  case AArch64::LDEORALH:
201
1.68k
  case AArch64::LDEORALW:  case AArch64::LDEORALX:
202
1.68k
  case AArch64::LDSETAB:   case AArch64::LDSETAH:
203
1.68k
  case AArch64::LDSETAW:   case AArch64::LDSETAX:
204
1.68k
  case AArch64::LDSETALB:  case AArch64::LDSETALH:
205
1.68k
  case AArch64::LDSETALW:  case AArch64::LDSETALX:
206
1.68k
  case AArch64::LDSMAXAB:  case AArch64::LDSMAXAH:
207
1.68k
  case AArch64::LDSMAXAW:  case AArch64::LDSMAXAX:
208
1.68k
  case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
209
1.68k
  case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
210
1.68k
  case AArch64::LDSMINAB:  case AArch64::LDSMINAH:
211
1.68k
  case AArch64::LDSMINAW:  case AArch64::LDSMINAX:
212
1.68k
  case AArch64::LDSMINALB: case AArch64::LDSMINALH:
213
1.68k
  case AArch64::LDSMINALW: case AArch64::LDSMINALX:
214
1.68k
  case AArch64::LDUMAXAB:  case AArch64::LDUMAXAH:
215
1.68k
  case AArch64::LDUMAXAW:  case AArch64::LDUMAXAX:
216
1.68k
  case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
217
1.68k
  case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
218
1.68k
  case AArch64::LDUMINAB:  case AArch64::LDUMINAH:
219
1.68k
  case AArch64::LDUMINAW:  case AArch64::LDUMINAX:
220
1.68k
  case AArch64::LDUMINALB: case AArch64::LDUMINALH:
221
1.68k
  case AArch64::LDUMINALW: case AArch64::LDUMINALX:
222
1.68k
  case AArch64::SWPAB:     case AArch64::SWPAH:
223
1.68k
  case AArch64::SWPAW:     case AArch64::SWPAX:
224
1.68k
  case AArch64::SWPALB:    case AArch64::SWPALH:
225
1.68k
  case AArch64::SWPALW:    case AArch64::SWPALX:
226
1.68k
    return true;
227
138k
  }
228
138k
  return false;
229
138k
}
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::atomicBarrierDroppedOnZero(unsigned int)
230
231
namespace AArch64CC {
232
233
// The CondCodes constants map directly to the 4-bit encoding of the condition
234
// field for predicated instructions.
235
enum CondCode {  // Meaning (integer)          Meaning (floating-point)
236
  EQ = 0x0,      // Equal                      Equal
237
  NE = 0x1,      // Not equal                  Not equal, or unordered
238
  HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
239
  LO = 0x3,      // Unsigned lower             Less than
240
  MI = 0x4,      // Minus, negative            Less than
241
  PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
242
  VS = 0x6,      // Overflow                   Unordered
243
  VC = 0x7,      // No overflow                Not unordered
244
  HI = 0x8,      // Unsigned higher            Greater than, or unordered
245
  LS = 0x9,      // Unsigned lower or same     Less than or equal
246
  GE = 0xa,      // Greater than or equal      Greater than or equal
247
  LT = 0xb,      // Less than                  Less than, or unordered
248
  GT = 0xc,      // Greater than               Greater than
249
  LE = 0xd,      // Less than or equal         <, ==, or unordered
250
  AL = 0xe,      // Always (unconditional)     Always (unconditional)
251
  NV = 0xf,      // Always (unconditional)     Always (unconditional)
252
  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
253
  Invalid
254
};
255
256
2.98k
inline static const char *getCondCodeName(CondCode Code) {
257
2.98k
  switch (Code) {
258
2.98k
  
default: 0
llvm_unreachable0
("Unknown condition code");
259
2.98k
  
case EQ: return "eq"532
;
260
2.98k
  
case NE: return "ne"717
;
261
2.98k
  
case HS: return "hs"140
;
262
2.98k
  
case LO: return "lo"160
;
263
2.98k
  
case MI: return "mi"116
;
264
2.98k
  
case PL: return "pl"49
;
265
2.98k
  
case VS: return "vs"96
;
266
2.98k
  
case VC: return "vc"65
;
267
2.98k
  
case HI: return "hi"155
;
268
2.98k
  
case LS: return "ls"88
;
269
2.98k
  
case GE: return "ge"150
;
270
2.98k
  
case LT: return "lt"223
;
271
2.98k
  
case GT: return "gt"262
;
272
2.98k
  
case LE: return "le"187
;
273
2.98k
  
case AL: return "al"21
;
274
2.98k
  
case NV: return "nv"20
;
275
2.98k
  }
276
2.98k
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
AArch64InstPrinter.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Line
Count
Source
256
2.98k
inline static const char *getCondCodeName(CondCode Code) {
257
2.98k
  switch (Code) {
258
2.98k
  
default: 0
llvm_unreachable0
("Unknown condition code");
259
2.98k
  
case EQ: return "eq"532
;
260
2.98k
  
case NE: return "ne"717
;
261
2.98k
  
case HS: return "hs"140
;
262
2.98k
  
case LO: return "lo"160
;
263
2.98k
  
case MI: return "mi"116
;
264
2.98k
  
case PL: return "pl"49
;
265
2.98k
  
case VS: return "vs"96
;
266
2.98k
  
case VC: return "vc"65
;
267
2.98k
  
case HI: return "hi"155
;
268
2.98k
  
case LS: return "ls"88
;
269
2.98k
  
case GE: return "ge"150
;
270
2.98k
  
case LT: return "lt"223
;
271
2.98k
  
case GT: return "gt"262
;
272
2.98k
  
case LE: return "le"187
;
273
2.98k
  
case AL: return "al"21
;
274
2.98k
  
case NV: return "nv"20
;
275
2.98k
  }
276
2.98k
}
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::AArch64CC::getCondCodeName(llvm::AArch64CC::CondCode)
277
278
2.38M
inline static CondCode getInvertedCondCode(CondCode Code) {
279
2.38M
  // To reverse a condition it's necessary to only invert the low bit:
280
2.38M
281
2.38M
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
2.38M
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64ConditionalCompares.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
115k
inline static CondCode getInvertedCondCode(CondCode Code) {
279
115k
  // To reverse a condition it's necessary to only invert the low bit:
280
115k
281
115k
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
115k
}
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64FastISel.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
95
inline static CondCode getInvertedCondCode(CondCode Code) {
279
95
  // To reverse a condition it's necessary to only invert the low bit:
280
95
281
95
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
95
}
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64ISelDAGToDAG.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
937
inline static CondCode getInvertedCondCode(CondCode Code) {
279
937
  // To reverse a condition it's necessary to only invert the low bit:
280
937
281
937
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
937
}
AArch64ISelLowering.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
2.88k
inline static CondCode getInvertedCondCode(CondCode Code) {
279
2.88k
  // To reverse a condition it's necessary to only invert the low bit:
280
2.88k
281
2.88k
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
2.88k
}
AArch64InstrInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
2.24M
inline static CondCode getInvertedCondCode(CondCode Code) {
279
2.24M
  // To reverse a condition it's necessary to only invert the low bit:
280
2.24M
281
2.24M
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
2.24M
}
AArch64InstructionSelector.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
14.7k
inline static CondCode getInvertedCondCode(CondCode Code) {
279
14.7k
  // To reverse a condition it's necessary to only invert the low bit:
280
14.7k
281
14.7k
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
14.7k
}
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64SpeculationHardening.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
16
inline static CondCode getInvertedCondCode(CondCode Code) {
279
16
  // To reverse a condition it's necessary to only invert the low bit:
280
16
281
16
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
16
}
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64AsmParser.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
38
inline static CondCode getInvertedCondCode(CondCode Code) {
279
38
  // To reverse a condition it's necessary to only invert the low bit:
280
38
281
38
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
38
}
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
AArch64InstPrinter.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
278
955
inline static CondCode getInvertedCondCode(CondCode Code) {
279
955
  // To reverse a condition it's necessary to only invert the low bit:
280
955
281
955
  return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
282
955
}
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::AArch64CC::getInvertedCondCode(llvm::AArch64CC::CondCode)
283
284
/// Given a condition code, return NZCV flags that would satisfy that condition.
285
/// The flag bits are in the format expected by the ccmp instructions.
286
/// Note that many different flag settings can satisfy a given condition code,
287
/// this function just returns one of them.
288
2.73k
inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
289
2.73k
  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
290
2.73k
  enum { N = 8, Z = 4, C = 2, V = 1 };
291
2.73k
  switch (Code) {
292
2.73k
  
default: 0
llvm_unreachable0
("Unknown condition code");
293
2.73k
  
case EQ: return Z757
; // Z == 1
294
2.73k
  
case NE: return 0440
; // Z == 0
295
2.73k
  
case HS: return C301
; // C == 1
296
2.73k
  
case LO: return 055
; // C == 0
297
2.73k
  
case MI: return N23
; // N == 1
298
2.73k
  
case PL: return 05
; // N == 0
299
2.73k
  
case VS: return V11
; // V == 1
300
2.73k
  
case VC: return 017
; // V == 0
301
2.73k
  
case HI: return C38
; // C == 1 && Z == 0
302
2.73k
  
case LS: return 0266
; // C == 0 || Z == 1
303
2.73k
  
case GE: return 053
; // N == V
304
2.73k
  
case LT: return N410
; // N != V
305
2.73k
  
case GT: return 0310
; // Z == 0 && N == V
306
2.73k
  
case LE: return Z48
; // Z == 1 || N != V
307
2.73k
  }
308
2.73k
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
AArch64ConditionalCompares.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
288
2.58k
inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
289
2.58k
  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
290
2.58k
  enum { N = 8, Z = 4, C = 2, V = 1 };
291
2.58k
  switch (Code) {
292
2.58k
  
default: 0
llvm_unreachable0
("Unknown condition code");
293
2.58k
  
case EQ: return Z696
; // Z == 1
294
2.58k
  
case NE: return 0429
; // Z == 0
295
2.58k
  
case HS: return C301
; // C == 1
296
2.58k
  
case LO: return 055
; // C == 0
297
2.58k
  
case MI: return N0
; // N == 1
298
2.58k
  
case PL: return 03
; // N == 0
299
2.58k
  
case VS: return V0
; // V == 1
300
2.58k
  
case VC: return 017
; // V == 0
301
2.58k
  
case HI: return C37
; // C == 1 && Z == 0
302
2.58k
  
case LS: return 0263
; // C == 0 || Z == 1
303
2.58k
  
case GE: return 049
; // N == V
304
2.58k
  
case LT: return N406
; // N != V
305
2.58k
  
case GT: return 0290
; // Z == 0 && N == V
306
2.58k
  
case LE: return Z38
; // Z == 1 || N != V
307
2.58k
  }
308
2.58k
}
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
AArch64ISelLowering.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Line
Count
Source
288
150
inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
289
150
  // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
290
150
  enum { N = 8, Z = 4, C = 2, V = 1 };
291
150
  switch (Code) {
292
150
  
default: 0
llvm_unreachable0
("Unknown condition code");
293
150
  
case EQ: return Z61
; // Z == 1
294
150
  
case NE: return 011
; // Z == 0
295
150
  
case HS: return C0
; // C == 1
296
150
  
case LO: return 00
; // C == 0
297
150
  
case MI: return N23
; // N == 1
298
150
  
case PL: return 02
; // N == 0
299
150
  
case VS: return V11
; // V == 1
300
150
  
case VC: return 00
; // V == 0
301
150
  
case HI: return C1
; // C == 1 && Z == 0
302
150
  
case LS: return 03
; // C == 0 || Z == 1
303
150
  
case GE: return 04
; // N == V
304
150
  
case LT: return N4
; // N != V
305
150
  
case GT: return 020
; // Z == 0 && N == V
306
150
  
case LE: return Z10
; // Z == 1 || N != V
307
150
  }
308
150
}
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::AArch64CC::getNZCVToSatisfyCondCode(llvm::AArch64CC::CondCode)
309
} // end namespace AArch64CC
310
311
struct SysAlias {
312
  const char *Name;
313
  uint16_t Encoding;
314
  FeatureBitset FeaturesRequired;
315
316
4.54M
  SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
317
  SysAlias (const char *N, uint16_t E, FeatureBitset F) :
318
16.9M
    Name(N), Encoding(E), FeaturesRequired(F) {};
319
320
1.13k
  bool haveFeatures(FeatureBitset ActiveFeatures) const {
321
1.13k
    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
322
1.13k
  }
323
324
150
  FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
325
};
326
327
struct SysAliasReg : SysAlias {
328
  bool NeedsReg;
329
358k
  SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
330
  SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) : SysAlias(N, E, F),
331
9.44M
    NeedsReg(R) {};
332
};
333
334
namespace AArch64AT{
335
  struct AT : SysAlias {
336
    using SysAlias::SysAlias;
337
  };
338
  #define GET_AT_DECL
339
  #include "AArch64GenSystemOperands.inc"
340
}
341
342
namespace AArch64DB {
343
  struct DB : SysAlias {
344
    using SysAlias::SysAlias;
345
  };
346
  #define GET_DB_DECL
347
  #include "AArch64GenSystemOperands.inc"
348
}
349
350
namespace  AArch64DC {
351
  struct DC : SysAlias {
352
    using SysAlias::SysAlias;
353
  };
354
  #define GET_DC_DECL
355
  #include "AArch64GenSystemOperands.inc"
356
}
357
358
namespace  AArch64IC {
359
  struct IC : SysAliasReg {
360
    using SysAliasReg::SysAliasReg;
361
  };
362
  #define GET_IC_DECL
363
  #include "AArch64GenSystemOperands.inc"
364
}
365
366
namespace  AArch64ISB {
367
  struct ISB : SysAlias {
368
    using SysAlias::SysAlias;
369
  };
370
  #define GET_ISB_DECL
371
  #include "AArch64GenSystemOperands.inc"
372
}
373
374
namespace  AArch64TSB {
375
  struct TSB : SysAlias {
376
    using SysAlias::SysAlias;
377
  };
378
  #define GET_TSB_DECL
379
  #include "AArch64GenSystemOperands.inc"
380
}
381
382
namespace AArch64PRFM {
383
  struct PRFM : SysAlias {
384
    using SysAlias::SysAlias;
385
  };
386
  #define GET_PRFM_DECL
387
  #include "AArch64GenSystemOperands.inc"
388
}
389
390
namespace AArch64SVEPRFM {
391
  struct SVEPRFM : SysAlias {
392
    using SysAlias::SysAlias;
393
  };
394
#define GET_SVEPRFM_DECL
395
#include "AArch64GenSystemOperands.inc"
396
}
397
398
namespace AArch64SVEPredPattern {
399
  struct SVEPREDPAT {
400
    const char *Name;
401
    uint16_t Encoding;
402
  };
403
#define GET_SVEPREDPAT_DECL
404
#include "AArch64GenSystemOperands.inc"
405
}
406
407
namespace AArch64ExactFPImm {
408
  struct ExactFPImm {
409
    const char *Name;
410
    int Enum;
411
    const char *Repr;
412
  };
413
#define GET_EXACTFPIMM_DECL
414
#include "AArch64GenSystemOperands.inc"
415
}
416
417
namespace AArch64PState {
418
  struct PState : SysAlias{
419
    using SysAlias::SysAlias;
420
  };
421
  #define GET_PSTATE_DECL
422
  #include "AArch64GenSystemOperands.inc"
423
}
424
425
namespace AArch64PSBHint {
426
  struct PSB : SysAlias {
427
    using SysAlias::SysAlias;
428
  };
429
  #define GET_PSB_DECL
430
  #include "AArch64GenSystemOperands.inc"
431
}
432
433
namespace AArch64BTIHint {
434
  struct BTI : SysAlias {
435
    using SysAlias::SysAlias;
436
  };
437
  #define GET_BTI_DECL
438
  #include "AArch64GenSystemOperands.inc"
439
}
440
441
namespace AArch64SE {
442
    enum ShiftExtSpecifiers {
443
        Invalid = -1,
444
        LSL,
445
        MSL,
446
        LSR,
447
        ASR,
448
        ROR,
449
450
        UXTB,
451
        UXTH,
452
        UXTW,
453
        UXTX,
454
455
        SXTB,
456
        SXTH,
457
        SXTW,
458
        SXTX
459
    };
460
}
461
462
namespace AArch64Layout {
463
    enum VectorLayout {
464
        Invalid = -1,
465
        VL_8B,
466
        VL_4H,
467
        VL_2S,
468
        VL_1D,
469
470
        VL_16B,
471
        VL_8H,
472
        VL_4S,
473
        VL_2D,
474
475
        // Bare layout for the 128-bit vector
476
        // (only show ".b", ".h", ".s", ".d" without vector number)
477
        VL_B,
478
        VL_H,
479
        VL_S,
480
        VL_D
481
    };
482
}
483
484
inline static const char *
485
0
AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
486
0
  switch (Layout) {
487
0
  case AArch64Layout::VL_8B:  return ".8b";
488
0
  case AArch64Layout::VL_4H:  return ".4h";
489
0
  case AArch64Layout::VL_2S:  return ".2s";
490
0
  case AArch64Layout::VL_1D:  return ".1d";
491
0
  case AArch64Layout::VL_16B:  return ".16b";
492
0
  case AArch64Layout::VL_8H:  return ".8h";
493
0
  case AArch64Layout::VL_4S:  return ".4s";
494
0
  case AArch64Layout::VL_2D:  return ".2d";
495
0
  case AArch64Layout::VL_B:  return ".b";
496
0
  case AArch64Layout::VL_H:  return ".h";
497
0
  case AArch64Layout::VL_S:  return ".s";
498
0
  case AArch64Layout::VL_D:  return ".d";
499
0
  default: llvm_unreachable("Unknown Vector Layout");
500
0
  }
501
0
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::AArch64VectorLayoutToString(llvm::AArch64Layout::VectorLayout)
502
503
inline static AArch64Layout::VectorLayout
504
0
AArch64StringToVectorLayout(StringRef LayoutStr) {
505
0
  return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
506
0
             .Case(".8b", AArch64Layout::VL_8B)
507
0
             .Case(".4h", AArch64Layout::VL_4H)
508
0
             .Case(".2s", AArch64Layout::VL_2S)
509
0
             .Case(".1d", AArch64Layout::VL_1D)
510
0
             .Case(".16b", AArch64Layout::VL_16B)
511
0
             .Case(".8h", AArch64Layout::VL_8H)
512
0
             .Case(".4s", AArch64Layout::VL_4S)
513
0
             .Case(".2d", AArch64Layout::VL_2D)
514
0
             .Case(".b", AArch64Layout::VL_B)
515
0
             .Case(".h", AArch64Layout::VL_H)
516
0
             .Case(".s", AArch64Layout::VL_S)
517
0
             .Case(".d", AArch64Layout::VL_D)
518
0
             .Default(AArch64Layout::Invalid);
519
0
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ConditionalCompares.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ExpandImm.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64A53Fix835769.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ConditionOptimizer.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64RedundantCopyElimination.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64MCInstLower.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64PromoteConstant.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64PBQPRegAlloc.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64AsmBackend.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64InstPrinter.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64MCCodeEmitter.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64MCTargetDesc.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
Unexecuted instantiation: AArch64BaseInfo.cpp:llvm::AArch64StringToVectorLayout(llvm::StringRef)
520
521
namespace AArch64SysReg {
522
  struct SysReg {
523
    const char *Name;
524
    unsigned Encoding;
525
    bool Readable;
526
    bool Writeable;
527
    FeatureBitset FeaturesRequired;
528
529
8.25k
    bool haveFeatures(FeatureBitset ActiveFeatures) const {
530
8.25k
      return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
531
8.25k
    }
532
  };
533
534
  #define GET_SYSREG_DECL
535
  #include "AArch64GenSystemOperands.inc"
536
537
  const SysReg *lookupSysRegByName(StringRef);
538
  const SysReg *lookupSysRegByEncoding(uint16_t);
539
540
  uint32_t parseGenericRegister(StringRef Name);
541
  std::string genericRegisterString(uint32_t Bits);
542
}
543
544
namespace AArch64TLBI {
545
  struct TLBI : SysAliasReg {
546
    using SysAliasReg::SysAliasReg;
547
  };
548
  #define GET_TLBI_DECL
549
  #include "AArch64GenSystemOperands.inc"
550
}
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namespace AArch64PRCTX {
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  struct PRCTX : SysAliasReg {
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    using SysAliasReg::SysAliasReg;
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  };
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  #define GET_PRCTX_DECL
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  #include "AArch64GenSystemOperands.inc"
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}
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namespace AArch64II {
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  /// Target Operand Flag enum.
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  enum TOF {
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    //===------------------------------------------------------------------===//
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    // AArch64 Specific MachineOperand flags.
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    MO_NO_FLAG,
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    MO_FRAGMENT = 0x7,
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    /// MO_PAGE - A symbol operand with this flag represents the pc-relative
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    /// offset of the 4K page containing the symbol.  This is used with the
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    /// ADRP instruction.
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    MO_PAGE = 1,
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    /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
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    /// that symbol within a 4K page.  This offset is added to the page address
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    /// to produce the complete address.
578
    MO_PAGEOFF = 2,
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    /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
581
    /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
582
    MO_G3 = 3,
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    /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
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    /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
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    MO_G2 = 4,
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    /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
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    /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
590
    MO_G1 = 5,
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    /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
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    /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
594
    MO_G0 = 6,
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    /// MO_HI12 - This flag indicates that a symbol operand represents the bits
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    /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
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    /// by-12-bits instruction.
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    MO_HI12 = 7,
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    /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
602
    /// reference is actually to the ".refptrp.FOO" symbol.  This is used for
603
    /// stub symbols on windows.
604
    MO_COFFSTUB = 0x8,
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    /// MO_GOT - This flag indicates that a symbol operand represents the
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    /// address of the GOT entry for the symbol, rather than the address of
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    /// the symbol itself.
609
    MO_GOT = 0x10,
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    /// MO_NC - Indicates whether the linker is expected to check the symbol
612
    /// reference for overflow. For example in an ADRP/ADD pair of relocations
613
    /// the ADRP usually does check, but not the ADD.
614
    MO_NC = 0x20,
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    /// MO_TLS - Indicates that the operand being accessed is some kind of
617
    /// thread-local symbol. On Darwin, only one type of thread-local access
618
    /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
619
    /// referee will affect interpretation.
620
    MO_TLS = 0x40,
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    /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
623
    /// to the symbol is for an import stub.  This is used for DLL import
624
    /// storage class indication on Windows.
625
    MO_DLLIMPORT = 0x80,
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    /// MO_S - Indicates that the bits of the symbol operand represented by
628
    /// MO_G0 etc are signed.
629
    MO_S = 0x100,
630
  };
631
} // end namespace AArch64II
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} // end namespace llvm
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#endif