Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
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//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AMDGPURegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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namespace AMDGPU {
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enum PartialMappingIdx {
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  None = - 1,
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  PM_SGPR1  = 2,
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  PM_SGPR16 = 6,
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  PM_SGPR32 = 7,
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  PM_SGPR64 = 8,
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  PM_SGPR128 = 9,
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  PM_SGPR256 = 10,
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  PM_SGPR512 = 11,
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  PM_VGPR1  = 12,
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  PM_VGPR16 = 16,
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  PM_VGPR32 = 17,
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  PM_VGPR64 = 18,
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  PM_VGPR128 = 19,
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  PM_VGPR256 = 20,
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  PM_VGPR512 = 21,
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  PM_SGPR96 = 22,
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  PM_VGPR96 = 23
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};
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const RegisterBankInfo::PartialMapping PartMappings[] {
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  // StartIdx, Length, RegBank
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  {0, 1,  SCCRegBank},
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  {0, 1,  VCCRegBank},
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  {0, 1,  SGPRRegBank}, // SGPR begin
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  {0, 16, SGPRRegBank},
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  {0, 32, SGPRRegBank},
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  {0, 64, SGPRRegBank},
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  {0, 128, SGPRRegBank},
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  {0, 256, SGPRRegBank},
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  {0, 512, SGPRRegBank},
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  {0, 1,  VGPRRegBank}, // VGPR begin
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  {0, 16, VGPRRegBank},
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  {0, 32, VGPRRegBank},
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  {0, 64, VGPRRegBank},
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  {0, 128, VGPRRegBank},
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  {0, 256, VGPRRegBank},
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  {0, 512, VGPRRegBank},
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  {0, 96, SGPRRegBank},
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  {0, 96, VGPRRegBank},
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};
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const RegisterBankInfo::ValueMapping ValMappings[] {
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  // SCC
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  {&PartMappings[0], 1},
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  // VCC
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  {&PartMappings[1], 1},
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  // SGPRs
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  {&PartMappings[2], 1},
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  {nullptr, 0}, // Illegal power of 2 sizes
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  {nullptr, 0},
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  {nullptr, 0},
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  {&PartMappings[3], 1},
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  {&PartMappings[4], 1},
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  {&PartMappings[5], 1},
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  {&PartMappings[6], 1},
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  {&PartMappings[7], 1},
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  {&PartMappings[8], 1},
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    // VGPRs
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  {&PartMappings[9], 1},
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  {nullptr, 0},
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  {nullptr, 0},
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  {nullptr, 0},
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  {&PartMappings[10], 1},
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  {&PartMappings[11], 1},
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  {&PartMappings[12], 1},
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  {&PartMappings[13], 1},
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  {&PartMappings[14], 1},
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  {&PartMappings[15], 1},
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  {&PartMappings[16], 1},
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  {&PartMappings[17], 1}
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};
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const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
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     /*32-bit op*/ {0, 32, SGPRRegBank},
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   /*2x32-bit op*/ {0, 32, SGPRRegBank},
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                   {32, 32, SGPRRegBank},
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/*<2x32-bit> op*/  {0, 64, SGPRRegBank},
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    /*32-bit op*/  {0, 32, VGPRRegBank},
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  /*2x32-bit op*/  {0, 32, VGPRRegBank},
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                   {32, 32, VGPRRegBank},
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};
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// For some instructions which can operate 64-bit only for the scalar version.
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const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
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  /*32-bit sgpr*/     {&SGPROnly64BreakDown[0], 1},
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  /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
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  /*64-bit sgpr */    {&SGPROnly64BreakDown[3], 1},
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  /*32-bit vgpr*/     {&SGPROnly64BreakDown[4], 1},
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  /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
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};
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enum ValueMappingIdx {
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  SCCStartIdx = 0,
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  SGPRStartIdx = 2,
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  VGPRStartIdx = 12
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};
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const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
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                                                      unsigned Size) {
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  unsigned Idx;
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  switch (Size) {
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  case 1:
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    if (BankID == AMDGPU::SCCRegBankID)
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      return &ValMappings[0];
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    if (BankID == AMDGPU::VCCRegBankID)
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      return &ValMappings[1];
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    // 1-bit values not from a compare etc.
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    Idx = BankID == AMDGPU::SGPRRegBankID ? 
PM_SGPR1382
:
PM_VGPR1124
;
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    break;
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  case 96:
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    assert(BankID != AMDGPU::VCCRegBankID);
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    Idx = BankID == AMDGPU::SGPRRegBankID ? 
PM_SGPR960
: PM_VGPR96;
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    break;
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  default:
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    assert(BankID != AMDGPU::VCCRegBankID);
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    Idx = BankID == AMDGPU::VGPRRegBankID ? 
VGPRStartIdx4.06k
:
SGPRStartIdx4.22k
;
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    Idx += Log2_32_Ceil(Size);
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    break;
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  }
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  assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
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  assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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  return &ValMappings[Idx];
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}
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const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
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                                                                unsigned Size) {
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  if (Size != 64)
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    return getValueMapping(BankID, Size);
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  if (BankID == AMDGPU::VGPRRegBankID)
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    return &ValMappingsSGPR64OnlyVGPR32[4];
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  assert(BankID == AMDGPU::SGPRRegBankID);
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  return &ValMappingsSGPR64OnlyVGPR32[2];
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}
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const RegisterBankInfo::PartialMapping LoadSGPROnlyBreakDown[] {
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  /* 256-bit load */    {0, 256, SGPRRegBank},
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  /* 512-bit load */    {0, 512, SGPRRegBank},
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  /* 8 32-bit loads */  {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
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                        {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
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                        {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
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                        {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
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  /* 16 32-bit loads */ {0, 32, VGPRRegBank}, {32, 32, VGPRRegBank},
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                        {64, 32, VGPRRegBank}, {96, 32, VGPRRegBank},
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                        {128, 32, VGPRRegBank}, {160, 32, VGPRRegBank},
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                        {192, 32, VGPRRegBank}, {224, 32, VGPRRegBank},
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                        {256, 32, VGPRRegBank}, {288, 32, VGPRRegBank},
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                        {320, 32, VGPRRegBank}, {352, 32, VGPRRegBank},
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                        {384, 32, VGPRRegBank}, {416, 32, VGPRRegBank},
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                        {448, 32, VGPRRegBank}, {480, 32, VGPRRegBank},
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  /* 4 64-bit loads */  {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
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                        {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
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  /* 8 64-bit loads */  {0, 64, VGPRRegBank}, {64, 64, VGPRRegBank},
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                        {128, 64, VGPRRegBank}, {192, 64, VGPRRegBank},
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                        {256, 64, VGPRRegBank}, {320, 64, VGPRRegBank},
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                        {384, 64, VGPRRegBank}, {448, 64, VGPRRegBank},
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  /* FIXME: The generic register bank select does not support complex
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   * break downs where the number of vector elements does not equal the
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   * number of breakdowns.
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   * FIXME: register bank select now tries to handle complex break downs,
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   * but it emits an illegal instruction:
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   * %1:vgpr(<8 x s32>) = G_CONCAT_VECTORS %2:vgpr(s128), %3:vgpr(s128)
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   */
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  /* 2 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
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  /* 4 128-bit loads */ {0, 128, VGPRRegBank}, {128, 128, VGPRRegBank},
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                        {256, 128, VGPRRegBank}, {384, 128, VGPRRegBank}
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};
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const RegisterBankInfo::ValueMapping ValMappingsLoadSGPROnly[] {
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  /* 256-bit load */     {&LoadSGPROnlyBreakDown[0], 1},
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  /* 512-bit load */     {&LoadSGPROnlyBreakDown[1], 1},
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  /* <8 x i32> load  */  {&LoadSGPROnlyBreakDown[2], 8},
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  /* <16 x i32> load */  {&LoadSGPROnlyBreakDown[10], 16},
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  /* <4 x i64> load */   {&LoadSGPROnlyBreakDown[26], 4},
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  /* <8 x i64> load */   {&LoadSGPROnlyBreakDown[30], 8}
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};
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const RegisterBankInfo::ValueMapping *
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getValueMappingLoadSGPROnly(unsigned BankID, LLT SizeTy) {
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  unsigned Size = SizeTy.getSizeInBits();
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  if (Size < 256 || 
BankID == AMDGPU::SGPRRegBankID32
)
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    return getValueMapping(BankID, Size);
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  assert((Size == 256 || Size == 512) && BankID == AMDGPU::VGPRRegBankID);
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  // Default to using the non-split ValueMappings, we will use these if
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  // the register bank is SGPR or if we don't know how to handle the vector
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  // type.
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  unsigned Idx = Size == 256 ? 
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:
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;
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  // We need to split this load if it has a vgpr pointer.
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  if (BankID == AMDGPU::VGPRRegBankID) {
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    if (SizeTy == LLT::vector(8, 32))
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      Idx = 2;
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    else if (SizeTy == LLT::vector(16, 32))
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      Idx = 3;
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    else if (SizeTy == LLT::vector(4, 64))
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      Idx = 4;
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    else if (SizeTy == LLT::vector(8, 64))
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      Idx = 5;
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  }
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  return &ValMappingsLoadSGPROnly[Idx];
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}
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} // End AMDGPU namespace.
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} // End llvm namespace.