Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Source (jump to first uncovered line)
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//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This is the parent TargetLowering class for hardware code gen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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15
37
#define AMDGPU_LOG2E_F     1.44269504088896340735992468100189214f
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37
#define AMDGPU_LN2_F       0.693147180559945309417232121458176568f
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37
#define AMDGPU_LN10_F      2.30258509299404568401799145468436421f
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#include "AMDGPUISelLowering.h"
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#include "AMDGPU.h"
21
#include "AMDGPUCallLowering.h"
22
#include "AMDGPUFrameLowering.h"
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#include "AMDGPURegisterInfo.h"
24
#include "AMDGPUSubtarget.h"
25
#include "AMDGPUTargetMachine.h"
26
#include "Utils/AMDGPUBaseInfo.h"
27
#include "R600MachineFunctionInfo.h"
28
#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
30
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
36
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/DataLayout.h"
38
#include "llvm/IR/DiagnosticInfo.h"
39
#include "llvm/Support/KnownBits.h"
40
using namespace llvm;
41
42
#include "AMDGPUGenCallingConv.inc"
43
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// Find a larger type to do a load / store of a vector with.
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7.64k
EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
46
7.64k
  unsigned StoreSize = VT.getStoreSizeInBits();
47
7.64k
  if (StoreSize <= 32)
48
1.94k
    return EVT::getIntegerVT(Ctx, StoreSize);
49
5.69k
50
5.69k
  assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
51
5.69k
  return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
52
5.69k
}
53
54
14.7k
unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
55
14.7k
  EVT VT = Op.getValueType();
56
14.7k
  KnownBits Known = DAG.computeKnownBits(Op);
57
14.7k
  return VT.getSizeInBits() - Known.countMinLeadingZeros();
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14.7k
}
59
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7.50k
unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
61
7.50k
  EVT VT = Op.getValueType();
62
7.50k
63
7.50k
  // In order for this to be a signed 24-bit value, bit 23, must
64
7.50k
  // be a sign bit.
65
7.50k
  return VT.getSizeInBits() - DAG.ComputeNumSignBits(Op);
66
7.50k
}
67
68
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
69
                                           const AMDGPUSubtarget &STI)
70
3.93k
    : TargetLowering(TM), Subtarget(&STI) {
71
3.93k
  // Lower floating point store/load to integer store/load to reduce the number
72
3.93k
  // of patterns in tablegen.
73
3.93k
  setOperationAction(ISD::LOAD, MVT::f32, Promote);
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3.93k
  AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
75
3.93k
76
3.93k
  setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
77
3.93k
  AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
78
3.93k
79
3.93k
  setOperationAction(ISD::LOAD, MVT::v3f32, Promote);
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3.93k
  AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32);
81
3.93k
82
3.93k
  setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
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3.93k
  AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
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3.93k
85
3.93k
  setOperationAction(ISD::LOAD, MVT::v5f32, Promote);
86
3.93k
  AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32);
87
3.93k
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3.93k
  setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
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3.93k
  AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
90
3.93k
91
3.93k
  setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
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3.93k
  AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
93
3.93k
94
3.93k
  setOperationAction(ISD::LOAD, MVT::v32f32, Promote);
95
3.93k
  AddPromotedToType(ISD::LOAD, MVT::v32f32, MVT::v32i32);
96
3.93k
97
3.93k
  setOperationAction(ISD::LOAD, MVT::i64, Promote);
98
3.93k
  AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
99
3.93k
100
3.93k
  setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
101
3.93k
  AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
102
3.93k
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3.93k
  setOperationAction(ISD::LOAD, MVT::f64, Promote);
104
3.93k
  AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32);
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3.93k
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  setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
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  AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
108
3.93k
109
3.93k
  // There are no 64-bit extloads. These should be done as a 32-bit extload and
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  // an extension to 64-bit.
111
23.5k
  for (MVT VT : MVT::integer_valuetypes()) {
112
23.5k
    setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
113
23.5k
    setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
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23.5k
    setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
115
23.5k
  }
116
3.93k
117
23.5k
  for (MVT VT : MVT::integer_valuetypes()) {
118
23.5k
    if (VT == MVT::i64)
119
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      continue;
120
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121
19.6k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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19.6k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
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19.6k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
124
19.6k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
125
19.6k
126
19.6k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127
19.6k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
128
19.6k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
129
19.6k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
130
19.6k
131
19.6k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
133
19.6k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
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    setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
135
19.6k
  }
136
3.93k
137
306k
  for (MVT VT : MVT::integer_vector_valuetypes()) {
138
306k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
139
306k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
140
306k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
141
306k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
142
306k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
143
306k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
144
306k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
145
306k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
146
306k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
147
306k
    setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
148
306k
    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
149
306k
    setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
150
306k
  }
151
3.93k
152
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
153
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
154
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
155
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
156
3.93k
157
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
158
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
159
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
160
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand);
161
3.93k
162
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
163
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
164
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
165
3.93k
  setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
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3.93k
167
3.93k
  setOperationAction(ISD::STORE, MVT::f32, Promote);
168
3.93k
  AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
169
3.93k
170
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  setOperationAction(ISD::STORE, MVT::v2f32, Promote);
171
3.93k
  AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
172
3.93k
173
3.93k
  setOperationAction(ISD::STORE, MVT::v3f32, Promote);
174
3.93k
  AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
175
3.93k
176
3.93k
  setOperationAction(ISD::STORE, MVT::v4f32, Promote);
177
3.93k
  AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
178
3.93k
179
3.93k
  setOperationAction(ISD::STORE, MVT::v5f32, Promote);
180
3.93k
  AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
181
3.93k
182
3.93k
  setOperationAction(ISD::STORE, MVT::v8f32, Promote);
183
3.93k
  AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
184
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185
3.93k
  setOperationAction(ISD::STORE, MVT::v16f32, Promote);
186
3.93k
  AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
187
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188
3.93k
  setOperationAction(ISD::STORE, MVT::v32f32, Promote);
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3.93k
  AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
190
3.93k
191
3.93k
  setOperationAction(ISD::STORE, MVT::i64, Promote);
192
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  AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
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3.93k
194
3.93k
  setOperationAction(ISD::STORE, MVT::v2i64, Promote);
195
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  AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
196
3.93k
197
3.93k
  setOperationAction(ISD::STORE, MVT::f64, Promote);
198
3.93k
  AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
199
3.93k
200
3.93k
  setOperationAction(ISD::STORE, MVT::v2f64, Promote);
201
3.93k
  AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
202
3.93k
203
3.93k
  setTruncStoreAction(MVT::i64, MVT::i1, Expand);
204
3.93k
  setTruncStoreAction(MVT::i64, MVT::i8, Expand);
205
3.93k
  setTruncStoreAction(MVT::i64, MVT::i16, Expand);
206
3.93k
  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
207
3.93k
208
3.93k
  setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
209
3.93k
  setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
210
3.93k
  setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
211
3.93k
  setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
212
3.93k
213
3.93k
  setTruncStoreAction(MVT::f32, MVT::f16, Expand);
214
3.93k
  setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
215
3.93k
  setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
216
3.93k
  setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
217
3.93k
218
3.93k
  setTruncStoreAction(MVT::f64, MVT::f16, Expand);
219
3.93k
  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
220
3.93k
221
3.93k
  setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
222
3.93k
  setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
223
3.93k
224
3.93k
  setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
225
3.93k
  setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand);
226
3.93k
227
3.93k
  setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand);
228
3.93k
  setTruncStoreAction(MVT::v8f64, MVT::v8f16, Expand);
229
3.93k
230
3.93k
231
3.93k
  setOperationAction(ISD::Constant, MVT::i32, Legal);
232
3.93k
  setOperationAction(ISD::Constant, MVT::i64, Legal);
233
3.93k
  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
234
3.93k
  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
235
3.93k
236
3.93k
  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
237
3.93k
  setOperationAction(ISD::BRIND, MVT::Other, Expand);
238
3.93k
239
3.93k
  // This is totally unsupported, just custom lower to produce an error.
240
3.93k
  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
241
3.93k
242
3.93k
  // Library functions.  These default to Expand, but we have instructions
243
3.93k
  // for them.
244
3.93k
  setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
245
3.93k
  setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
246
3.93k
  setOperationAction(ISD::FPOW,   MVT::f32, Legal);
247
3.93k
  setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
248
3.93k
  setOperationAction(ISD::FABS,   MVT::f32, Legal);
249
3.93k
  setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
250
3.93k
  setOperationAction(ISD::FRINT,  MVT::f32, Legal);
251
3.93k
  setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
252
3.93k
  setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
253
3.93k
  setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
254
3.93k
255
3.93k
  setOperationAction(ISD::FROUND, MVT::f32, Custom);
256
3.93k
  setOperationAction(ISD::FROUND, MVT::f64, Custom);
257
3.93k
258
3.93k
  setOperationAction(ISD::FLOG, MVT::f32, Custom);
259
3.93k
  setOperationAction(ISD::FLOG10, MVT::f32, Custom);
260
3.93k
  setOperationAction(ISD::FEXP, MVT::f32, Custom);
261
3.93k
262
3.93k
263
3.93k
  setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
264
3.93k
  setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
265
3.93k
266
3.93k
  setOperationAction(ISD::FREM, MVT::f32, Custom);
267
3.93k
  setOperationAction(ISD::FREM, MVT::f64, Custom);
268
3.93k
269
3.93k
  // Expand to fneg + fadd.
270
3.93k
  setOperationAction(ISD::FSUB, MVT::f64, Expand);
271
3.93k
272
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
273
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
274
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
275
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
276
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
277
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
278
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
279
3.93k
  setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
280
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
281
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
282
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
283
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
284
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
285
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
286
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
287
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
288
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
289
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
290
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom);
291
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
292
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom);
293
3.93k
  setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
294
3.93k
295
3.93k
  setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
296
3.93k
  setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom);
297
3.93k
  setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom);
298
3.93k
299
3.93k
  const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
300
7.86k
  for (MVT VT : ScalarIntVTs) {
301
7.86k
    // These should use [SU]DIVREM, so set them to expand
302
7.86k
    setOperationAction(ISD::SDIV, VT, Expand);
303
7.86k
    setOperationAction(ISD::UDIV, VT, Expand);
304
7.86k
    setOperationAction(ISD::SREM, VT, Expand);
305
7.86k
    setOperationAction(ISD::UREM, VT, Expand);
306
7.86k
307
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    // GPU does not have divrem function for signed or unsigned.
308
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    setOperationAction(ISD::SDIVREM, VT, Custom);
309
7.86k
    setOperationAction(ISD::UDIVREM, VT, Custom);
310
7.86k
311
7.86k
    // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
312
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    setOperationAction(ISD::SMUL_LOHI, VT, Expand);
313
7.86k
    setOperationAction(ISD::UMUL_LOHI, VT, Expand);
314
7.86k
315
7.86k
    setOperationAction(ISD::BSWAP, VT, Expand);
316
7.86k
    setOperationAction(ISD::CTTZ, VT, Expand);
317
7.86k
    setOperationAction(ISD::CTLZ, VT, Expand);
318
7.86k
319
7.86k
    // AMDGPU uses ADDC/SUBC/ADDE/SUBE
320
7.86k
    setOperationAction(ISD::ADDC, VT, Legal);
321
7.86k
    setOperationAction(ISD::SUBC, VT, Legal);
322
7.86k
    setOperationAction(ISD::ADDE, VT, Legal);
323
7.86k
    setOperationAction(ISD::SUBE, VT, Legal);
324
7.86k
  }
325
3.93k
326
3.93k
  // The hardware supports 32-bit ROTR, but not ROTL.
327
3.93k
  setOperationAction(ISD::ROTL, MVT::i32, Expand);
328
3.93k
  setOperationAction(ISD::ROTL, MVT::i64, Expand);
329
3.93k
  setOperationAction(ISD::ROTR, MVT::i64, Expand);
330
3.93k
331
3.93k
  setOperationAction(ISD::MUL, MVT::i64, Expand);
332
3.93k
  setOperationAction(ISD::MULHU, MVT::i64, Expand);
333
3.93k
  setOperationAction(ISD::MULHS, MVT::i64, Expand);
334
3.93k
  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
335
3.93k
  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
336
3.93k
  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
337
3.93k
  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
338
3.93k
  setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
339
3.93k
340
3.93k
  setOperationAction(ISD::SMIN, MVT::i32, Legal);
341
3.93k
  setOperationAction(ISD::UMIN, MVT::i32, Legal);
342
3.93k
  setOperationAction(ISD::SMAX, MVT::i32, Legal);
343
3.93k
  setOperationAction(ISD::UMAX, MVT::i32, Legal);
344
3.93k
345
3.93k
  setOperationAction(ISD::CTTZ, MVT::i64, Custom);
346
3.93k
  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
347
3.93k
  setOperationAction(ISD::CTLZ, MVT::i64, Custom);
348
3.93k
  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
349
3.93k
350
3.93k
  static const MVT::SimpleValueType VectorIntTypes[] = {
351
3.93k
    MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32
352
3.93k
  };
353
3.93k
354
15.7k
  for (MVT VT : VectorIntTypes) {
355
15.7k
    // Expand the following operations for the current type by default.
356
15.7k
    setOperationAction(ISD::ADD,  VT, Expand);
357
15.7k
    setOperationAction(ISD::AND,  VT, Expand);
358
15.7k
    setOperationAction(ISD::FP_TO_SINT, VT, Expand);
359
15.7k
    setOperationAction(ISD::FP_TO_UINT, VT, Expand);
360
15.7k
    setOperationAction(ISD::MUL,  VT, Expand);
361
15.7k
    setOperationAction(ISD::MULHU, VT, Expand);
362
15.7k
    setOperationAction(ISD::MULHS, VT, Expand);
363
15.7k
    setOperationAction(ISD::OR,   VT, Expand);
364
15.7k
    setOperationAction(ISD::SHL,  VT, Expand);
365
15.7k
    setOperationAction(ISD::SRA,  VT, Expand);
366
15.7k
    setOperationAction(ISD::SRL,  VT, Expand);
367
15.7k
    setOperationAction(ISD::ROTL, VT, Expand);
368
15.7k
    setOperationAction(ISD::ROTR, VT, Expand);
369
15.7k
    setOperationAction(ISD::SUB,  VT, Expand);
370
15.7k
    setOperationAction(ISD::SINT_TO_FP, VT, Expand);
371
15.7k
    setOperationAction(ISD::UINT_TO_FP, VT, Expand);
372
15.7k
    setOperationAction(ISD::SDIV, VT, Expand);
373
15.7k
    setOperationAction(ISD::UDIV, VT, Expand);
374
15.7k
    setOperationAction(ISD::SREM, VT, Expand);
375
15.7k
    setOperationAction(ISD::UREM, VT, Expand);
376
15.7k
    setOperationAction(ISD::SMUL_LOHI, VT, Expand);
377
15.7k
    setOperationAction(ISD::UMUL_LOHI, VT, Expand);
378
15.7k
    setOperationAction(ISD::SDIVREM, VT, Custom);
379
15.7k
    setOperationAction(ISD::UDIVREM, VT, Expand);
380
15.7k
    setOperationAction(ISD::SELECT, VT, Expand);
381
15.7k
    setOperationAction(ISD::VSELECT, VT, Expand);
382
15.7k
    setOperationAction(ISD::SELECT_CC, VT, Expand);
383
15.7k
    setOperationAction(ISD::XOR,  VT, Expand);
384
15.7k
    setOperationAction(ISD::BSWAP, VT, Expand);
385
15.7k
    setOperationAction(ISD::CTPOP, VT, Expand);
386
15.7k
    setOperationAction(ISD::CTTZ, VT, Expand);
387
15.7k
    setOperationAction(ISD::CTLZ, VT, Expand);
388
15.7k
    setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
389
15.7k
    setOperationAction(ISD::SETCC, VT, Expand);
390
15.7k
  }
391
3.93k
392
3.93k
  static const MVT::SimpleValueType FloatVectorTypes[] = {
393
3.93k
     MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32
394
3.93k
  };
395
3.93k
396
15.7k
  for (MVT VT : FloatVectorTypes) {
397
15.7k
    setOperationAction(ISD::FABS, VT, Expand);
398
15.7k
    setOperationAction(ISD::FMINNUM, VT, Expand);
399
15.7k
    setOperationAction(ISD::FMAXNUM, VT, Expand);
400
15.7k
    setOperationAction(ISD::FADD, VT, Expand);
401
15.7k
    setOperationAction(ISD::FCEIL, VT, Expand);
402
15.7k
    setOperationAction(ISD::FCOS, VT, Expand);
403
15.7k
    setOperationAction(ISD::FDIV, VT, Expand);
404
15.7k
    setOperationAction(ISD::FEXP2, VT, Expand);
405
15.7k
    setOperationAction(ISD::FEXP, VT, Expand);
406
15.7k
    setOperationAction(ISD::FLOG2, VT, Expand);
407
15.7k
    setOperationAction(ISD::FREM, VT, Expand);
408
15.7k
    setOperationAction(ISD::FLOG, VT, Expand);
409
15.7k
    setOperationAction(ISD::FLOG10, VT, Expand);
410
15.7k
    setOperationAction(ISD::FPOW, VT, Expand);
411
15.7k
    setOperationAction(ISD::FFLOOR, VT, Expand);
412
15.7k
    setOperationAction(ISD::FTRUNC, VT, Expand);
413
15.7k
    setOperationAction(ISD::FMUL, VT, Expand);
414
15.7k
    setOperationAction(ISD::FMA, VT, Expand);
415
15.7k
    setOperationAction(ISD::FRINT, VT, Expand);
416
15.7k
    setOperationAction(ISD::FNEARBYINT, VT, Expand);
417
15.7k
    setOperationAction(ISD::FSQRT, VT, Expand);
418
15.7k
    setOperationAction(ISD::FSIN, VT, Expand);
419
15.7k
    setOperationAction(ISD::FSUB, VT, Expand);
420
15.7k
    setOperationAction(ISD::FNEG, VT, Expand);
421
15.7k
    setOperationAction(ISD::VSELECT, VT, Expand);
422
15.7k
    setOperationAction(ISD::SELECT_CC, VT, Expand);
423
15.7k
    setOperationAction(ISD::FCOPYSIGN, VT, Expand);
424
15.7k
    setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
425
15.7k
    setOperationAction(ISD::SETCC, VT, Expand);
426
15.7k
    setOperationAction(ISD::FCANONICALIZE, VT, Expand);
427
15.7k
  }
428
3.93k
429
3.93k
  // This causes using an unrolled select operation rather than expansion with
430
3.93k
  // bit operations. This is in general better, but the alternative using BFI
431
3.93k
  // instructions may be better if the select sources are SGPRs.
432
3.93k
  setOperationAction(ISD::SELECT, MVT::v2f32, Promote);
433
3.93k
  AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32);
434
3.93k
435
3.93k
  setOperationAction(ISD::SELECT, MVT::v3f32, Promote);
436
3.93k
  AddPromotedToType(ISD::SELECT, MVT::v3f32, MVT::v3i32);
437
3.93k
438
3.93k
  setOperationAction(ISD::SELECT, MVT::v4f32, Promote);
439
3.93k
  AddPromotedToType(ISD::SELECT, MVT::v4f32, MVT::v4i32);
440
3.93k
441
3.93k
  setOperationAction(ISD::SELECT, MVT::v5f32, Promote);
442
3.93k
  AddPromotedToType(ISD::SELECT, MVT::v5f32, MVT::v5i32);
443
3.93k
444
3.93k
  // There are no libcalls of any kind.
445
1.93M
  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; 
++I1.93M
)
446
1.93M
    setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
447
3.93k
448
3.93k
  setBooleanContents(ZeroOrNegativeOneBooleanContent);
449
3.93k
  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
450
3.93k
451
3.93k
  setSchedulingPreference(Sched::RegPressure);
452
3.93k
  setJumpIsExpensive(true);
453
3.93k
454
3.93k
  // FIXME: This is only partially true. If we have to do vector compares, any
455
3.93k
  // SGPR pair can be a condition register. If we have a uniform condition, we
456
3.93k
  // are better off doing SALU operations, where there is only one SCC. For now,
457
3.93k
  // we don't have a way of knowing during instruction selection if a condition
458
3.93k
  // will be uniform and we always use vector compares. Assume we are using
459
3.93k
  // vector compares until that is fixed.
460
3.93k
  setHasMultipleConditionRegisters(true);
461
3.93k
462
3.93k
  setMinCmpXchgSizeInBits(32);
463
3.93k
  setSupportsUnalignedAtomics(false);
464
3.93k
465
3.93k
  PredictableSelectIsExpensive = false;
466
3.93k
467
3.93k
  // We want to find all load dependencies for long chains of stores to enable
468
3.93k
  // merging into very wide vectors. The problem is with vectors with > 4
469
3.93k
  // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
470
3.93k
  // vectors are a legal type, even though we have to split the loads
471
3.93k
  // usually. When we can more precisely specify load legality per address
472
3.93k
  // space, we should be able to make FindBetterChain/MergeConsecutiveStores
473
3.93k
  // smarter so that they can figure out what to do in 2 iterations without all
474
3.93k
  // N > 4 stores on the same chain.
475
3.93k
  GatherAllAliasesMaxDepth = 16;
476
3.93k
477
3.93k
  // memcpy/memmove/memset are expanded in the IR, so we shouldn't need to worry
478
3.93k
  // about these during lowering.
479
3.93k
  MaxStoresPerMemcpy  = 0xffffffff;
480
3.93k
  MaxStoresPerMemmove = 0xffffffff;
481
3.93k
  MaxStoresPerMemset  = 0xffffffff;
482
3.93k
483
3.93k
  setTargetDAGCombine(ISD::BITCAST);
484
3.93k
  setTargetDAGCombine(ISD::SHL);
485
3.93k
  setTargetDAGCombine(ISD::SRA);
486
3.93k
  setTargetDAGCombine(ISD::SRL);
487
3.93k
  setTargetDAGCombine(ISD::TRUNCATE);
488
3.93k
  setTargetDAGCombine(ISD::MUL);
489
3.93k
  setTargetDAGCombine(ISD::MULHU);
490
3.93k
  setTargetDAGCombine(ISD::MULHS);
491
3.93k
  setTargetDAGCombine(ISD::SELECT);
492
3.93k
  setTargetDAGCombine(ISD::SELECT_CC);
493
3.93k
  setTargetDAGCombine(ISD::STORE);
494
3.93k
  setTargetDAGCombine(ISD::FADD);
495
3.93k
  setTargetDAGCombine(ISD::FSUB);
496
3.93k
  setTargetDAGCombine(ISD::FNEG);
497
3.93k
  setTargetDAGCombine(ISD::FABS);
498
3.93k
  setTargetDAGCombine(ISD::AssertZext);
499
3.93k
  setTargetDAGCombine(ISD::AssertSext);
500
3.93k
}
501
502
//===----------------------------------------------------------------------===//
503
// Target Information
504
//===----------------------------------------------------------------------===//
505
506
LLVM_READNONE
507
1.02k
static bool fnegFoldsIntoOp(unsigned Opc) {
508
1.02k
  switch (Opc) {
509
1.02k
  case ISD::FADD:
510
375
  case ISD::FSUB:
511
375
  case ISD::FMUL:
512
375
  case ISD::FMA:
513
375
  case ISD::FMAD:
514
375
  case ISD::FMINNUM:
515
375
  case ISD::FMAXNUM:
516
375
  case ISD::FMINNUM_IEEE:
517
375
  case ISD::FMAXNUM_IEEE:
518
375
  case ISD::FSIN:
519
375
  case ISD::FTRUNC:
520
375
  case ISD::FRINT:
521
375
  case ISD::FNEARBYINT:
522
375
  case ISD::FCANONICALIZE:
523
375
  case AMDGPUISD::RCP:
524
375
  case AMDGPUISD::RCP_LEGACY:
525
375
  case AMDGPUISD::RCP_IFLAG:
526
375
  case AMDGPUISD::SIN_HW:
527
375
  case AMDGPUISD::FMUL_LEGACY:
528
375
  case AMDGPUISD::FMIN_LEGACY:
529
375
  case AMDGPUISD::FMAX_LEGACY:
530
375
  case AMDGPUISD::FMED3:
531
375
    return true;
532
649
  default:
533
649
    return false;
534
1.02k
  }
535
1.02k
}
536
537
/// \p returns true if the operation will definitely need to use a 64-bit
538
/// encoding, and thus will use a VOP3 encoding regardless of the source
539
/// modifiers.
540
LLVM_READONLY
541
2.98k
static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) {
542
2.98k
  return N->getNumOperands() > 2 || 
VT == MVT::f641.84k
;
543
2.98k
}
544
545
// Most FP instructions support source modifiers, but this could be refined
546
// slightly.
547
LLVM_READONLY
548
3.96k
static bool hasSourceMods(const SDNode *N) {
549
3.96k
  if (isa<MemSDNode>(N))
550
424
    return false;
551
3.53k
552
3.53k
  switch (N->getOpcode()) {
553
3.53k
  case ISD::CopyToReg:
554
549
  case ISD::SELECT:
555
549
  case ISD::FDIV:
556
549
  case ISD::FREM:
557
549
  case ISD::INLINEASM:
558
549
  case ISD::INLINEASM_BR:
559
549
  case AMDGPUISD::INTERP_P1:
560
549
  case AMDGPUISD::INTERP_P2:
561
549
  case AMDGPUISD::DIV_SCALE:
562
549
563
549
  // TODO: Should really be looking at the users of the bitcast. These are
564
549
  // problematic because bitcasts are used to legalize all stores to integer
565
549
  // types.
566
549
  case ISD::BITCAST:
567
549
    return false;
568
2.98k
  default:
569
2.98k
    return true;
570
3.53k
  }
571
3.53k
}
572
573
bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
574
3.80k
                                                 unsigned CostThreshold) {
575
3.80k
  // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus
576
3.80k
  // it is truly free to use a source modifier in all cases. If there are
577
3.80k
  // multiple users but for each one will necessitate using VOP3, there will be
578
3.80k
  // a code size increase. Try to avoid increasing code size unless we know it
579
3.80k
  // will save on the instruction count.
580
3.80k
  unsigned NumMayIncreaseSize = 0;
581
3.80k
  MVT VT = N->getValueType(0).getScalarType().getSimpleVT();
582
3.80k
583
3.80k
  // XXX - Should this limit number of uses to check?
584
3.96k
  for (const SDNode *U : N->uses()) {
585
3.96k
    if (!hasSourceMods(U))
586
973
      return false;
587
2.98k
588
2.98k
    if (!opMustUseVOP3Encoding(U, VT)) {
589
1.59k
      if (++NumMayIncreaseSize > CostThreshold)
590
1.33k
        return false;
591
1.59k
    }
592
2.98k
  }
593
3.80k
594
3.80k
  
return true1.50k
;
595
3.80k
}
596
597
171k
MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
598
171k
  return MVT::i32;
599
171k
}
600
601
3.47k
bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
602
3.47k
  return true;
603
3.47k
}
604
605
// The backend supports 32 and 64 bit floating point immediates.
606
// FIXME: Why are we reporting vectors of FP immediates as legal?
607
bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
608
0
                                        bool ForCodeSize) const {
609
0
  EVT ScalarVT = VT.getScalarType();
610
0
  return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64 ||
611
0
         (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
612
0
}
613
614
// We don't want to shrink f64 / f32 constants.
615
0
bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
616
0
  EVT ScalarVT = VT.getScalarType();
617
0
  return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
618
0
}
619
620
bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
621
                                                 ISD::LoadExtType ExtTy,
622
4.08k
                                                 EVT NewVT) const {
623
4.08k
  // TODO: This may be worth removing. Check regression tests for diffs.
624
4.08k
  if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT))
625
1.53k
    return false;
626
2.55k
627
2.55k
  unsigned NewSize = NewVT.getStoreSizeInBits();
628
2.55k
629
2.55k
  // If we are reducing to a 32-bit load, this is always better.
630
2.55k
  if (NewSize == 32)
631
399
    return true;
632
2.15k
633
2.15k
  EVT OldVT = N->getValueType(0);
634
2.15k
  unsigned OldSize = OldVT.getStoreSizeInBits();
635
2.15k
636
2.15k
  MemSDNode *MN = cast<MemSDNode>(N);
637
2.15k
  unsigned AS = MN->getAddressSpace();
638
2.15k
  // Do not shrink an aligned scalar load to sub-dword.
639
2.15k
  // Scalar engine cannot do sub-dword loads.
640
2.15k
  if (OldSize >= 32 && 
NewSize < 322.10k
&&
MN->getAlignment() >= 42.04k
&&
641
2.15k
      
(1.72k
AS == AMDGPUAS::CONSTANT_ADDRESS1.72k
||
642
1.72k
       
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT397
||
643
1.72k
       
(397
isa<LoadSDNode>(N)397
&&
644
397
        AS == AMDGPUAS::GLOBAL_ADDRESS && 
MN->isInvariant()230
)) &&
645
2.15k
      
AMDGPUInstrInfo::isUniformMMO(MN->getMemOperand())1.32k
)
646
1.32k
    return false;
647
829
648
829
  // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
649
829
  // extloads, so doing one requires using a buffer_load. In cases where we
650
829
  // still couldn't use a scalar load, using the wider load shouldn't really
651
829
  // hurt anything.
652
829
653
829
  // If the old size already had to be an extload, there's no harm in continuing
654
829
  // to reduce the width.
655
829
  return (OldSize < 32);
656
829
}
657
658
bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
659
                                                   const SelectionDAG &DAG,
660
18.6k
                                                   const MachineMemOperand &MMO) const {
661
18.6k
662
18.6k
  assert(LoadTy.getSizeInBits() == CastTy.getSizeInBits());
663
18.6k
664
18.6k
  if (LoadTy.getScalarType() == MVT::i32)
665
16.5k
    return false;
666
2.14k
667
2.14k
  unsigned LScalarSize = LoadTy.getScalarSizeInBits();
668
2.14k
  unsigned CastScalarSize = CastTy.getScalarSizeInBits();
669
2.14k
670
2.14k
  if ((LScalarSize >= CastScalarSize) && 
(CastScalarSize < 32)1.63k
)
671
1.18k
    return false;
672
967
673
967
  bool Fast = false;
674
967
  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), CastTy,
675
967
                            MMO, &Fast) && 
Fast943
;
676
967
}
677
678
// SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
679
// profitable with the expansion for 64-bit since it's generally good to
680
// speculate things.
681
// FIXME: These should really have the size as a parameter.
682
27
bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
683
27
  return true;
684
27
}
685
686
60
bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
687
60
  return true;
688
60
}
689
690
2.97M
bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {
691
2.97M
  switch (N->getOpcode()) {
692
2.97M
    default:
693
2.61M
    return false;
694
2.97M
    case ISD::EntryToken:
695
145k
    case ISD::TokenFactor:
696
145k
      return true;
697
145k
    case ISD::INTRINSIC_WO_CHAIN:
698
27.4k
    {
699
27.4k
      unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
700
27.4k
      switch (IntrID) {
701
27.4k
        default:
702
27.2k
        return false;
703
27.4k
        case Intrinsic::amdgcn_readfirstlane:
704
221
        case Intrinsic::amdgcn_readlane:
705
221
          return true;
706
0
      }
707
0
    }
708
0
    break;
709
195k
    case ISD::LOAD:
710
195k
    {
711
195k
      const LoadSDNode * L = dyn_cast<LoadSDNode>(N);
712
195k
      if (L->getMemOperand()->getAddrSpace()
713
195k
      == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
714
166
        return true;
715
195k
      return false;
716
195k
    }
717
195k
    
break0
;
718
2.97M
  }
719
2.97M
}
720
721
//===---------------------------------------------------------------------===//
722
// Target Properties
723
//===---------------------------------------------------------------------===//
724
725
2.16k
bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
726
2.16k
  assert(VT.isFloatingPoint());
727
2.16k
728
2.16k
  // Packed operations do not have a fabs modifier.
729
2.16k
  return VT == MVT::f32 || 
VT == MVT::f64765
||
730
2.16k
         
(529
Subtarget->has16BitInsts()529
&&
VT == MVT::f16429
);
731
2.16k
}
732
733
4.73k
bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
734
4.73k
  assert(VT.isFloatingPoint());
735
4.73k
  return VT == MVT::f32 || 
VT == MVT::f641.25k
||
736
4.73k
         
(652
Subtarget->has16BitInsts()652
&&
VT == MVT::f16540
) ||
737
4.73k
         
(282
Subtarget->hasVOP3PInsts()282
&&
VT == MVT::v2f16103
);
738
4.73k
}
739
740
bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
741
                                                         unsigned NumElem,
742
27.3k
                                                         unsigned AS) const {
743
27.3k
  return true;
744
27.3k
}
745
746
37.8k
bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
747
37.8k
  // There are few operations which truly have vector input operands. Any vector
748
37.8k
  // operation is going to involve operations on each component, and a
749
37.8k
  // build_vector will be a copy per element, so it always makes sense to use a
750
37.8k
  // build_vector input in place of the extracted element to avoid a copy into a
751
37.8k
  // super register.
752
37.8k
  //
753
37.8k
  // We should probably only do this if all users are extracts only, but this
754
37.8k
  // should be the common case.
755
37.8k
  return true;
756
37.8k
}
757
758
44.4k
bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
759
44.4k
  // Truncate is just accessing a subregister.
760
44.4k
761
44.4k
  unsigned SrcSize = Source.getSizeInBits();
762
44.4k
  unsigned DestSize = Dest.getSizeInBits();
763
44.4k
764
44.4k
  return DestSize < SrcSize && DestSize % 32 == 0 ;
765
44.4k
}
766
767
2.17k
bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
768
2.17k
  // Truncate is just accessing a subregister.
769
2.17k
770
2.17k
  unsigned SrcSize = Source->getScalarSizeInBits();
771
2.17k
  unsigned DestSize = Dest->getScalarSizeInBits();
772
2.17k
773
2.17k
  if (DestSize== 16 && 
Subtarget->has16BitInsts()52
)
774
30
    return SrcSize >= 32;
775
2.14k
776
2.14k
  return DestSize < SrcSize && 
DestSize % 32 == 0947
;
777
2.14k
}
778
779
118
bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
780
118
  unsigned SrcSize = Src->getScalarSizeInBits();
781
118
  unsigned DestSize = Dest->getScalarSizeInBits();
782
118
783
118
  if (SrcSize == 16 && 
Subtarget->has16BitInsts()14
)
784
6
    return DestSize >= 32;
785
112
786
112
  return SrcSize == 32 && 
DestSize == 64103
;
787
112
}
788
789
33.8k
bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
790
33.8k
  // Any register load of a 64-bit value really requires 2 32-bit moves. For all
791
33.8k
  // practical purposes, the extra mov 0 to load a 64-bit is free.  As used,
792
33.8k
  // this will enable reducing 64-bit operations the 32-bit, which is always
793
33.8k
  // good.
794
33.8k
795
33.8k
  if (Src == MVT::i16)
796
9.75k
    return Dest == MVT::i32 ||
Dest == MVT::i641.11k
;
797
24.1k
798
24.1k
  return Src == MVT::i32 && 
Dest == MVT::i6413.5k
;
799
24.1k
}
800
801
8.37k
bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
802
8.37k
  return isZExtFree(Val.getValueType(), VT2);
803
8.37k
}
804
805
9.70k
bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
806
9.70k
  // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
807
9.70k
  // limited number of native 64-bit operations. Shrinking an operation to fit
808
9.70k
  // in a single 32-bit register should always be helpful. As currently used,
809
9.70k
  // this is much less general than the name suggests, and is only used in
810
9.70k
  // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
811
9.70k
  // not profitable, and may actually be harmful.
812
9.70k
  return SrcVT.getSizeInBits() > 32 && 
DestVT.getSizeInBits() == 3228
;
813
9.70k
}
814
815
//===---------------------------------------------------------------------===//
816
// TargetLowering Callbacks
817
//===---------------------------------------------------------------------===//
818
819
CCAssignFn *AMDGPUCallLowering::CCAssignFnForCall(CallingConv::ID CC,
820
6.15k
                                                  bool IsVarArg) {
821
6.15k
  switch (CC) {
822
6.15k
  case CallingConv::AMDGPU_VS:
823
2.98k
  case CallingConv::AMDGPU_GS:
824
2.98k
  case CallingConv::AMDGPU_PS:
825
2.98k
  case CallingConv::AMDGPU_CS:
826
2.98k
  case CallingConv::AMDGPU_HS:
827
2.98k
  case CallingConv::AMDGPU_ES:
828
2.98k
  case CallingConv::AMDGPU_LS:
829
2.98k
    return CC_AMDGPU;
830
3.16k
  case CallingConv::C:
831
3.16k
  case CallingConv::Fast:
832
3.16k
  case CallingConv::Cold:
833
3.16k
    return CC_AMDGPU_Func;
834
3.16k
  case CallingConv::AMDGPU_KERNEL:
835
1
  case CallingConv::SPIR_KERNEL:
836
1
  default:
837
1
    report_fatal_error("Unsupported calling convention for call");
838
6.15k
  }
839
6.15k
}
840
841
CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
842
8.77k
                                                    bool IsVarArg) {
843
8.77k
  switch (CC) {
844
8.77k
  case CallingConv::AMDGPU_KERNEL:
845
0
  case CallingConv::SPIR_KERNEL:
846
0
    llvm_unreachable("kernels should not be handled here");
847
2.98k
  case CallingConv::AMDGPU_VS:
848
2.98k
  case CallingConv::AMDGPU_GS:
849
2.98k
  case CallingConv::AMDGPU_PS:
850
2.98k
  case CallingConv::AMDGPU_CS:
851
2.98k
  case CallingConv::AMDGPU_HS:
852
2.98k
  case CallingConv::AMDGPU_ES:
853
2.98k
  case CallingConv::AMDGPU_LS:
854
2.98k
    return RetCC_SI_Shader;
855
5.79k
  case CallingConv::C:
856
5.79k
  case CallingConv::Fast:
857
5.79k
  case CallingConv::Cold:
858
5.79k
    return RetCC_AMDGPU_Func;
859
5.79k
  default:
860
0
    report_fatal_error("Unsupported calling convention.");
861
8.77k
  }
862
8.77k
}
863
864
/// The SelectionDAGBuilder will automatically promote function arguments
865
/// with illegal types.  However, this does not work for the AMDGPU targets
866
/// since the function arguments are stored in memory as these illegal types.
867
/// In order to handle this properly we need to get the original types sizes
868
/// from the LLVM IR Function and fixup the ISD:InputArg values before
869
/// passing them to AnalyzeFormalArguments()
870
871
/// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
872
/// input values across multiple registers.  Each item in the Ins array
873
/// represents a single value that will be stored in registers.  Ins[x].VT is
874
/// the value type of the value that will be stored in the register, so
875
/// whatever SDNode we lower the argument to needs to be this type.
876
///
877
/// In order to correctly lower the arguments we need to know the size of each
878
/// argument.  Since Ins[x].VT gives us the size of the register that will
879
/// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
880
/// for the orignal function argument so that we can deduce the correct memory
881
/// type to use for Ins[x].  In most cases the correct memory type will be
882
/// Ins[x].ArgVT.  However, this will not always be the case.  If, for example,
883
/// we have a kernel argument of type v8i8, this argument will be split into
884
/// 8 parts and each part will be represented by its own item in the Ins array.
885
/// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
886
/// the argument before it was split.  From this, we deduce that the memory type
887
/// for each individual part is i8.  We pass the memory type as LocVT to the
888
/// calling convention analysis function and the register type (Ins[x].VT) as
889
/// the ValVT.
890
void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
891
  CCState &State,
892
22.2k
  const SmallVectorImpl<ISD::InputArg> &Ins) const {
893
22.2k
  const MachineFunction &MF = State.getMachineFunction();
894
22.2k
  const Function &Fn = MF.getFunction();
895
22.2k
  LLVMContext &Ctx = Fn.getParent()->getContext();
896
22.2k
  const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
897
22.2k
  const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
898
22.2k
  CallingConv::ID CC = Fn.getCallingConv();
899
22.2k
900
22.2k
  unsigned MaxAlign = 1;
901
22.2k
  uint64_t ExplicitArgOffset = 0;
902
22.2k
  const DataLayout &DL = Fn.getParent()->getDataLayout();
903
22.2k
904
22.2k
  unsigned InIndex = 0;
905
22.2k
906
48.0k
  for (const Argument &Arg : Fn.args()) {
907
48.0k
    Type *BaseArgTy = Arg.getType();
908
48.0k
    unsigned Align = DL.getABITypeAlignment(BaseArgTy);
909
48.0k
    MaxAlign = std::max(Align, MaxAlign);
910
48.0k
    unsigned AllocSize = DL.getTypeAllocSize(BaseArgTy);
911
48.0k
912
48.0k
    uint64_t ArgOffset = alignTo(ExplicitArgOffset, Align) + ExplicitOffset;
913
48.0k
    ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize;
914
48.0k
915
48.0k
    // We're basically throwing away everything passed into us and starting over
916
48.0k
    // to get accurate in-memory offsets. The "PartOffset" is completely useless
917
48.0k
    // to us as computed in Ins.
918
48.0k
    //
919
48.0k
    // We also need to figure out what type legalization is trying to do to get
920
48.0k
    // the correct memory offsets.
921
48.0k
922
48.0k
    SmallVector<EVT, 16> ValueVTs;
923
48.0k
    SmallVector<uint64_t, 16> Offsets;
924
48.0k
    ComputeValueVTs(*this, DL, BaseArgTy, ValueVTs, &Offsets, ArgOffset);
925
48.0k
926
48.0k
    for (unsigned Value = 0, NumValues = ValueVTs.size();
927
101k
         Value != NumValues; 
++Value53.2k
) {
928
53.2k
      uint64_t BasePartOffset = Offsets[Value];
929
53.2k
930
53.2k
      EVT ArgVT = ValueVTs[Value];
931
53.2k
      EVT MemVT = ArgVT;
932
53.2k
      MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT);
933
53.2k
      unsigned NumRegs = getNumRegistersForCallingConv(Ctx, CC, ArgVT);
934
53.2k
935
53.2k
      if (NumRegs == 1) {
936
52.3k
        // This argument is not split, so the IR type is the memory type.
937
52.3k
        if (ArgVT.isExtended()) {
938
64
          // We have an extended type, like i24, so we should just use the
939
64
          // register type.
940
64
          MemVT = RegisterVT;
941
52.3k
        } else {
942
52.3k
          MemVT = ArgVT;
943
52.3k
        }
944
52.3k
      } else 
if (863
ArgVT.isVector()863
&&
RegisterVT.isVector()550
&&
945
863
                 
ArgVT.getScalarType() == RegisterVT.getScalarType()236
) {
946
236
        assert(ArgVT.getVectorNumElements() > RegisterVT.getVectorNumElements());
947
236
        // We have a vector value which has been split into a vector with
948
236
        // the same scalar type, but fewer elements.  This should handle
949
236
        // all the floating-point vector types.
950
236
        MemVT = RegisterVT;
951
627
      } else if (ArgVT.isVector() &&
952
627
                 
ArgVT.getVectorNumElements() == NumRegs314
) {
953
301
        // This arg has been split so that each element is stored in a separate
954
301
        // register.
955
301
        MemVT = ArgVT.getScalarType();
956
326
      } else if (ArgVT.isExtended()) {
957
29
        // We have an extended type, like i65.
958
29
        MemVT = RegisterVT;
959
297
      } else {
960
297
        unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs;
961
297
        assert(ArgVT.getStoreSizeInBits() % NumRegs == 0);
962
297
        if (RegisterVT.isInteger()) {
963
297
          MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits);
964
297
        } else 
if (0
RegisterVT.isVector()0
) {
965
0
          assert(!RegisterVT.getScalarType().isFloatingPoint());
966
0
          unsigned NumElements = RegisterVT.getVectorNumElements();
967
0
          assert(MemoryBits % NumElements == 0);
968
0
          // This vector type has been split into another vector type with
969
0
          // a different elements size.
970
0
          EVT ScalarVT = EVT::getIntegerVT(State.getContext(),
971
0
                                           MemoryBits / NumElements);
972
0
          MemVT = EVT::getVectorVT(State.getContext(), ScalarVT, NumElements);
973
0
        } else {
974
0
          llvm_unreachable("cannot deduce memory type.");
975
0
        }
976
53.2k
      }
977
53.2k
978
53.2k
      // Convert one element vectors to scalar.
979
53.2k
      if (MemVT.isVector() && 
MemVT.getVectorNumElements() == 11.71k
)
980
54
        MemVT = MemVT.getScalarType();
981
53.2k
982
53.2k
      // Round up vec3/vec5 argument.
983
53.2k
      if (MemVT.isVector() && 
!MemVT.isPow2VectorType()1.65k
) {
984
74
        assert(MemVT.getVectorNumElements() == 3 ||
985
74
               MemVT.getVectorNumElements() == 5);
986
74
        MemVT = MemVT.getPow2VectorType(State.getContext());
987
74
      }
988
53.2k
989
53.2k
      unsigned PartOffset = 0;
990
108k
      for (unsigned i = 0; i != NumRegs; 
++i55.6k
) {
991
55.6k
        State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
992
55.6k
                                               BasePartOffset + PartOffset,
993
55.6k
                                               MemVT.getSimpleVT(),
994
55.6k
                                               CCValAssign::Full));
995
55.6k
        PartOffset += MemVT.getStoreSize();
996
55.6k
      }
997
53.2k
    }
998
48.0k
  }
999
22.2k
}
1000
1001
SDValue AMDGPUTargetLowering::LowerReturn(
1002
  SDValue Chain, CallingConv::ID CallConv,
1003
  bool isVarArg,
1004
  const SmallVectorImpl<ISD::OutputArg> &Outs,
1005
  const SmallVectorImpl<SDValue> &OutVals,
1006
22.2k
  const SDLoc &DL, SelectionDAG &DAG) const {
1007
22.2k
  // FIXME: Fails for r600 tests
1008
22.2k
  //assert(!isVarArg && Outs.empty() && OutVals.empty() &&
1009
22.2k
  // "wave terminate should not have return values");
1010
22.2k
  return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1011
22.2k
}
1012
1013
//===---------------------------------------------------------------------===//
1014
// Target specific lowering
1015
//===---------------------------------------------------------------------===//
1016
1017
/// Selects the correct CCAssignFn for a given CallingConvention value.
1018
CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1019
6.15k
                                                    bool IsVarArg) {
1020
6.15k
  return AMDGPUCallLowering::CCAssignFnForCall(CC, IsVarArg);
1021
6.15k
}
1022
1023
CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1024
8.77k
                                                      bool IsVarArg) {
1025
8.77k
  return AMDGPUCallLowering::CCAssignFnForReturn(CC, IsVarArg);
1026
8.77k
}
1027
1028
SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1029
                                                  SelectionDAG &DAG,
1030
                                                  MachineFrameInfo &MFI,
1031
39
                                                  int ClobberedFI) const {
1032
39
  SmallVector<SDValue, 8> ArgChains;
1033
39
  int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
1034
39
  int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
1035
39
1036
39
  // Include the original chain at the beginning of the list. When this is
1037
39
  // used by target LowerCall hooks, this helps legalize find the
1038
39
  // CALLSEQ_BEGIN node.
1039
39
  ArgChains.push_back(Chain);
1040
39
1041
39
  // Add a chain value for each stack argument corresponding
1042
39
  for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1043
39
                            UE = DAG.getEntryNode().getNode()->use_end();
1044
1.38k
       U != UE; 
++U1.34k
) {
1045
1.34k
    if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) {
1046
99
      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) {
1047
99
        if (FI->getIndex() < 0) {
1048
99
          int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
1049
99
          int64_t InLastByte = InFirstByte;
1050
99
          InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
1051
99
1052
99
          if ((InFirstByte <= FirstByte && 
FirstByte <= InLastByte55
) ||
1053
99
              
(60
FirstByte <= InFirstByte60
&&
InFirstByte <= LastByte44
))
1054
43
            ArgChains.push_back(SDValue(L, 1));
1055
99
        }
1056
99
      }
1057
99
    }
1058
1.34k
  }
1059
39
1060
39
  // Build a tokenfactor for all the chains.
1061
39
  return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1062
39
}
1063
1064
SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1065
                                                 SmallVectorImpl<SDValue> &InVals,
1066
83
                                                 StringRef Reason) const {
1067
83
  SDValue Callee = CLI.Callee;
1068
83
  SelectionDAG &DAG = CLI.DAG;
1069
83
1070
83
  const Function &Fn = DAG.getMachineFunction().getFunction();
1071
83
1072
83
  StringRef FuncName("<unknown>");
1073
83
1074
83
  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
1075
64
    FuncName = G->getSymbol();
1076
19
  else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1077
17
    FuncName = G->getGlobal()->getName();
1078
83
1079
83
  DiagnosticInfoUnsupported NoCalls(
1080
83
    Fn, Reason + FuncName, CLI.DL.getDebugLoc());
1081
83
  DAG.getContext()->diagnose(NoCalls);
1082
83
1083
83
  if (!CLI.IsTailCall) {
1084
153
    for (unsigned I = 0, E = CLI.Ins.size(); I != E; 
++I75
)
1085
75
      InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
1086
78
  }
1087
83
1088
83
  return DAG.getEntryNode();
1089
83
}
1090
1091
SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1092
78
                                        SmallVectorImpl<SDValue> &InVals) const {
1093
78
  return lowerUnhandledCall(CLI, InVals, "unsupported call to function ");
1094
78
}
1095
1096
SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1097
3
                                                      SelectionDAG &DAG) const {
1098
3
  const Function &Fn = DAG.getMachineFunction().getFunction();
1099
3
1100
3
  DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "unsupported dynamic alloca",
1101
3
                                            SDLoc(Op).getDebugLoc());
1102
3
  DAG.getContext()->diagnose(NoDynamicAlloca);
1103
3
  auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
1104
3
  return DAG.getMergeValues(Ops, SDLoc());
1105
3
}
1106
1107
SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1108
28.5k
                                             SelectionDAG &DAG) const {
1109
28.5k
  switch (Op.getOpcode()) {
1110
28.5k
  default:
1111
0
    Op->print(errs(), &DAG);
1112
0
    llvm_unreachable("Custom lowering code for this"
1113
28.5k
                     "instruction is not implemented yet!");
1114
28.5k
    
break0
;
1115
28.5k
  
case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG)16
;
1116
28.5k
  
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG)5.12k
;
1117
28.5k
  
case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG)21.0k
;
1118
28.5k
  
case ISD::UDIVREM: return LowerUDIVREM(Op, DAG)179
;
1119
28.5k
  
case ISD::SDIVREM: return LowerSDIVREM(Op, DAG)72
;
1120
28.5k
  
case ISD::FREM: return LowerFREM(Op, DAG)46
;
1121
28.5k
  
case ISD::FCEIL: return LowerFCEIL(Op, DAG)31
;
1122
28.5k
  
case ISD::FTRUNC: return LowerFTRUNC(Op, DAG)75
;
1123
28.5k
  
case ISD::FRINT: return LowerFRINT(Op, DAG)14
;
1124
28.5k
  
case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG)48
;
1125
28.5k
  
case ISD::FROUND: return LowerFROUND(Op, DAG)93
;
1126
28.5k
  
case ISD::FFLOOR: return LowerFFLOOR(Op, DAG)0
;
1127
28.5k
  case ISD::FLOG:
1128
37
    return LowerFLOG(Op, DAG, 1 / AMDGPU_LOG2E_F);
1129
28.5k
  case ISD::FLOG10:
1130
37
    return LowerFLOG(Op, DAG, AMDGPU_LN2_F / AMDGPU_LN10_F);
1131
28.5k
  case ISD::FEXP:
1132
50
    return lowerFEXP(Op, DAG);
1133
28.5k
  
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG)42
;
1134
28.5k
  
case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG)51
;
1135
28.5k
  
case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG)1.01k
;
1136
28.5k
  
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG)65
;
1137
28.5k
  
case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG)37
;
1138
28.5k
  case ISD::CTTZ:
1139
455
  case ISD::CTTZ_ZERO_UNDEF:
1140
455
  case ISD::CTLZ:
1141
455
  case ISD::CTLZ_ZERO_UNDEF:
1142
455
    return LowerCTLZ_CTTZ(Op, DAG);
1143
455
  
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG)3
;
1144
0
  }
1145
0
  return Op;
1146
0
}
1147
1148
void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1149
                                              SmallVectorImpl<SDValue> &Results,
1150
46
                                              SelectionDAG &DAG) const {
1151
46
  switch (N->getOpcode()) {
1152
46
  case ISD::SIGN_EXTEND_INREG:
1153
0
    // Different parts of legalization seem to interpret which type of
1154
0
    // sign_extend_inreg is the one to check for custom lowering. The extended
1155
0
    // from type is what really matters, but some places check for custom
1156
0
    // lowering of the result type. This results in trying to use
1157
0
    // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
1158
0
    // nothing here and let the illegal result integer be handled normally.
1159
0
    return;
1160
46
  default:
1161
46
    return;
1162
46
  }
1163
46
}
1164
1165
236
static bool hasDefinedInitializer(const GlobalValue *GV) {
1166
236
  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1167
236
  if (!GVar || !GVar->hasInitializer())
1168
1
    return false;
1169
235
1170
235
  return !isa<UndefValue>(GVar->getInitializer());
1171
235
}
1172
1173
SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1174
                                                 SDValue Op,
1175
236
                                                 SelectionDAG &DAG) const {
1176
236
1177
236
  const DataLayout &DL = DAG.getDataLayout();
1178
236
  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
1179
236
  const GlobalValue *GV = G->getGlobal();
1180
236
1181
236
  if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1182
236
      
G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS0
) {
1183
236
    if (!MFI->isEntryFunction()) {
1184
1
      const Function &Fn = DAG.getMachineFunction().getFunction();
1185
1
      DiagnosticInfoUnsupported BadLDSDecl(
1186
1
        Fn, "local memory global used by non-kernel function", SDLoc(Op).getDebugLoc());
1187
1
      DAG.getContext()->diagnose(BadLDSDecl);
1188
1
    }
1189
236
1190
236
    // XXX: What does the value of G->getOffset() mean?
1191
236
    assert(G->getOffset() == 0 &&
1192
236
         "Do not know what to do with an non-zero offset");
1193
236
1194
236
    // TODO: We could emit code to handle the initialization somewhere.
1195
236
    if (!hasDefinedInitializer(GV)) {
1196
236
      unsigned Offset = MFI->allocateLDSGlobal(DL, *GV);
1197
236
      return DAG.getConstant(Offset, SDLoc(Op), Op.getValueType());
1198
236
    }
1199
0
  }
1200
0
1201
0
  const Function &Fn = DAG.getMachineFunction().getFunction();
1202
0
  DiagnosticInfoUnsupported BadInit(
1203
0
      Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
1204
0
  DAG.getContext()->diagnose(BadInit);
1205
0
  return SDValue();
1206
0
}
1207
1208
SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1209
5.12k
                                                  SelectionDAG &DAG) const {
1210
5.12k
  SmallVector<SDValue, 8> Args;
1211
5.12k
1212
5.12k
  EVT VT = Op.getValueType();
1213
5.12k
  if (VT == MVT::v4i16 || 
VT == MVT::v4f165.02k
) {
1214
202
    SDLoc SL(Op);
1215
202
    SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1216
202
    SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1217
202
1218
202
    SDValue BV = DAG.getBuildVector(MVT::v2i32, SL, { Lo, Hi });
1219
202
    return DAG.getNode(ISD::BITCAST, SL, VT, BV);
1220
202
  }
1221
4.92k
1222
4.92k
  for (const SDUse &U : Op->ops())
1223
9.88k
    DAG.ExtractVectorElements(U.get(), Args);
1224
4.92k
1225
4.92k
  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1226
4.92k
}
1227
1228
SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1229
21.0k
                                                     SelectionDAG &DAG) const {
1230
21.0k
1231
21.0k
  SmallVector<SDValue, 8> Args;
1232
21.0k
  unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1233
21.0k
  EVT VT = Op.getValueType();
1234
21.0k
  DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
1235
21.0k
                            VT.getVectorNumElements());
1236
21.0k
1237
21.0k
  return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
1238
21.0k
}
1239
1240
/// Generate Min/Max node
1241
SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1242
                                                   SDValue LHS, SDValue RHS,
1243
                                                   SDValue True, SDValue False,
1244
                                                   SDValue CC,
1245
826
                                                   DAGCombinerInfo &DCI) const {
1246
826
  if (!(LHS == True && 
RHS == False126
) &&
!(703
LHS == False703
&&
RHS == True13
))
1247
692
    return SDValue();
1248
134
1249
134
  SelectionDAG &DAG = DCI.DAG;
1250
134
  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1251
134
  switch (CCOpcode) {
1252
134
  case ISD::SETOEQ:
1253
26
  case ISD::SETONE:
1254
26
  case ISD::SETUNE:
1255
26
  case ISD::SETNE:
1256
26
  case ISD::SETUEQ:
1257
26
  case ISD::SETEQ:
1258
26
  case ISD::SETFALSE:
1259
26
  case ISD::SETFALSE2:
1260
26
  case ISD::SETTRUE:
1261
26
  case ISD::SETTRUE2:
1262
26
  case ISD::SETUO:
1263
26
  case ISD::SETO:
1264
26
    break;
1265
32
  case ISD::SETULE:
1266
32
  case ISD::SETULT: {
1267
32
    if (LHS == True)
1268
32
      return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1269
0
    return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1270
0
  }
1271
4
  case ISD::SETOLE:
1272
4
  case ISD::SETOLT:
1273
4
  case ISD::SETLE:
1274
4
  case ISD::SETLT: {
1275
4
    // Ordered. Assume ordered for undefined.
1276
4
1277
4
    // Only do this after legalization to avoid interfering with other combines
1278
4
    // which might occur.
1279
4
    if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1280
4
        
!DCI.isCalledByLegalizer()2
)
1281
2
      return SDValue();
1282
2
1283
2
    // We need to permute the operands to get the correct NaN behavior. The
1284
2
    // selected operand is the second one based on the failing compare with NaN,
1285
2
    // so permute it based on the compare type the hardware uses.
1286
2
    if (LHS == True)
1287
2
      return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1288
0
    return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1289
0
  }
1290
31
  case ISD::SETUGE:
1291
31
  case ISD::SETUGT: {
1292
31
    if (LHS == True)
1293
30
      return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1294
1
    return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1295
1
  }
1296
41
  case ISD::SETGT:
1297
41
  case ISD::SETGE:
1298
41
  case ISD::SETOGE:
1299
41
  case ISD::SETOGT: {
1300
41
    if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1301
41
        
!DCI.isCalledByLegalizer()35
)
1302
14
      return SDValue();
1303
27
1304
27
    if (LHS == True)
1305
17
      return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1306
10
    return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1307
10
  }
1308
10
  case ISD::SETCC_INVALID:
1309
0
    llvm_unreachable("Invalid setcc condcode!");
1310
26
  }
1311
26
  return SDValue();
1312
26
}
1313
1314
std::pair<SDValue, SDValue>
1315
3.16k
AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1316
3.16k
  SDLoc SL(Op);
1317
3.16k
1318
3.16k
  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1319
3.16k
1320
3.16k
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1321
3.16k
  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1322
3.16k
1323
3.16k
  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1324
3.16k
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1325
3.16k
1326
3.16k
  return std::make_pair(Lo, Hi);
1327
3.16k
}
1328
1329
0
SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1330
0
  SDLoc SL(Op);
1331
0
1332
0
  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1333
0
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1334
0
  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1335
0
}
1336
1337
138
SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1338
138
  SDLoc SL(Op);
1339
138
1340
138
  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1341
138
  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1342
138
  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1343
138
}
1344
1345
// Split a vector type into two parts. The first part is a power of two vector.
1346
// The second part is whatever is left over, and is a scalar if it would
1347
// otherwise be a 1-vector.
1348
std::pair<EVT, EVT>
1349
25.3k
AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1350
25.3k
  EVT LoVT, HiVT;
1351
25.3k
  EVT EltVT = VT.getVectorElementType();
1352
25.3k
  unsigned NumElts = VT.getVectorNumElements();
1353
25.3k
  unsigned LoNumElts = PowerOf2Ceil((NumElts + 1) / 2);
1354
25.3k
  LoVT = EVT::getVectorVT(*DAG.getContext(), EltVT, LoNumElts);
1355
25.3k
  HiVT = NumElts - LoNumElts == 1
1356
25.3k
             ? 
EltVT1.08k
1357
25.3k
             : 
EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts - LoNumElts)24.2k
;
1358
25.3k
  return std::make_pair(LoVT, HiVT);
1359
25.3k
}
1360
1361
// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
1362
// scalar.
1363
std::pair<SDValue, SDValue>
1364
AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1365
                                  const EVT &LoVT, const EVT &HiVT,
1366
12.6k
                                  SelectionDAG &DAG) const {
1367
12.6k
  assert(LoVT.getVectorNumElements() +
1368
12.6k
                 (HiVT.isVector() ? HiVT.getVectorNumElements() : 1) <=
1369
12.6k
             N.getValueType().getVectorNumElements() &&
1370
12.6k
         "More vector elements requested than available!");
1371
12.6k
  auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1372
12.6k
  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
1373
12.6k
                           DAG.getConstant(0, DL, IdxTy));
1374
12.6k
  SDValue Hi = DAG.getNode(
1375
12.6k
      HiVT.isVector() ? 
ISD::EXTRACT_SUBVECTOR12.1k
:
ISD::EXTRACT_VECTOR_ELT544
, DL,
1376
12.6k
      HiVT, N, DAG.getConstant(LoVT.getVectorNumElements(), DL, IdxTy));
1377
12.6k
  return std::make_pair(Lo, Hi);
1378
12.6k
}
1379
1380
SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1381
3.35k
                                              SelectionDAG &DAG) const {
1382
3.35k
  LoadSDNode *Load = cast<LoadSDNode>(Op);
1383
3.35k
  EVT VT = Op.getValueType();
1384
3.35k
1385
3.35k
1386
3.35k
  // If this is a 2 element vector, we really want to scalarize and not create
1387
3.35k
  // weird 1 element vectors.
1388
3.35k
  if (VT.getVectorNumElements() == 2)
1389
23
    return scalarizeVectorLoad(Load, DAG);
1390
3.33k
1391
3.33k
  SDValue BasePtr = Load->getBasePtr();
1392
3.33k
  EVT MemVT = Load->getMemoryVT();
1393
3.33k
  SDLoc SL(Op);
1394
3.33k
1395
3.33k
  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1396
3.33k
1397
3.33k
  EVT LoVT, HiVT;
1398
3.33k
  EVT LoMemVT, HiMemVT;
1399
3.33k
  SDValue Lo, Hi;
1400
3.33k
1401
3.33k
  std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1402
3.33k
  std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1403
3.33k
  std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG);
1404
3.33k
1405
3.33k
  unsigned Size = LoMemVT.getStoreSize();
1406
3.33k
  unsigned BaseAlign = Load->getAlignment();
1407
3.33k
  unsigned HiAlign = MinAlign(BaseAlign, Size);
1408
3.33k
1409
3.33k
  SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1410
3.33k
                                  Load->getChain(), BasePtr, SrcValue, LoMemVT,
1411
3.33k
                                  BaseAlign, Load->getMemOperand()->getFlags());
1412
3.33k
  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, Size);
1413
3.33k
  SDValue HiLoad =
1414
3.33k
      DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(),
1415
3.33k
                     HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1416
3.33k
                     HiMemVT, HiAlign, Load->getMemOperand()->getFlags());
1417
3.33k
1418
3.33k
  auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
1419
3.33k
  SDValue Join;
1420
3.33k
  if (LoVT == HiVT) {
1421
2.91k
    // This is the case that the vector is power of two so was evenly split.
1422
2.91k
    Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
1423
2.91k
  } else {
1424
422
    Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad,
1425
422
                       DAG.getConstant(0, SL, IdxTy));
1426
422
    Join = DAG.getNode(HiVT.isVector() ? 
ISD::INSERT_SUBVECTOR0
1427
422
                                       : ISD::INSERT_VECTOR_ELT,
1428
422
                       SL, VT, Join, HiLoad,
1429
422
                       DAG.getConstant(LoVT.getVectorNumElements(), SL, IdxTy));
1430
422
  }
1431
3.33k
1432
3.33k
  SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1433
3.33k
                                     LoLoad.getValue(1), HiLoad.getValue(1))};
1434
3.33k
1435
3.33k
  return DAG.getMergeValues(Ops, SL);
1436
3.33k
}
1437
1438
// Widen a vector load from vec3 to vec4.
1439
SDValue AMDGPUTargetLowering::WidenVectorLoad(SDValue Op,
1440
366
                                              SelectionDAG &DAG) const {
1441
366
  LoadSDNode *Load = cast<LoadSDNode>(Op);
1442
366
  EVT VT = Op.getValueType();
1443
366
  assert(VT.getVectorNumElements() == 3);
1444
366
  SDValue BasePtr = Load->getBasePtr();
1445
366
  EVT MemVT = Load->getMemoryVT();
1446
366
  SDLoc SL(Op);
1447
366
  const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1448
366
  unsigned BaseAlign = Load->getAlignment();
1449
366
1450
366
  EVT WideVT =
1451
366
      EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
1452
366
  EVT WideMemVT =
1453
366
      EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), 4);
1454
366
  SDValue WideLoad = DAG.getExtLoad(
1455
366
      Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue,
1456
366
      WideMemVT, BaseAlign, Load->getMemOperand()->getFlags());
1457
366
  return DAG.getMergeValues(
1458
366
      {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad,
1459
366
                   DAG.getConstant(0, SL, getVectorIdxTy(DAG.getDataLayout()))),
1460
366
       WideLoad.getValue(1)},
1461
366
      SL);
1462
366
}
1463
1464
SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1465
9.36k
                                               SelectionDAG &DAG) const {
1466
9.36k
  StoreSDNode *Store = cast<StoreSDNode>(Op);
1467
9.36k
  SDValue Val = Store->getValue();
1468
9.36k
  EVT VT = Val.getValueType();
1469
9.36k
1470
9.36k
  // If this is a 2 element vector, we really want to scalarize and not create
1471
9.36k
  // weird 1 element vectors.
1472
9.36k
  if (VT.getVectorNumElements() == 2)
1473
33
    return scalarizeVectorStore(Store, DAG);
1474
9.33k
1475
9.33k
  EVT MemVT = Store->getMemoryVT();
1476
9.33k
  SDValue Chain = Store->getChain();
1477
9.33k
  SDValue BasePtr = Store->getBasePtr();
1478
9.33k
  SDLoc SL(Op);
1479
9.33k
1480
9.33k
  EVT LoVT, HiVT;
1481
9.33k
  EVT LoMemVT, HiMemVT;
1482
9.33k
  SDValue Lo, Hi;
1483
9.33k
1484
9.33k
  std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG);
1485
9.33k
  std::tie(LoMemVT, HiMemVT) = getSplitDestVTs(MemVT, DAG);
1486
9.33k
  std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG);
1487
9.33k
1488
9.33k
  SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize());
1489
9.33k
1490
9.33k
  const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1491
9.33k
  unsigned BaseAlign = Store->getAlignment();
1492
9.33k
  unsigned Size = LoMemVT.getStoreSize();
1493
9.33k
  unsigned HiAlign = MinAlign(BaseAlign, Size);
1494
9.33k
1495
9.33k
  SDValue LoStore =
1496
9.33k
      DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1497
9.33k
                        Store->getMemOperand()->getFlags());
1498
9.33k
  SDValue HiStore =
1499
9.33k
      DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size),
1500
9.33k
                        HiMemVT, HiAlign, Store->getMemOperand()->getFlags());
1501
9.33k
1502
9.33k
  return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1503
9.33k
}
1504
1505
// This is a shortcut for integer division because we have fast i32<->f32
1506
// conversions, and fast f32 reciprocal instructions. The fractional part of a
1507
// float is enough to accurately represent up to a 24-bit signed integer.
1508
SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1509
169
                                            bool Sign) const {
1510
169
  SDLoc DL(Op);
1511
169
  EVT VT = Op.getValueType();
1512
169
  SDValue LHS = Op.getOperand(0);
1513
169
  SDValue RHS = Op.getOperand(1);
1514
169
  MVT IntVT = MVT::i32;
1515
169
  MVT FltVT = MVT::f32;
1516
169
1517
169
  unsigned LHSSignBits = DAG.ComputeNumSignBits(LHS);
1518
169
  if (LHSSignBits < 9)
1519
129
    return SDValue();
1520
40
1521
40
  unsigned RHSSignBits = DAG.ComputeNumSignBits(RHS);
1522
40
  if (RHSSignBits < 9)
1523
4
    return SDValue();
1524
36
1525
36
  unsigned BitSize = VT.getSizeInBits();
1526
36
  unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1527
36
  unsigned DivBits = BitSize - SignBits;
1528
36
  if (Sign)
1529
18
    ++DivBits;
1530
36
1531
36
  ISD::NodeType ToFp = Sign ? 
ISD::SINT_TO_FP18
:
ISD::UINT_TO_FP18
;
1532
36
  ISD::NodeType ToInt = Sign ? 
ISD::FP_TO_SINT18
:
ISD::FP_TO_UINT18
;
1533
36
1534
36
  SDValue jq = DAG.getConstant(1, DL, IntVT);
1535
36
1536
36
  if (Sign) {
1537
18
    // char|short jq = ia ^ ib;
1538
18
    jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1539
18
1540
18
    // jq = jq >> (bitsize - 2)
1541
18
    jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1542
18
                     DAG.getConstant(BitSize - 2, DL, VT));
1543
18
1544
18
    // jq = jq | 0x1
1545
18
    jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1546
18
  }
1547
36
1548
36
  // int ia = (int)LHS;
1549
36
  SDValue ia = LHS;
1550
36
1551
36
  // int ib, (int)RHS;
1552
36
  SDValue ib = RHS;
1553
36
1554
36
  // float fa = (float)ia;
1555
36
  SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1556
36
1557
36
  // float fb = (float)ib;
1558
36
  SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1559
36
1560
36
  SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1561
36
                           fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1562
36
1563
36
  // fq = trunc(fq);
1564
36
  fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1565
36
1566
36
  // float fqneg = -fq;
1567
36
  SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1568
36
1569
36
  // float fr = mad(fqneg, fb, fa);
1570
36
  unsigned OpCode = Subtarget->hasFP32Denormals() ?
1571
0
                    (unsigned)AMDGPUISD::FMAD_FTZ :
1572
36
                    (unsigned)ISD::FMAD;
1573
36
  SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
1574
36
1575
36
  // int iq = (int)fq;
1576
36
  SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1577
36
1578
36
  // fr = fabs(fr);
1579
36
  fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1580
36
1581
36
  // fb = fabs(fb);
1582
36
  fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1583
36
1584
36
  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1585
36
1586
36
  // int cv = fr >= fb;
1587
36
  SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1588
36
1589
36
  // jq = (cv ? jq : 0);
1590
36
  jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1591
36
1592
36
  // dst = iq + jq;
1593
36
  SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1594
36
1595
36
  // Rem needs compensation, it's easier to recompute it
1596
36
  SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1597
36
  Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1598
36
1599
36
  // Truncate to number of bits this divide really is.
1600
36
  if (Sign) {
1601
18
    SDValue InRegSize
1602
18
      = DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), DivBits));
1603
18
    Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);
1604
18
    Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);
1605
18
  } else {
1606
18
    SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT);
1607
18
    Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);
1608
18
    Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);
1609
18
  }
1610
36
1611
36
  return DAG.getMergeValues({ Div, Rem }, DL);
1612
36
}
1613
1614
void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1615
                                      SelectionDAG &DAG,
1616
81
                                      SmallVectorImpl<SDValue> &Results) const {
1617
81
  SDLoc DL(Op);
1618
81
  EVT VT = Op.getValueType();
1619
81
1620
81
  assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64");
1621
81
1622
81
  EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1623
81
1624
81
  SDValue One = DAG.getConstant(1, DL, HalfVT);
1625
81
  SDValue Zero = DAG.getConstant(0, DL, HalfVT);
1626
81
1627
81
  //HiLo split
1628
81
  SDValue LHS = Op.getOperand(0);
1629
81
  SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1630
81
  SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);
1631
81
1632
81
  SDValue RHS = Op.getOperand(1);
1633
81
  SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1634
81
  SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);
1635
81
1636
81
  if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1637
81
      
DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))16
) {
1638
16
1639
16
    SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1640
16
                              LHS_Lo, RHS_Lo);
1641
16
1642
16
    SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(0), Zero});
1643
16
    SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
1644
16
1645
16
    Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
1646
16
    Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
1647
16
    return;
1648
16
  }
1649
65
1650
65
  if (isTypeLegal(MVT::i64)) {
1651
46
    // Compute denominator reciprocal.
1652
46
    unsigned FMAD = Subtarget->hasFP32Denormals() ?
1653
0
                    (unsigned)AMDGPUISD::FMAD_FTZ :
1654
46
                    (unsigned)ISD::FMAD;
1655
46
1656
46
    SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
1657
46
    SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
1658
46
    SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
1659
46
      DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
1660
46
      Cvt_Lo);
1661
46
    SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
1662
46
    SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,
1663
46
      DAG.getConstantFP(APInt(32, 0x5f7ffffc).bitsToFloat(), DL, MVT::f32));
1664
46
    SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,
1665
46
      DAG.getConstantFP(APInt(32, 0x2f800000).bitsToFloat(), DL, MVT::f32));
1666
46
    SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);
1667
46
    SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,
1668
46
      DAG.getConstantFP(APInt(32, 0xcf800000).bitsToFloat(), DL, MVT::f32),
1669
46
      Mul1);
1670
46
    SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);
1671
46
    SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);
1672
46
    SDValue Rcp64 = DAG.getBitcast(VT,
1673
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
1674
46
1675
46
    SDValue Zero64 = DAG.getConstant(0, DL, VT);
1676
46
    SDValue One64  = DAG.getConstant(1, DL, VT);
1677
46
    SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
1678
46
    SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
1679
46
1680
46
    SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
1681
46
    SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
1682
46
    SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
1683
46
    SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1684
46
                                    Zero);
1685
46
    SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
1686
46
                                    One);
1687
46
1688
46
    SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
1689
46
                                  Mulhi1_Lo, Zero1);
1690
46
    SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
1691
46
                                  Mulhi1_Hi, Add1_Lo.getValue(1));
1692
46
    SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
1693
46
    SDValue Add1 = DAG.getBitcast(VT,
1694
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
1695
46
1696
46
    SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
1697
46
    SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
1698
46
    SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1699
46
                                    Zero);
1700
46
    SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
1701
46
                                    One);
1702
46
1703
46
    SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
1704
46
                                  Mulhi2_Lo, Zero1);
1705
46
    SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
1706
46
                                   Mulhi2_Hi, Add1_Lo.getValue(1));
1707
46
    SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
1708
46
                                  Zero, Add2_Lo.getValue(1));
1709
46
    SDValue Add2 = DAG.getBitcast(VT,
1710
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
1711
46
    SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
1712
46
1713
46
    SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
1714
46
1715
46
    SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
1716
46
    SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
1717
46
    SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
1718
46
                                  Mul3_Lo, Zero1);
1719
46
    SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,
1720
46
                                  Mul3_Hi, Sub1_Lo.getValue(1));
1721
46
    SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);
1722
46
    SDValue Sub1 = DAG.getBitcast(VT,
1723
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Sub1_Lo, Sub1_Hi}));
1724
46
1725
46
    SDValue MinusOne = DAG.getConstant(0xffffffffu, DL, HalfVT);
1726
46
    SDValue C1 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, MinusOne, Zero,
1727
46
                                 ISD::SETUGE);
1728
46
    SDValue C2 = DAG.getSelectCC(DL, Sub1_Lo, RHS_Lo, MinusOne, Zero,
1729
46
                                 ISD::SETUGE);
1730
46
    SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ);
1731
46
1732
46
    // TODO: Here and below portions of the code can be enclosed into if/endif.
1733
46
    // Currently control flow is unconditional and we have 4 selects after
1734
46
    // potential endif to substitute PHIs.
1735
46
1736
46
    // if C3 != 0 ...
1737
46
    SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,
1738
46
                                  RHS_Lo, Zero1);
1739
46
    SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,
1740
46
                                  RHS_Hi, Sub1_Lo.getValue(1));
1741
46
    SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1742
46
                                  Zero, Sub2_Lo.getValue(1));
1743
46
    SDValue Sub2 = DAG.getBitcast(VT,
1744
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Sub2_Lo, Sub2_Hi}));
1745
46
1746
46
    SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);
1747
46
1748
46
    SDValue C4 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, MinusOne, Zero,
1749
46
                                 ISD::SETUGE);
1750
46
    SDValue C5 = DAG.getSelectCC(DL, Sub2_Lo, RHS_Lo, MinusOne, Zero,
1751
46
                                 ISD::SETUGE);
1752
46
    SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ);
1753
46
1754
46
    // if (C6 != 0)
1755
46
    SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);
1756
46
1757
46
    SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,
1758
46
                                  RHS_Lo, Zero1);
1759
46
    SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,
1760
46
                                  RHS_Hi, Sub2_Lo.getValue(1));
1761
46
    SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,
1762
46
                                  Zero, Sub3_Lo.getValue(1));
1763
46
    SDValue Sub3 = DAG.getBitcast(VT,
1764
46
                        DAG.getBuildVector(MVT::v2i32, DL, {Sub3_Lo, Sub3_Hi}));
1765
46
1766
46
    // endif C6
1767
46
    // endif C3
1768
46
1769
46
    SDValue Sel1 = DAG.getSelectCC(DL, C6, Zero, Add4, Add3, ISD::SETNE);
1770
46
    SDValue Div  = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE);
1771
46
1772
46
    SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);
1773
46
    SDValue Rem  = DAG.getSelectCC(DL, C3, Zero, Sel2, Sub1, ISD::SETNE);
1774
46
1775
46
    Results.push_back(Div);
1776
46
    Results.push_back(Rem);
1777
46
1778
46
    return;
1779
46
  }
1780
19
1781
19
  // r600 expandion.
1782
19
  // Get Speculative values
1783
19
  SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1784
19
  SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1785
19
1786
19
  SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ);
1787
19
  SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {REM_Lo, Zero});
1788
19
  REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);
1789
19
1790
19
  SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ);
1791
19
  SDValue DIV_Lo = Zero;
1792
19
1793
19
  const unsigned halfBitWidth = HalfVT.getSizeInBits();
1794
19
1795
627
  for (unsigned i = 0; i < halfBitWidth; 
++i608
) {
1796
608
    const unsigned bitPos = halfBitWidth - i - 1;
1797
608
    SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1798
608
    // Get value of high bit
1799
608
    SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1800
608
    HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);
1801
608
    HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1802
608
1803
608
    // Shift
1804
608
    REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1805
608
    // Add LHS high bit
1806
608
    REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1807
608
1808
608
    SDValue BIT = DAG.getConstant(1ULL << bitPos, DL, HalfVT);
1809
608
    SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE);
1810
608
1811
608
    DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1812
608
1813
608
    // Update REM
1814
608
    SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1815
608
    REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1816
608
  }
1817
19
1818
19
  SDValue DIV = DAG.getBuildVector(MVT::v2i32, DL, {DIV_Lo, DIV_Hi});
1819
19
  DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);
1820
19
  Results.push_back(DIV);
1821
19
  Results.push_back(REM);
1822
19
}
1823
1824
SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1825
179
                                           SelectionDAG &DAG) const {
1826
179
  SDLoc DL(Op);
1827
179
  EVT VT = Op.getValueType();
1828
179
1829
179
  if (VT == MVT::i64) {
1830
58
    SmallVector<SDValue, 2> Results;
1831
58
    LowerUDIVREM64(Op, DAG, Results);
1832
58
    return DAG.getMergeValues(Results, DL);
1833
58
  }
1834
121
1835
121
  if (VT == MVT::i32) {
1836
121
    if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1837
18
      return Res;
1838
103
  }
1839
103
1840
103
  SDValue Num = Op.getOperand(0);
1841
103
  SDValue Den = Op.getOperand(1);
1842
103
1843
103
  // RCP =  URECIP(Den) = 2^32 / Den + e
1844
103
  // e is rounding error.
1845
103
  SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1846
103
1847
103
  // RCP_LO = mul(RCP, Den) */
1848
103
  SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1849
103
1850
103
  // RCP_HI = mulhu (RCP, Den) */
1851
103
  SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1852
103
1853
103
  // NEG_RCP_LO = -RCP_LO
1854
103
  SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1855
103
                                                     RCP_LO);
1856
103
1857
103
  // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1858
103
  SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1859
103
                                           NEG_RCP_LO, RCP_LO,
1860
103
                                           ISD::SETEQ);
1861
103
  // Calculate the rounding error from the URECIP instruction
1862
103
  // E = mulhu(ABS_RCP_LO, RCP)
1863
103
  SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1864
103
1865
103
  // RCP_A_E = RCP + E
1866
103
  SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1867
103
1868
103
  // RCP_S_E = RCP - E
1869
103
  SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1870
103
1871
103
  // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1872
103
  SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1873
103
                                     RCP_A_E, RCP_S_E,
1874
103
                                     ISD::SETEQ);
1875
103
  // Quotient = mulhu(Tmp0, Num)
1876
103
  SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1877
103
1878
103
  // Num_S_Remainder = Quotient * Den
1879
103
  SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1880
103
1881
103
  // Remainder = Num - Num_S_Remainder
1882
103
  SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1883
103
1884
103
  // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1885
103
  SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1886
103
                                                 DAG.getConstant(-1, DL, VT),
1887
103
                                                 DAG.getConstant(0, DL, VT),
1888
103
                                                 ISD::SETUGE);
1889
103
  // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1890
103
  SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1891
103
                                                  Num_S_Remainder,
1892
103
                                                  DAG.getConstant(-1, DL, VT),
1893
103
                                                  DAG.getConstant(0, DL, VT),
1894
103
                                                  ISD::SETUGE);
1895
103
  // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1896
103
  SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1897
103
                                               Remainder_GE_Zero);
1898
103
1899
103
  // Calculate Division result:
1900
103
1901
103
  // Quotient_A_One = Quotient + 1
1902
103
  SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1903
103
                                       DAG.getConstant(1, DL, VT));
1904
103
1905
103
  // Quotient_S_One = Quotient - 1
1906
103
  SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1907
103
                                       DAG.getConstant(1, DL, VT));
1908
103
1909
103
  // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1910
103
  SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1911
103
                                     Quotient, Quotient_A_One, ISD::SETEQ);
1912
103
1913
103
  // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1914
103
  Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1915
103
                            Quotient_S_One, Div, ISD::SETEQ);
1916
103
1917
103
  // Calculate Rem result:
1918
103
1919
103
  // Remainder_S_Den = Remainder - Den
1920
103
  SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1921
103
1922
103
  // Remainder_A_Den = Remainder + Den
1923
103
  SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1924
103
1925
103
  // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1926
103
  SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1927
103
                                    Remainder, Remainder_S_Den, ISD::SETEQ);
1928
103
1929
103
  // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1930
103
  Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1931
103
                            Remainder_A_Den, Rem, ISD::SETEQ);
1932
103
  SDValue Ops[2] = {
1933
103
    Div,
1934
103
    Rem
1935
103
  };
1936
103
  return DAG.getMergeValues(Ops, DL);
1937
103
}
1938
1939
SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1940
84
                                           SelectionDAG &DAG) const {
1941
84
  SDLoc DL(Op);
1942
84
  EVT VT = Op.getValueType();
1943
84
1944
84
  SDValue LHS = Op.getOperand(0);
1945
84
  SDValue RHS = Op.getOperand(1);
1946
84
1947
84
  SDValue Zero = DAG.getConstant(0, DL, VT);
1948
84
  SDValue NegOne = DAG.getConstant(-1, DL, VT);
1949
84
1950
84
  if (VT == MVT::i32) {
1951
48
    if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1952
18
      return Res;
1953
66
  }
1954
66
1955
66
  if (VT == MVT::i64 &&
1956
66
      
DAG.ComputeNumSignBits(LHS) > 3236
&&
1957
66
      
DAG.ComputeNumSignBits(RHS) > 3212
) {
1958
12
    EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1959
12
1960
12
    //HiLo split
1961
12
    SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1962
12
    SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1963
12
    SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1964
12
                                 LHS_Lo, RHS_Lo);
1965
12
    SDValue Res[2] = {
1966
12
      DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1967
12
      DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1968
12
    };
1969
12
    return DAG.getMergeValues(Res, DL);
1970
12
  }
1971
54
1972
54
  SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1973
54
  SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1974
54
  SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1975
54
  SDValue RSign = LHSign; // Remainder sign is the same as LHS
1976
54
1977
54
  LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1978
54
  RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1979
54
1980
54
  LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1981
54
  RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1982
54
1983
54
  SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1984
54
  SDValue Rem = Div.getValue(1);
1985
54
1986
54
  Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1987
54
  Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1988
54
1989
54
  Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1990
54
  Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1991
54
1992
54
  SDValue Res[2] = {
1993
54
    Div,
1994
54
    Rem
1995
54
  };
1996
54
  return DAG.getMergeValues(Res, DL);
1997
54
}
1998
1999
// (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
2000
46
SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2001
46
  SDLoc SL(Op);
2002
46
  EVT VT = Op.getValueType();
2003
46
  SDValue X = Op.getOperand(0);
2004
46
  SDValue Y = Op.getOperand(1);
2005
46
2006
46
  // TODO: Should this propagate fast-math-flags?
2007
46
2008
46
  SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
2009
46
  SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
2010
46
  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
2011
46
2012
46
  return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
2013
46
}
2014
2015
31
SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2016
31
  SDLoc SL(Op);
2017
31
  SDValue Src = Op.getOperand(0);
2018
31
2019
31
  // result = trunc(src)
2020
31
  // if (src > 0.0 && src != result)
2021
31
  //   result += 1.0
2022
31
2023
31
  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2024
31
2025
31
  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2026
31
  const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2027
31
2028
31
  EVT SetCCVT =
2029
31
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2030
31
2031
31
  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
2032
31
  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2033
31
  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2034
31
2035
31
  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
2036
31
  // TODO: Should this propagate fast-math-flags?
2037
31
  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2038
31
}
2039
2040
static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL,
2041
91
                                  SelectionDAG &DAG) {
2042
91
  const unsigned FractBits = 52;
2043
91
  const unsigned ExpBits = 11;
2044
91
2045
91
  SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
2046
91
                                Hi,
2047
91
                                DAG.getConstant(FractBits - 32, SL, MVT::i32),
2048
91
                                DAG.getConstant(ExpBits, SL, MVT::i32));
2049
91
  SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
2050
91
                            DAG.getConstant(1023, SL, MVT::i32));
2051
91
2052
91
  return Exp;
2053
91
}
2054
2055
75
SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2056
75
  SDLoc SL(Op);
2057
75
  SDValue Src = Op.getOperand(0);
2058
75
2059
75
  assert(Op.getValueType() == MVT::f64);
2060
75
2061
75
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2062
75
  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2063
75
2064
75
  SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2065
75
2066
75
  // Extract the upper half, since this is where we will find the sign and
2067
75
  // exponent.
2068
75
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2069
75
2070
75
  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2071
75
2072
75
  const unsigned FractBits = 52;
2073
75
2074
75
  // Extract the sign bit.
2075
75
  const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2076
75
  SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2077
75
2078
75
  // Extend back to 64-bits.
2079
75
  SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit});
2080
75
  SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2081
75
2082
75
  SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2083
75
  const SDValue FractMask
2084
75
    = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2085
75
2086
75
  SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2087
75
  SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2088
75
  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2089
75
2090
75
  EVT SetCCVT =
2091
75
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2092
75
2093
75
  const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2094
75
2095
75
  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2096
75
  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2097
75
2098
75
  SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2099
75
  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2100
75
2101
75
  return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2102
75
}
2103
2104
14
SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2105
14
  SDLoc SL(Op);
2106
14
  SDValue Src = Op.getOperand(0);
2107
14
2108
14
  assert(Op.getValueType() == MVT::f64);
2109
14
2110
14
  APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
2111
14
  SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2112
14
  SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2113
14
2114
14
  // TODO: Should this propagate fast-math-flags?
2115
14
2116
14
  SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2117
14
  SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2118
14
2119
14
  SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2120
14
2121
14
  APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
2122
14
  SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2123
14
2124
14
  EVT SetCCVT =
2125
14
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2126
14
  SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2127
14
2128
14
  return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2129
14
}
2130
2131
48
SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2132
48
  // FNEARBYINT and FRINT are the same, except in their handling of FP
2133
48
  // exceptions. Those aren't really meaningful for us, and OpenCL only has
2134
48
  // rint, so just treat them as equivalent.
2135
48
  return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2136
48
}
2137
2138
// XXX - May require not supporting f32 denormals?
2139
2140
// Don't handle v2f16. The extra instructions to scalarize and repack around the
2141
// compare and vselect end up producing worse code than scalarizing the whole
2142
// operation.
2143
77
SDValue AMDGPUTargetLowering::LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const {
2144
77
  SDLoc SL(Op);
2145
77
  SDValue X = Op.getOperand(0);
2146
77
  EVT VT = Op.getValueType();
2147
77
2148
77
  SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);
2149
77
2150
77
  // TODO: Should this propagate fast-math-flags?
2151
77
2152
77
  SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
2153
77
2154
77
  SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);
2155
77
2156
77
  const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
2157
77
  const SDValue One = DAG.getConstantFP(1.0, SL, VT);
2158
77
  const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
2159
77
2160
77
  SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
2161
77
2162
77
  EVT SetCCVT =
2163
77
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
2164
77
2165
77
  SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2166
77
2167
77
  SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);
2168
77
2169
77
  return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2170
77
}
2171
2172
16
SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2173
16
  SDLoc SL(Op);
2174
16
  SDValue X = Op.getOperand(0);
2175
16
2176
16
  SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2177
16
2178
16
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2179
16
  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2180
16
  const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2181
16
  const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2182
16
  EVT SetCCVT =
2183
16
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2184
16
2185
16
  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2186
16
2187
16
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2188
16
2189
16
  SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2190
16
2191
16
  const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2192
16
                                       MVT::i64);
2193
16
2194
16
  SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2195
16
  SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2196
16
                          DAG.getConstant(INT64_C(0x0008000000000000), SL,
2197
16
                                          MVT::i64),
2198
16
                          Exp);
2199
16
2200
16
  SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2201
16
  SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2202
16
                              DAG.getConstant(0, SL, MVT::i64), Tmp0,
2203
16
                              ISD::SETNE);
2204
16
2205
16
  SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2206
16
                             D, DAG.getConstant(0, SL, MVT::i64));
2207
16
  SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2208
16
2209
16
  K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2210
16
  K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2211
16
2212
16
  SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2213
16
  SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2214
16
  SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2215
16
2216
16
  SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2217
16
                            ExpEqNegOne,
2218
16
                            DAG.getConstantFP(1.0, SL, MVT::f64),
2219
16
                            DAG.getConstantFP(0.0, SL, MVT::f64));
2220
16
2221
16
  SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2222
16
2223
16
  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2224
16
  K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2225
16
2226
16
  return K;
2227
16
}
2228
2229
93
SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2230
93
  EVT VT = Op.getValueType();
2231
93
2232
93
  if (VT == MVT::f32 || 
VT == MVT::f1622
)
2233
77
    return LowerFROUND32_16(Op, DAG);
2234
16
2235
16
  if (VT == MVT::f64)
2236
16
    return LowerFROUND64(Op, DAG);
2237
0
2238
0
  llvm_unreachable("unhandled type");
2239
0
}
2240
2241
0
SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2242
0
  SDLoc SL(Op);
2243
0
  SDValue Src = Op.getOperand(0);
2244
0
2245
0
  // result = trunc(src);
2246
0
  // if (src < 0.0 && src != result)
2247
0
  //   result += -1.0.
2248
0
2249
0
  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2250
0
2251
0
  const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2252
0
  const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2253
0
2254
0
  EVT SetCCVT =
2255
0
      getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2256
0
2257
0
  SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2258
0
  SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2259
0
  SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2260
0
2261
0
  SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2262
0
  // TODO: Should this propagate fast-math-flags?
2263
0
  return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2264
0
}
2265
2266
SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2267
74
                                        double Log2BaseInverted) const {
2268
74
  EVT VT = Op.getValueType();
2269
74
2270
74
  SDLoc SL(Op);
2271
74
  SDValue Operand = Op.getOperand(0);
2272
74
  SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);
2273
74
  SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT);
2274
74
2275
74
  return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);
2276
74
}
2277
2278
// Return M_LOG2E of appropriate type
2279
50
static SDValue getLog2EVal(SelectionDAG &DAG, const SDLoc &SL, EVT VT) {
2280
50
  switch (VT.getScalarType().getSimpleVT().SimpleTy) {
2281
50
  case MVT::f32:
2282
37
    return DAG.getConstantFP(1.44269504088896340735992468100189214f, SL, VT);
2283
50
  case MVT::f16:
2284
13
    return DAG.getConstantFP(
2285
13
      APFloat(APFloat::IEEEhalf(), "1.44269504088896340735992468100189214"),
2286
13
      SL, VT);
2287
50
  case MVT::f64:
2288
0
    return DAG.getConstantFP(
2289
0
      APFloat(APFloat::IEEEdouble(), "0x1.71547652b82fep+0"), SL, VT);
2290
50
  default:
2291
0
    llvm_unreachable("unsupported fp type");
2292
50
  }
2293
50
}
2294
2295
// exp2(M_LOG2E_F * f);
2296
50
SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
2297
50
  EVT VT = Op.getValueType();
2298
50
  SDLoc SL(Op);
2299
50
  SDValue Src = Op.getOperand(0);
2300
50
2301
50
  const SDValue K = getLog2EVal(DAG, SL, VT);
2302
50
  SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2303
50
  return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
2304
50
}
2305
2306
4.12k
static bool isCtlzOpc(unsigned Opc) {
2307
4.12k
  return Opc == ISD::CTLZ || 
Opc == ISD::CTLZ_ZERO_UNDEF4.07k
;
2308
4.12k
}
2309
2310
8.39k
static bool isCttzOpc(unsigned Opc) {
2311
8.39k
  return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
2312
8.39k
}
2313
2314
455
SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2315
455
  SDLoc SL(Op);
2316
455
  SDValue Src = Op.getOperand(0);
2317
455
  bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
2318
455
                   
Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF342
;
2319
455
2320
455
  unsigned ISDOpc, NewOpc;
2321
455
  if (isCtlzOpc(Op.getOpcode())) {
2322
342
    ISDOpc = ISD::CTLZ_ZERO_UNDEF;
2323
342
    NewOpc = AMDGPUISD::FFBH_U32;
2324
342
  } else 
if (113
isCttzOpc(Op.getOpcode())113
) {
2325
113
    ISDOpc = ISD::CTTZ_ZERO_UNDEF;
2326
113
    NewOpc = AMDGPUISD::FFBL_B32;
2327
113
  } else
2328
113
    
llvm_unreachable0
("Unexpected OPCode!!!");
2329
455
2330
455
2331
455
  if (ZeroUndef && 
Src.getValueType() == MVT::i32447
)
2332
359
    return DAG.getNode(NewOpc, SL, MVT::i32, Src);
2333
96
2334
96
  SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2335
96
2336
96
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2337
96
  const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2338
96
2339
96
  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2340
96
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2341
96
2342
96
  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2343
96
                                   *DAG.getContext(), MVT::i32);
2344
96
2345
96
  SDValue HiOrLo = isCtlzOpc(Op.getOpcode()) ? 
Hi82
:
Lo14
;
2346
96
  SDValue Hi0orLo0 = DAG.getSetCC(SL, SetCCVT, HiOrLo, Zero, ISD::SETEQ);
2347
96
2348
96
  SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);
2349
96
  SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);
2350
96
2351
96
  const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2352
96
  SDValue Add, NewOpr;
2353
96
  if (isCtlzOpc(Op.getOpcode())) {
2354
82
    Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);
2355
82
    // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2356
82
    NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);
2357
82
  } else {
2358
14
    Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);
2359
14
    // cttz(x) = lo_32(x) == 0 ? cttz(hi_32(x)) + 32 : cttz(lo_32(x))
2360
14
    NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);
2361
14
  }
2362
96
2363
96
  if (!ZeroUndef) {
2364
8
    // Test if the full 64-bit input is zero.
2365
8
2366
8
    // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2367
8
    // which we probably don't want.
2368
8
    SDValue LoOrHi = isCtlzOpc(Op.getOpcode()) ? Lo : 
Hi0
;
2369
8
    SDValue Lo0OrHi0 = DAG.getSetCC(SL, SetCCVT, LoOrHi, Zero, ISD::SETEQ);
2370
8
    SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);
2371
8
2372
8
    // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2373
8
    // with the same cycles, otherwise it is slower.
2374
8
    // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2375
8
    // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2376
8
2377
8
    const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2378
8
2379
8
    // The instruction returns -1 for 0 input, but the defined intrinsic
2380
8
    // behavior is to return the number of bits.
2381
8
    NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2382
8
                         SrcIsZero, Bits32, NewOpr);
2383
8
  }
2384
96
2385
96
  return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
2386
96
}
2387
2388
SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2389
67
                                               bool Signed) const {
2390
67
  // Unsigned
2391
67
  // cul2f(ulong u)
2392
67
  //{
2393
67
  //  uint lz = clz(u);
2394
67
  //  uint e = (u != 0) ? 127U + 63U - lz : 0;
2395
67
  //  u = (u << lz) & 0x7fffffffffffffffUL;
2396
67
  //  ulong t = u & 0xffffffffffUL;
2397
67
  //  uint v = (e << 23) | (uint)(u >> 40);
2398
67
  //  uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2399
67
  //  return as_float(v + r);
2400
67
  //}
2401
67
  // Signed
2402
67
  // cl2f(long l)
2403
67
  //{
2404
67
  //  long s = l >> 63;
2405
67
  //  float r = cul2f((l + s) ^ s);
2406
67
  //  return s ? -r : r;
2407
67
  //}
2408
67
2409
67
  SDLoc SL(Op);
2410
67
  SDValue Src = Op.getOperand(0);
2411
67
  SDValue L = Src;
2412
67
2413
67
  SDValue S;
2414
67
  if (Signed) {
2415
32
    const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2416
32
    S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2417
32
2418
32
    SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2419
32
    L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2420
32
  }
2421
67
2422
67
  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2423
67
                                   *DAG.getContext(), MVT::f32);
2424
67
2425
67
2426
67
  SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2427
67
  SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2428
67
  SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2429
67
  LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2430
67
2431
67
  SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2432
67
  SDValue E = DAG.getSelect(SL, MVT::i32,
2433
67
    DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2434
67
    DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2435
67
    ZeroI32);
2436
67
2437
67
  SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2438
67
    DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2439
67
    DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2440
67
2441
67
  SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2442
67
                          DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2443
67
2444
67
  SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2445
67
                             U, DAG.getConstant(40, SL, MVT::i64));
2446
67
2447
67
  SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2448
67
    DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2449
67
    DAG.getNode(ISD::TRUNCATE, SL, MVT::i32,  UShl));
2450
67
2451
67
  SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2452
67
  SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2453
67
  SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2454
67
2455
67
  SDValue One = DAG.getConstant(1, SL, MVT::i32);
2456
67
2457
67
  SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2458
67
2459
67
  SDValue R = DAG.getSelect(SL, MVT::i32,
2460
67
    RCmp,
2461
67
    One,
2462
67
    DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2463
67
  R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2464
67
  R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2465
67
2466
67
  if (!Signed)
2467
35
    return R;
2468
32
2469
32
  SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2470
32
  return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2471
32
}
2472
2473
SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2474
10
                                               bool Signed) const {
2475
10
  SDLoc SL(Op);
2476
10
  SDValue Src = Op.getOperand(0);
2477
10
2478
10
  SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2479
10
2480
10
  SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2481
10
                           DAG.getConstant(0, SL, MVT::i32));
2482
10
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2483
10
                           DAG.getConstant(1, SL, MVT::i32));
2484
10
2485
10
  SDValue CvtHi = DAG.getNode(Signed ? 
ISD::SINT_TO_FP2
:
ISD::UINT_TO_FP8
,
2486
10
                              SL, MVT::f64, Hi);
2487
10
2488
10
  SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2489
10
2490
10
  SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2491
10
                              DAG.getConstant(32, SL, MVT::i32));
2492
10
  // TODO: Should this propagate fast-math-flags?
2493
10
  return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2494
10
}
2495
2496
SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2497
51
                                               SelectionDAG &DAG) const {
2498
51
  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2499
51
         "operation should be legal");
2500
51
2501
51
  // TODO: Factor out code common with LowerSINT_TO_FP.
2502
51
2503
51
  EVT DestVT = Op.getValueType();
2504
51
  if (Subtarget->has16BitInsts() && 
DestVT == MVT::f1625
) {
2505
8
    SDLoc DL(Op);
2506
8
    SDValue Src = Op.getOperand(0);
2507
8
2508
8
    SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2509
8
    SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2510
8
    SDValue FPRound =
2511
8
        DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2512
8
2513
8
    return FPRound;
2514
8
  }
2515
43
2516
43
  if (DestVT == MVT::f32)
2517
35
    return LowerINT_TO_FP32(Op, DAG, false);
2518
8
2519
8
  assert(DestVT == MVT::f64);
2520
8
  return LowerINT_TO_FP64(Op, DAG, false);
2521
8
}
2522
2523
SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2524
42
                                              SelectionDAG &DAG) const {
2525
42
  assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2526
42
         "operation should be legal");
2527
42
2528
42
  // TODO: Factor out code common with LowerUINT_TO_FP.
2529
42
2530
42
  EVT DestVT = Op.getValueType();
2531
42
  if (Subtarget->has16BitInsts() && 
DestVT == MVT::f1624
) {
2532
8
    SDLoc DL(Op);
2533
8
    SDValue Src = Op.getOperand(0);
2534
8
2535
8
    SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);
2536
8
    SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SDLoc(Op));
2537
8
    SDValue FPRound =
2538
8
        DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2539
8
2540
8
    return FPRound;
2541
8
  }
2542
34
2543
34
  if (DestVT == MVT::f32)
2544
32
    return LowerINT_TO_FP32(Op, DAG, true);
2545
2
2546
2
  assert(DestVT == MVT::f64);
2547
2
  return LowerINT_TO_FP64(Op, DAG, true);
2548
2
}
2549
2550
SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2551
16
                                               bool Signed) const {
2552
16
  SDLoc SL(Op);
2553
16
2554
16
  SDValue Src = Op.getOperand(0);
2555
16
2556
16
  SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2557
16
2558
16
  SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2559
16
                                 MVT::f64);
2560
16
  SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2561
16
                                 MVT::f64);
2562
16
  // TODO: Should this propagate fast-math-flags?
2563
16
  SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2564
16
2565
16
  SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2566
16
2567
16
2568
16
  SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2569
16
2570
16
  SDValue Hi = DAG.getNode(Signed ? 
ISD::FP_TO_SINT2
:
ISD::FP_TO_UINT14
, SL,
2571
16
                           MVT::i32, FloorMul);
2572
16
  SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2573
16
2574
16
  SDValue Result = DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi});
2575
16
2576
16
  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2577
16
}
2578
2579
1.01k
SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2580
1.01k
  SDLoc DL(Op);
2581
1.01k
  SDValue N0 = Op.getOperand(0);
2582
1.01k
2583
1.01k
  // Convert to target node to get known bits
2584
1.01k
  if (N0.getValueType() == MVT::f32)
2585
961
    return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2586
49
2587
49
  if (getTargetMachine().Options.UnsafeFPMath) {
2588
10
    // There is a generic expand for FP_TO_FP16 with unsafe fast math.
2589
10
    return SDValue();
2590
10
  }
2591
39
2592
39
  assert(N0.getSimpleValueType() == MVT::f64);
2593
39
2594
39
  // f64 -> f16 conversion using round-to-nearest-even rounding mode.
2595
39
  const unsigned ExpMask = 0x7ff;
2596
39
  const unsigned ExpBiasf64 = 1023;
2597
39
  const unsigned ExpBiasf16 = 15;
2598
39
  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2599
39
  SDValue One = DAG.getConstant(1, DL, MVT::i32);
2600
39
  SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2601
39
  SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,
2602
39
                           DAG.getConstant(32, DL, MVT::i64));
2603
39
  UH = DAG.getZExtOrTrunc(UH, DL, MVT::i32);
2604
39
  U = DAG.getZExtOrTrunc(U, DL, MVT::i32);
2605
39
  SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2606
39
                          DAG.getConstant(20, DL, MVT::i64));
2607
39
  E = DAG.getNode(ISD::AND, DL, MVT::i32, E,
2608
39
                  DAG.getConstant(ExpMask, DL, MVT::i32));
2609
39
  // Subtract the fp64 exponent bias (1023) to get the real exponent and
2610
39
  // add the f16 bias (15) to get the biased exponent for the f16 format.
2611
39
  E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,
2612
39
                  DAG.getConstant(-ExpBiasf64 + ExpBiasf16, DL, MVT::i32));
2613
39
2614
39
  SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2615
39
                          DAG.getConstant(8, DL, MVT::i32));
2616
39
  M = DAG.getNode(ISD::AND, DL, MVT::i32, M,
2617
39
                  DAG.getConstant(0xffe, DL, MVT::i32));
2618
39
2619
39
  SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,
2620
39
                                  DAG.getConstant(0x1ff, DL, MVT::i32));
2621
39
  MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);
2622
39
2623
39
  SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ);
2624
39
  M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);
2625
39
2626
39
  // (M != 0 ? 0x0200 : 0) | 0x7c00;
2627
39
  SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,
2628
39
      DAG.getSelectCC(DL, M, Zero, DAG.getConstant(0x0200, DL, MVT::i32),
2629
39
                      Zero, ISD::SETNE), DAG.getConstant(0x7c00, DL, MVT::i32));
2630
39
2631
39
  // N = M | (E << 12);
2632
39
  SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2633
39
      DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2634
39
                  DAG.getConstant(12, DL, MVT::i32)));
2635
39
2636
39
  // B = clamp(1-E, 0, 13);
2637
39
  SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,
2638
39
                                  One, E);
2639
39
  SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);
2640
39
  B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,
2641
39
                  DAG.getConstant(13, DL, MVT::i32));
2642
39
2643
39
  SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,
2644
39
                                   DAG.getConstant(0x1000, DL, MVT::i32));
2645
39
2646
39
  SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);
2647
39
  SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2648
39
  SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE);
2649
39
  D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
2650
39
2651
39
  SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
2652
39
  SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,
2653
39
                              DAG.getConstant(0x7, DL, MVT::i32));
2654
39
  V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,
2655
39
                  DAG.getConstant(2, DL, MVT::i32));
2656
39
  SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32),
2657
39
                               One, Zero, ISD::SETEQ);
2658
39
  SDValue V1 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(5, DL, MVT::i32),
2659
39
                               One, Zero, ISD::SETGT);
2660
39
  V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);
2661
39
  V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);
2662
39
2663
39
  V = DAG.getSelectCC(DL, E, DAG.getConstant(30, DL, MVT::i32),
2664
39
                      DAG.getConstant(0x7c00, DL, MVT::i32), V, ISD::SETGT);
2665
39
  V = DAG.getSelectCC(DL, E, DAG.getConstant(1039, DL, MVT::i32),
2666
39
                      I, V, ISD::SETEQ);
2667
39
2668
39
  // Extract the sign bit.
2669
39
  SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,
2670
39
                            DAG.getConstant(16, DL, MVT::i32));
2671
39
  Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
2672
39
                     DAG.getConstant(0x8000, DL, MVT::i32));
2673
39
2674
39
  V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
2675
39
  return DAG.getZExtOrTrunc(V, DL, Op.getValueType());
2676
39
}
2677
2678
SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2679
65
                                              SelectionDAG &DAG) const {
2680
65
  SDValue Src = Op.getOperand(0);
2681
65
2682
65
  // TODO: Factor out code common with LowerFP_TO_UINT.
2683
65
2684
65
  EVT SrcVT = Src.getValueType();
2685
65
  if (Subtarget->has16BitInsts() && 
SrcVT == MVT::f1633
) {
2686
3
    SDLoc DL(Op);
2687
3
2688
3
    SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2689
3
    SDValue FpToInt32 =
2690
3
        DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2691
3
2692
3
    return FpToInt32;
2693
3
  }
2694
62
2695
62
  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2696
2
    return LowerFP64_TO_INT(Op, DAG, true);
2697
60
2698
60
  return SDValue();
2699
60
}
2700
2701
SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2702
37
                                              SelectionDAG &DAG) const {
2703
37
  SDValue Src = Op.getOperand(0);
2704
37
2705
37
  // TODO: Factor out code common with LowerFP_TO_SINT.
2706
37
2707
37
  EVT SrcVT = Src.getValueType();
2708
37
  if (Subtarget->has16BitInsts() && 
SrcVT == MVT::f1613
) {
2709
3
    SDLoc DL(Op);
2710
3
2711
3
    SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
2712
3
    SDValue FpToInt32 =
2713
3
        DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
2714
3
2715
3
    return FpToInt32;
2716
3
  }
2717
34
2718
34
  if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2719
14
    return LowerFP64_TO_INT(Op, DAG, false);
2720
20
2721
20
  return SDValue();
2722
20
}
2723
2724
SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2725
16
                                                     SelectionDAG &DAG) const {
2726
16
  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2727
16
  MVT VT = Op.getSimpleValueType();
2728
16
  MVT ScalarVT = VT.getScalarType();
2729
16
2730
16
  assert(VT.isVector());
2731
16
2732
16
  SDValue Src = Op.getOperand(0);
2733
16
  SDLoc DL(Op);
2734
16
2735
16
  // TODO: Don't scalarize on Evergreen?
2736
16
  unsigned NElts = VT.getVectorNumElements();
2737
16
  SmallVector<SDValue, 8> Args;
2738
16
  DAG.ExtractVectorElements(Src, Args, 0, NElts);
2739
16
2740
16
  SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2741
66
  for (unsigned I = 0; I < NElts; 
++I50
)
2742
50
    Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2743
16
2744
16
  return DAG.getBuildVector(VT, DL, Args);
2745
16
}
2746
2747
//===----------------------------------------------------------------------===//
2748
// Custom DAG optimizations
2749
//===----------------------------------------------------------------------===//
2750
2751
14.6k
static bool isU24(SDValue Op, SelectionDAG &DAG) {
2752
14.6k
  return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2753
14.6k
}
2754
2755
7.46k
static bool isI24(SDValue Op, SelectionDAG &DAG) {
2756
7.46k
  EVT VT = Op.getValueType();
2757
7.46k
  return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2758
7.46k
                                     // as unsigned 24-bit values.
2759
7.46k
    AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2760
7.46k
}
2761
2762
static SDValue simplifyI24(SDNode *Node24,
2763
8.38k
                           TargetLowering::DAGCombinerInfo &DCI) {
2764
8.38k
  SelectionDAG &DAG = DCI.DAG;
2765
8.38k
  SDValue LHS = Node24->getOperand(0);
2766
8.38k
  SDValue RHS = Node24->getOperand(1);
2767
8.38k
2768
8.38k
  APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
2769
8.38k
2770
8.38k
  // First try to simplify using GetDemandedBits which allows the operands to
2771
8.38k
  // have other uses, but will only perform simplifications that involve
2772
8.38k
  // bypassing some nodes for this user.
2773
8.38k
  SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
2774
8.38k
  SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
2775
8.38k
  if (DemandedLHS || 
DemandedRHS8.00k
)
2776
403
    return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),
2777
403
                       DemandedLHS ? 
DemandedLHS383
:
LHS20
,
2778
403
                       DemandedRHS ? 
DemandedRHS362
:
RHS41
);
2779
7.98k
2780
7.98k
  // Now try SimplifyDemandedBits which can simplify the nodes used by our
2781
7.98k
  // operands if this node is the only user.
2782
7.98k
  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2783
7.98k
  if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI))
2784
240
    return SDValue(Node24, 0);
2785
7.74k
  if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI))
2786
166
    return SDValue(Node24, 0);
2787
7.57k
2788
7.57k
  return SDValue();
2789
7.57k
}
2790
2791
template <typename IntTy>
2792
static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
2793
48
                               uint32_t Width, const SDLoc &DL) {
2794
48
  if (Width + Offset < 32) {
2795
20
    uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2796
20
    IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2797
20
    return DAG.getConstant(Result, DL, MVT::i32);
2798
20
  }
2799
28
2800
28
  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2801
28
}
AMDGPUISelLowering.cpp:llvm::SDValue constantFoldBFE<int>(llvm::SelectionDAG&, int, unsigned int, unsigned int, llvm::SDLoc const&)
Line
Count
Source
2793
24
                               uint32_t Width, const SDLoc &DL) {
2794
24
  if (Width + Offset < 32) {
2795
10
    uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2796
10
    IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2797
10
    return DAG.getConstant(Result, DL, MVT::i32);
2798
10
  }
2799
14
2800
14
  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2801
14
}
AMDGPUISelLowering.cpp:llvm::SDValue constantFoldBFE<unsigned int>(llvm::SelectionDAG&, unsigned int, unsigned int, unsigned int, llvm::SDLoc const&)
Line
Count
Source
2793
24
                               uint32_t Width, const SDLoc &DL) {
2794
24
  if (Width + Offset < 32) {
2795
10
    uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2796
10
    IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2797
10
    return DAG.getConstant(Result, DL, MVT::i32);
2798
10
  }
2799
14
2800
14
  return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2801
14
}
2802
2803
217k
static bool hasVolatileUser(SDNode *Val) {
2804
433k
  for (SDNode *U : Val->uses()) {
2805
433k
    if (MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2806
76.6k
      if (M->isVolatile())
2807
6.63k
        return true;
2808
76.6k
    }
2809
433k
  }
2810
217k
2811
217k
  
return false211k
;
2812
217k
}
2813
2814
311k
bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2815
311k
  // i32 vectors are the canonical memory type.
2816
311k
  if (VT.getScalarType() == MVT::i32 || 
isTypeLegal(VT)189k
)
2817
292k
    return false;
2818
18.8k
2819
18.8k
  if (!VT.isByteSized())
2820
1.93k
    return false;
2821
16.8k
2822
16.8k
  unsigned Size = VT.getStoreSize();
2823
16.8k
2824
16.8k
  if ((Size == 1 || 
Size == 212.2k
||
Size == 48.01k
) &&
!VT.isVector()10.3k
)
2825
8.41k
    return false;
2826
8.46k
2827
8.46k
  if (Size == 3 || 
(8.04k
Size > 48.04k
&&
(Size % 4 != 0)6.11k
))
2828
1.27k
    return false;
2829
7.19k
2830
7.19k
  return true;
2831
7.19k
}
2832
2833
// Find a load or store from corresponding pattern root.
2834
// Roots may be build_vector, bitconvert or their combinations.
2835
3.60k
static MemSDNode* findMemSDNode(SDNode *N) {
2836
3.60k
  N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode();
2837
3.60k
  if (MemSDNode *MN = dyn_cast<MemSDNode>(N))
2838
3.60k
    return MN;
2839
0
  assert(isa<BuildVectorSDNode>(N));
2840
0
  for (SDValue V : N->op_values())
2841
0
    if (MemSDNode *MN =
2842
0
          dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
2843
0
      return MN;
2844
0
  llvm_unreachable("cannot find MemSDNode in the pattern!");
2845
0
}
2846
2847
bool AMDGPUTargetLowering::SelectFlatOffset(bool IsSigned,
2848
                                            SelectionDAG &DAG,
2849
                                            SDNode *N,
2850
                                            SDValue Addr,
2851
                                            SDValue &VAddr,
2852
                                            SDValue &Offset,
2853
19.1k
                                            SDValue &SLC) const {
2854
19.1k
  const GCNSubtarget &ST =
2855
19.1k
        DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
2856
19.1k
  int64_t OffsetVal = 0;
2857
19.1k
2858
19.1k
  if (ST.hasFlatInstOffsets() &&
2859
19.1k
      
(7.78k
!ST.hasFlatSegmentOffsetBug()7.78k
||
2860
7.78k
       
findMemSDNode(N)->getAddressSpace() != AMDGPUAS::FLAT_ADDRESS2.10k
) &&
2861
19.1k
      
DAG.isBaseWithConstantOffset(Addr)6.82k
) {
2862
1.50k
    SDValue N0 = Addr.getOperand(0);
2863
1.50k
    SDValue N1 = Addr.getOperand(1);
2864
1.50k
    int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();
2865
1.50k
2866
1.50k
    const SIInstrInfo *TII = ST.getInstrInfo();
2867
1.50k
    if (TII->isLegalFLATOffset(COffsetVal, findMemSDNode(N)->getAddressSpace(),
2868
1.50k
                               IsSigned)) {
2869
1.42k
      Addr = N0;
2870
1.42k
      OffsetVal = COffsetVal;
2871
1.42k
    }
2872
1.50k
  }
2873
19.1k
2874
19.1k
  VAddr = Addr;
2875
19.1k
  Offset = DAG.getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
2876
19.1k
  SLC = DAG.getTargetConstant(0, SDLoc(), MVT::i1);
2877
19.1k
2878
19.1k
  return true;
2879
19.1k
}
2880
2881
// Replace load of an illegal type with a store of a bitcast to a friendlier
2882
// type.
2883
SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2884
277k
                                                 DAGCombinerInfo &DCI) const {
2885
277k
  if (!DCI.isBeforeLegalize())
2886
29.9k
    return SDValue();
2887
247k
2888
247k
  LoadSDNode *LN = cast<LoadSDNode>(N);
2889
247k
  if (LN->isVolatile() || 
!ISD::isNormalLoad(LN)237k
||
hasVolatileUser(LN)217k
)
2890
36.3k
    return SDValue();
2891
211k
2892
211k
  SDLoc SL(N);
2893
211k
  SelectionDAG &DAG = DCI.DAG;
2894
211k
  EVT VT = LN->getMemoryVT();
2895
211k
2896
211k
  unsigned Size = VT.getStoreSize();
2897
211k
  unsigned Align = LN->getAlignment();
2898
211k
  if (Align < Size && 
isTypeLegal(VT)89.4k
) {
2899
79.1k
    bool IsFast;
2900
79.1k
    unsigned AS = LN->getAddressSpace();
2901
79.1k
2902
79.1k
    // Expand unaligned loads earlier than legalization. Due to visitation order
2903
79.1k
    // problems during legalization, the emitted instructions to pack and unpack
2904
79.1k
    // the bytes again are not eliminated in the case of an unaligned copy.
2905
79.1k
    if (!allowsMisalignedMemoryAccesses(
2906
79.1k
            VT, AS, Align, LN->getMemOperand()->getFlags(), &IsFast)) {
2907
332
      if (VT.isVector())
2908
50
        return scalarizeVectorLoad(LN, DAG);
2909
282
2910
282
      SDValue Ops[2];
2911
282
      std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(LN, DAG);
2912
282
      return DAG.getMergeValues(Ops, SDLoc(N));
2913
282
    }
2914
78.8k
2915
78.8k
    if (!IsFast)
2916
23
      return SDValue();
2917
210k
  }
2918
210k
2919
210k
  if (!shouldCombineMemoryType(VT))
2920
205k
    return SDValue();
2921
4.97k
2922
4.97k
  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2923
4.97k
2924
4.97k
  SDValue NewLoad
2925
4.97k
    = DAG.getLoad(NewVT, SL, LN->getChain(),
2926
4.97k
                  LN->getBasePtr(), LN->getMemOperand());
2927
4.97k
2928
4.97k
  SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);
2929
4.97k
  DCI.CombineTo(N, BC, NewLoad.getValue(1));
2930
4.97k
  return SDValue(N, 0);
2931
4.97k
}
2932
2933
// Replace store of an illegal type with a store of a bitcast to a friendlier
2934
// type.
2935
SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2936
157k
                                                  DAGCombinerInfo &DCI) const {
2937
157k
  if (!DCI.isBeforeLegalize())
2938
36.2k
    return SDValue();
2939
120k
2940
120k
  StoreSDNode *SN = cast<StoreSDNode>(N);
2941
120k
  if (SN->isVolatile() || 
!ISD::isNormalStore(SN)113k
)
2942
20.4k
    return SDValue();
2943
100k
2944
100k
  EVT VT = SN->getMemoryVT();
2945
100k
  unsigned Size = VT.getStoreSize();
2946
100k
2947
100k
  SDLoc SL(N);
2948
100k
  SelectionDAG &DAG = DCI.DAG;
2949
100k
  unsigned Align = SN->getAlignment();
2950
100k
  if (Align < Size && 
isTypeLegal(VT)14.3k
) {
2951
13.7k
    bool IsFast;
2952
13.7k
    unsigned AS = SN->getAddressSpace();
2953
13.7k
2954
13.7k
    // Expand unaligned stores earlier than legalization. Due to visitation
2955
13.7k
    // order problems during legalization, the emitted instructions to pack and
2956
13.7k
    // unpack the bytes again are not eliminated in the case of an unaligned
2957
13.7k
    // copy.
2958
13.7k
    if (!allowsMisalignedMemoryAccesses(
2959
13.7k
            VT, AS, Align, SN->getMemOperand()->getFlags(), &IsFast)) {
2960
287
      if (VT.isVector())
2961
55
        return scalarizeVectorStore(SN, DAG);
2962
232
2963
232
      return expandUnalignedStore(SN, DAG);
2964
232
    }
2965
13.5k
2966
13.5k
    if (!IsFast)
2967
0
      return SDValue();
2968
100k
  }
2969
100k
2970
100k
  if (!shouldCombineMemoryType(VT))
2971
97.9k
    return SDValue();
2972
2.21k
2973
2.21k
  EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
2974
2.21k
  SDValue Val = SN->getValue();
2975
2.21k
2976
2.21k
  //DCI.AddToWorklist(Val.getNode());
2977
2.21k
2978
2.21k
  bool OtherUses = !Val.hasOneUse();
2979
2.21k
  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);
2980
2.21k
  if (OtherUses) {
2981
33
    SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);
2982
33
    DAG.ReplaceAllUsesOfValueWith(Val, CastBack);
2983
33
  }
2984
2.21k
2985
2.21k
  return DAG.getStore(SN->getChain(), SL, CastVal,
2986
2.21k
                      SN->getBasePtr(), SN->getMemOperand());
2987
2.21k
}
2988
2989
// FIXME: This should go in generic DAG combiner with an isTruncateFree check,
2990
// but isTruncateFree is inaccurate for i16 now because of SALU vs. VALU
2991
// issues.
2992
SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
2993
13.2k
                                                        DAGCombinerInfo &DCI) const {
2994
13.2k
  SelectionDAG &DAG = DCI.DAG;
2995
13.2k
  SDValue N0 = N->getOperand(0);
2996
13.2k
2997
13.2k
  // (vt2 (assertzext (truncate vt0:x), vt1)) ->
2998
13.2k
  //     (vt2 (truncate (assertzext vt0:x, vt1)))
2999
13.2k
  if (N0.getOpcode() == ISD::TRUNCATE) {
3000
0
    SDValue N1 = N->getOperand(1);
3001
0
    EVT ExtVT = cast<VTSDNode>(N1)->getVT();
3002
0
    SDLoc SL(N);
3003
0
3004
0
    SDValue Src = N0.getOperand(0);
3005
0
    EVT SrcVT = Src.getValueType();
3006
0
    if (SrcVT.bitsGE(ExtVT)) {
3007
0
      SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);
3008
0
      return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);
3009
0
    }
3010
13.2k
  }
3011
13.2k
3012
13.2k
  return SDValue();
3013
13.2k
}
3014
/// Split the 64-bit value \p LHS into two 32-bit components, and perform the
3015
/// binary operation \p Opc to it with the corresponding constant operands.
3016
SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3017
  DAGCombinerInfo &DCI, const SDLoc &SL,
3018
  unsigned Opc, SDValue LHS,
3019
1.69k
  uint32_t ValLo, uint32_t ValHi) const {
3020
1.69k
  SelectionDAG &DAG = DCI.DAG;
3021
1.69k
  SDValue Lo, Hi;
3022
1.69k
  std::tie(Lo, Hi) = split64BitValue(LHS, DAG);
3023
1.69k
3024
1.69k
  SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32);
3025
1.69k
  SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32);
3026
1.69k
3027
1.69k
  SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);
3028
1.69k
  SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);
3029
1.69k
3030
1.69k
  // Re-visit the ands. It's possible we eliminated one of them and it could
3031
1.69k
  // simplify the vector.
3032
1.69k
  DCI.AddToWorklist(Lo.getNode());
3033
1.69k
  DCI.AddToWorklist(Hi.getNode());
3034
1.69k
3035
1.69k
  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd});
3036
1.69k
  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3037
1.69k
}
3038
3039
SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
3040
21.4k
                                                DAGCombinerInfo &DCI) const {
3041
21.4k
  EVT VT = N->getValueType(0);
3042
21.4k
3043
21.4k
  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3044
21.4k
  if (!RHS)
3045
3.83k
    return SDValue();
3046
17.5k
3047
17.5k
  SDValue LHS = N->getOperand(0);
3048
17.5k
  unsigned RHSVal = RHS->getZExtValue();
3049
17.5k
  if (!RHSVal)
3050
0
    return LHS;
3051
17.5k
3052
17.5k
  SDLoc SL(N);
3053
17.5k
  SelectionDAG &DAG = DCI.DAG;
3054
17.5k
3055
17.5k
  switch (LHS->getOpcode()) {
3056
17.5k
  default:
3057
11.7k
    break;
3058
17.5k
  case ISD::ZERO_EXTEND:
3059
5.82k
  case ISD::SIGN_EXTEND:
3060
5.82k
  case ISD::ANY_EXTEND: {
3061
5.82k
    SDValue X = LHS->getOperand(0);
3062
5.82k
3063
5.82k
    if (VT == MVT::i32 && 
RHSVal == 16699
&&
X.getValueType() == MVT::i16687
&&
3064
5.82k
        
isOperationLegal(ISD::BUILD_VECTOR, MVT::v2i16)687
) {
3065
37
      // Prefer build_vector as the canonical form if packed types are legal.
3066
37
      // (shl ([asz]ext i16:x), 16 -> build_vector 0, x
3067
37
      SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL,
3068
37
       { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) });
3069
37
      return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);
3070
37
    }
3071
5.78k
3072
5.78k
    // shl (ext x) => zext (shl x), if shift does not overflow int
3073
5.78k
    if (VT != MVT::i64)
3074
728
      break;
3075
5.06k
    KnownBits Known = DAG.computeKnownBits(X);
3076
5.06k
    unsigned LZ = Known.countMinLeadingZeros();
3077
5.06k
    if (LZ < RHSVal)
3078
1.88k
      break;
3079
3.17k
    EVT XVT = X.getValueType();
3080
3.17k
    SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));
3081
3.17k
    return DAG.getZExtOrTrunc(Shl, SL, VT);
3082
3.17k
  }
3083
14.3k
  }
3084
14.3k
3085
14.3k
  if (VT != MVT::i64)
3086
11.6k
    return SDValue();
3087
2.71k
3088
2.71k
  // i64 (shl x, C) -> (build_pair 0, (shl x, C -32))
3089
2.71k
3090
2.71k
  // On some subtargets, 64-bit shift is a quarter rate instruction. In the
3091
2.71k
  // common case, splitting this into a move and a 32-bit shift is faster and
3092
2.71k
  // the same code size.
3093
2.71k
  if (RHSVal < 32)
3094
1.33k
    return SDValue();
3095
1.38k
3096
1.38k
  SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32);
3097
1.38k
3098
1.38k
  SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
3099
1.38k
  SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);
3100
1.38k
3101
1.38k
  const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3102
1.38k
3103
1.38k
  SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift});
3104
1.38k
  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
3105
1.38k
}
3106
3107
SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
3108
6.71k
                                                DAGCombinerInfo &DCI) const {
3109
6.71k
  if (N->getValueType(0) != MVT::i64)
3110
6.07k
    return SDValue();
3111
637
3112
637
  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3113
637
  if (!RHS)
3114
34
    return SDValue();
3115
603
3116
603
  SelectionDAG &DAG = DCI.DAG;
3117
603
  SDLoc SL(N);
3118
603
  unsigned RHSVal = RHS->getZExtValue();
3119
603
3120
603
  // (sra i64:x, 32) -> build_pair x, (sra hi_32(x), 31)
3121
603
  if (RHSVal == 32) {
3122
6
    SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3123
6
    SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3124
6
                                   DAG.getConstant(31, SL, MVT::i32));
3125
6
3126
6
    SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift});
3127
6
    return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3128
6
  }
3129
597
3130
597
  // (sra i64:x, 63) -> build_pair (sra hi_32(x), 31), (sra hi_32(x), 31)
3131
597
  if (RHSVal == 63) {
3132
132
    SDValue Hi = getHiHalf64(N->getOperand(0), DAG);
3133
132
    SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,
3134
132
                                   DAG.getConstant(31, SL, MVT::i32));
3135
132
    SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift});
3136
132
    return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);
3137
132
  }
3138
465
3139
465
  return SDValue();
3140
465
}
3141
3142
SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3143
63.9k
                                                DAGCombinerInfo &DCI) const {
3144
63.9k
  auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3145
63.9k
  if (!RHS)
3146
4.77k
    return SDValue();
3147
59.1k
3148
59.1k
  EVT VT = N->getValueType(0);
3149
59.1k
  SDValue LHS = N->getOperand(0);
3150
59.1k
  unsigned ShiftAmt = RHS->getZExtValue();
3151
59.1k
  SelectionDAG &DAG = DCI.DAG;
3152
59.1k
  SDLoc SL(N);
3153
59.1k
3154
59.1k
  // fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
3155
59.1k
  // this improves the ability to match BFE patterns in isel.
3156
59.1k
  if (LHS.getOpcode() == ISD::AND) {
3157
3.28k
    if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
3158
3.28k
      if (Mask->getAPIntValue().isShiftedMask() &&
3159
3.28k
          
Mask->getAPIntValue().countTrailingZeros() == ShiftAmt3.22k
) {
3160
556
        return DAG.getNode(
3161
556
            ISD::AND, SL, VT,
3162
556
            DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
3163
556
            DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
3164
556
      }
3165
58.6k
    }
3166
3.28k
  }
3167
58.6k
3168
58.6k
  if (VT != MVT::i64)
3169
48.9k
    return SDValue();
3170
9.71k
3171
9.71k
  if (ShiftAmt < 32)
3172
227
    return SDValue();
3173
9.48k
3174
9.48k
  // srl i64:x, C for C >= 32
3175
9.48k
  // =>
3176
9.48k
  //   build_pair (srl hi_32(x), C - 32), 0
3177
9.48k
  SDValue One = DAG.getConstant(1, SL, MVT::i32);
3178
9.48k
  SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
3179
9.48k
3180
9.48k
  SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);
3181
9.48k
  SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);
3182
9.48k
3183
9.48k
  SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
3184
9.48k
  SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
3185
9.48k
3186
9.48k
  SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero});
3187
9.48k
3188
9.48k
  return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);
3189
9.48k
}
3190
3191
SDValue AMDGPUTargetLowering::performTruncateCombine(
3192
59.4k
  SDNode *N, DAGCombinerInfo &DCI) const {
3193
59.4k
  SDLoc SL(N);
3194
59.4k
  SelectionDAG &DAG = DCI.DAG;
3195
59.4k
  EVT VT = N->getValueType(0);
3196
59.4k
  SDValue Src = N->getOperand(0);
3197
59.4k
3198
59.4k
  // vt1 (truncate (bitcast (build_vector vt0:x, ...))) -> vt1 (bitcast vt0:x)
3199
59.4k
  if (Src.getOpcode() == ISD::BITCAST && 
!VT.isVector()6.40k
) {
3200
6.39k
    SDValue Vec = Src.getOperand(0);
3201
6.39k
    if (Vec.getOpcode() == ISD::BUILD_VECTOR) {
3202
2.07k
      SDValue Elt0 = Vec.getOperand(0);
3203
2.07k
      EVT EltVT = Elt0.getValueType();
3204
2.07k
      if (VT.getSizeInBits() <= EltVT.getSizeInBits()) {
3205
1.95k
        if (EltVT.isFloatingPoint()) {
3206
13
          Elt0 = DAG.getNode(ISD::BITCAST, SL,
3207
13
                             EltVT.changeTypeToInteger(), Elt0);
3208
13
        }
3209
1.95k
3210
1.95k
        return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);
3211
1.95k
      }
3212
57.5k
    }
3213
6.39k
  }
3214
57.5k
3215
57.5k
  // Equivalent of above for accessing the high element of a vector as an
3216
57.5k
  // integer operation.
3217
57.5k
  // trunc (srl (bitcast (build_vector x, y))), 16 -> trunc (bitcast y)
3218
57.5k
  if (Src.getOpcode() == ISD::SRL && 
!VT.isVector()28.8k
) {
3219
28.8k
    if (auto K = isConstOrConstSplat(Src.getOperand(1))) {
3220
28.7k
      if (2 * K->getZExtValue() == Src.getValueType().getScalarSizeInBits()) {
3221
21.2k
        SDValue BV = stripBitcast(Src.getOperand(0));
3222
21.2k
        if (BV.getOpcode() == ISD::BUILD_VECTOR &&
3223
21.2k
            
BV.getValueType().getVectorNumElements() == 21.47k
) {
3224
1.34k
          SDValue SrcElt = BV.getOperand(1);
3225
1.34k
          EVT SrcEltVT = SrcElt.getValueType();
3226
1.34k
          if (SrcEltVT.isFloatingPoint()) {
3227
6
            SrcElt = DAG.getNode(ISD::BITCAST, SL,
3228
6
                                 SrcEltVT.changeTypeToInteger(), SrcElt);
3229
6
          }
3230
1.34k
3231
1.34k
          return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);
3232
1.34k
        }
3233
56.1k
      }
3234
28.7k
    }
3235
28.8k
  }
3236
56.1k
3237
56.1k
  // Partially shrink 64-bit shifts to 32-bit if reduced to 16-bit.
3238
56.1k
  //
3239
56.1k
  // i16 (trunc (srl i64:x, K)), K <= 16 ->
3240
56.1k
  //     i16 (trunc (srl (i32 (trunc x), K)))
3241
56.1k
  if (VT.getScalarSizeInBits() < 32) {
3242
18.7k
    EVT SrcVT = Src.getValueType();
3243
18.7k
    if (SrcVT.getScalarSizeInBits() > 32 &&
3244
18.7k
        
(4.64k
Src.getOpcode() == ISD::SRL4.64k
||
3245
4.64k
         
Src.getOpcode() == ISD::SRA1.57k
||
3246
4.64k
         
Src.getOpcode() == ISD::SHL1.52k
)) {
3247
3.12k
      SDValue Amt = Src.getOperand(1);
3248
3.12k
      KnownBits Known = DAG.computeKnownBits(Amt);
3249
3.12k
      unsigned Size = VT.getScalarSizeInBits();
3250
3.12k
      if ((Known.isConstant() && 
Known.getConstant().ule(Size)3.09k
) ||
3251
3.12k
          
(Known.getBitWidth() - Known.countMinLeadingZeros() <= Log2_32(Size))2.44k
) {
3252
681
        EVT MidVT = VT.isVector() ?
3253
1
          EVT::getVectorVT(*DAG.getContext(), MVT::i32,
3254
680
                           VT.getVectorNumElements()) : MVT::i32;
3255
681
3256
681
        EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout());
3257
681
        SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,
3258
681
                                    Src.getOperand(0));
3259
681
        DCI.AddToWorklist(Trunc.getNode());
3260
681
3261
681
        if (Amt.getValueType() != NewShiftVT) {
3262
1
          Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT);
3263
1
          DCI.AddToWorklist(Amt.getNode());
3264
1
        }
3265
681
3266
681
        SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,
3267
681
                                          Trunc, Amt);
3268
681
        return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);
3269
681
      }
3270
55.4k
    }
3271
18.7k
  }
3272
55.4k
3273
55.4k
  return SDValue();
3274
55.4k
}
3275
3276
// We need to specifically handle i64 mul here to avoid unnecessary conversion
3277
// instructions. If we only match on the legalized i64 mul expansion,
3278
// SimplifyDemandedBits will be unable to remove them because there will be
3279
// multiple uses due to the separate mul + mulh[su].
3280
static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL,
3281
1.84k
                        SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3282
1.84k
  if (Size <= 32) {
3283
1.79k
    unsigned MulOpc = Signed ? 
AMDGPUISD::MUL_I24428
:
AMDGPUISD::MUL_U241.36k
;
3284
1.79k
    return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);
3285
1.79k
  }
3286
54
3287
54
  // Because we want to eliminate extension instructions before the
3288
54
  // operation, we need to create a single user here (i.e. not the separate
3289
54
  // mul_lo + mul_hi) so that SimplifyDemandedBits will deal with it.
3290
54
3291
54
  unsigned MulOpc = Signed ? 
AMDGPUISD::MUL_LOHI_I2415
:
AMDGPUISD::MUL_LOHI_U2439
;
3292
54
3293
54
  SDValue Mul = DAG.getNode(MulOpc, SL,
3294
54
                            DAG.getVTList(MVT::i32, MVT::i32), N0, N1);
3295
54
3296
54
  return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,
3297
54
                     Mul.getValue(0), Mul.getValue(1));
3298
54
}
3299
3300
SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3301
9.62k
                                                DAGCombinerInfo &DCI) const {
3302
9.62k
  EVT VT = N->getValueType(0);
3303
9.62k
3304
9.62k
  unsigned Size = VT.getSizeInBits();
3305
9.62k
  if (VT.isVector() || 
Size > 649.10k
)
3306
544
    return SDValue();
3307
9.07k
3308
9.07k
  // There are i16 integer mul/mad.
3309
9.07k
  if (Subtarget->has16BitInsts() && 
VT.getScalarType().bitsLE(MVT::i16)5.53k
)
3310
435
    return SDValue();
3311
8.64k
3312
8.64k
  SelectionDAG &DAG = DCI.DAG;
3313
8.64k
  SDLoc DL(N);
3314
8.64k
3315
8.64k
  SDValue N0 = N->getOperand(0);
3316
8.64k
  SDValue N1 = N->getOperand(1);
3317
8.64k
3318
8.64k
  // SimplifyDemandedBits has the annoying habit of turning useful zero_extends
3319
8.64k
  // in the source into any_extends if the result of the mul is truncated. Since
3320
8.64k
  // we can assume the high bits are whatever we want, use the underlying value
3321
8.64k
  // to avoid the unknown high bits from interfering.
3322
8.64k
  if (N0.getOpcode() == ISD::ANY_EXTEND)
3323
195
    N0 = N0.getOperand(0);
3324
8.64k
3325
8.64k
  if (N1.getOpcode() == ISD::ANY_EXTEND)
3326
187
    N1 = N1.getOperand(0);
3327
8.64k
3328
8.64k
  SDValue Mul;
3329
8.64k
3330
8.64k
  if (Subtarget->hasMulU24() && isU24(N0, DAG) && 
isU24(N1, DAG)1.49k
) {
3331
1.40k
    N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3332
1.40k
    N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3333
1.40k
    Mul = getMul24(DAG, DL, N0, N1, Size, false);
3334
7.23k
  } else if (Subtarget->hasMulI24() && 
isI24(N0, DAG)6.84k
&&
isI24(N1, DAG)528
) {
3335
443
    N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3336
443
    N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3337
443
    Mul = getMul24(DAG, DL, N0, N1, Size, true);
3338
6.79k
  } else {
3339
6.79k
    return SDValue();
3340
6.79k
  }
3341
1.84k
3342
1.84k
  // We need to use sext even for MUL_U24, because MUL_U24 is used
3343
1.84k
  // for signed multiply of 8 and 16-bit types.
3344
1.84k
  return DAG.getSExtOrTrunc(Mul, DL, VT);
3345
1.84k
}
3346
3347
SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3348
117
                                                  DAGCombinerInfo &DCI) const {
3349
117
  EVT VT = N->getValueType(0);
3350
117
3351
117
  if (!Subtarget->hasMulI24() || 
VT.isVector()87
)
3352
30
    return SDValue();
3353
87
3354
87
  SelectionDAG &DAG = DCI.DAG;
3355
87
  SDLoc DL(N);
3356
87
3357
87
  SDValue N0 = N->getOperand(0);
3358
87
  SDValue N1 = N->getOperand(1);
3359
87
3360
87
  if (!isI24(N0, DAG) || 
!isI24(N1, DAG)5
)
3361
87
    return SDValue();
3362
0
3363
0
  N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
3364
0
  N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
3365
0
3366
0
  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);
3367
0
  DCI.AddToWorklist(Mulhi.getNode());
3368
0
  return DAG.getSExtOrTrunc(Mulhi, DL, VT);
3369
0
}
3370
3371
SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3372
4.51k
                                                  DAGCombinerInfo &DCI) const {
3373
4.51k
  EVT VT = N->getValueType(0);
3374
4.51k
3375
4.51k
  if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32)
3376
0
    return SDValue();
3377
4.51k
3378
4.51k
  SelectionDAG &DAG = DCI.DAG;
3379
4.51k
  SDLoc DL(N);
3380
4.51k
3381
4.51k
  SDValue N0 = N->getOperand(0);
3382
4.51k
  SDValue N1 = N->getOperand(1);
3383
4.51k
3384
4.51k
  if (!isU24(N0, DAG) || 
!isU24(N1, DAG)0
)
3385
4.51k
    return SDValue();
3386
0
3387
0
  N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
3388
0
  N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
3389
0
3390
0
  SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);
3391
0
  DCI.AddToWorklist(Mulhi.getNode());
3392
0
  return DAG.getZExtOrTrunc(Mulhi, DL, VT);
3393
0
}
3394
3395
SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
3396
128
  SDNode *N, DAGCombinerInfo &DCI) const {
3397
128
  SelectionDAG &DAG = DCI.DAG;
3398
128
3399
128
  // Simplify demanded bits before splitting into multiple users.
3400
128
  if (SDValue V = simplifyI24(N, DCI))
3401
74
    return V;
3402
54
3403
54
  SDValue N0 = N->getOperand(0);
3404
54
  SDValue N1 = N->getOperand(1);
3405
54
3406
54
  bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
3407
54
3408
54
  unsigned MulLoOpc = Signed ? 
AMDGPUISD::MUL_I2415
:
AMDGPUISD::MUL_U2439
;
3409
54
  unsigned MulHiOpc = Signed ? 
AMDGPUISD::MULHI_I2415
:
AMDGPUISD::MULHI_U2439
;
3410
54
3411
54
  SDLoc SL(N);
3412
54
3413
54
  SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
3414
54
  SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);
3415
54
  return DAG.getMergeValues({ MulLo, MulHi }, SL);
3416
54
}
3417
3418
25
static bool isNegativeOne(SDValue Val) {
3419
25
  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
3420
25
    return C->isAllOnesValue();
3421
0
  return false;
3422
0
}
3423
3424
SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3425
                                          SDValue Op,
3426
                                          const SDLoc &DL,
3427
21
                                          unsigned Opc) const {
3428
21
  EVT VT = Op.getValueType();
3429
21
  EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT);
3430
21
  if (LegalVT != MVT::i32 && 
(3
Subtarget->has16BitInsts()3
&&
3431
3
                              LegalVT != MVT::i16))
3432
0
    return SDValue();
3433
21
3434
21
  if (VT != MVT::i32)
3435
11
    Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
3436
21
3437
21
  SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);
3438
21
  if (VT != MVT::i32)
3439
11
    FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);
3440
21
3441
21
  return FFBX;
3442
21
}
3443
3444
// The native instructions return -1 on 0 input. Optimize out a select that
3445
// produces -1 on 0.
3446
//
3447
// TODO: If zero is not undef, we could also do this if the output is compared
3448
// against the bitwidth.
3449
//
3450
// TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
3451
SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3452
                                                 SDValue LHS, SDValue RHS,
3453
11.5k
                                                 DAGCombinerInfo &DCI) const {
3454
11.5k
  ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3455
11.5k
  if (!CmpRhs || 
!CmpRhs->isNullValue()7.63k
)
3456
6.70k
    return SDValue();
3457
4.84k
3458
4.84k
  SelectionDAG &DAG = DCI.DAG;
3459
4.84k
  ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
3460
4.84k
  SDValue CmpLHS = Cond.getOperand(0);
3461
4.84k
3462
4.84k
  unsigned Opc = isCttzOpc(RHS.getOpcode()) ? 
AMDGPUISD::FFBL_B320
:
3463
4.84k
                                           AMDGPUISD::FFBH_U32;
3464
4.84k
3465
4.84k
  // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
3466
4.84k
  // select (setcc x, 0, eq), -1, (cttz_zero_undef x) -> ffbl_u32 x
3467
4.84k
  if (CCOpcode == ISD::SETEQ &&
3468
4.84k
      
(2.57k
isCtlzOpc(RHS.getOpcode())2.57k
||
isCttzOpc(RHS.getOpcode())2.56k
) &&
3469
4.84k
      
RHS.getOperand(0) == CmpLHS2
&&
3470
4.84k
      
isNegativeOne(LHS)2
) {
3471
2
    return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3472
2
  }
3473
4.84k
3474
4.84k
  // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
3475
4.84k
  // select (setcc x, 0, ne), (cttz_zero_undef x), -1 -> ffbl_u32 x
3476
4.84k
  if (CCOpcode == ISD::SETNE &&
3477
4.84k
      
(895
isCtlzOpc(LHS.getOpcode())895
||
isCttzOpc(RHS.getOpcode())872
) &&
3478
4.84k
      
LHS.getOperand(0) == CmpLHS23
&&
3479
4.84k
      
isNegativeOne(RHS)23
) {
3480
19
    return getFFBX_U32(DAG, CmpLHS, SL, Opc);
3481
19
  }
3482
4.82k
3483
4.82k
  return SDValue();
3484
4.82k
}
3485
3486
static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI,
3487
                                         unsigned Op,
3488
                                         const SDLoc &SL,
3489
                                         SDValue Cond,
3490
                                         SDValue N1,
3491
28
                                         SDValue N2) {
3492
28
  SelectionDAG &DAG = DCI.DAG;
3493
28
  EVT VT = N1.getValueType();
3494
28
3495
28
  SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,
3496
28
                                  N1.getOperand(0), N2.getOperand(0));
3497
28
  DCI.AddToWorklist(NewSelect.getNode());
3498
28
  return DAG.getNode(Op, SL, VT, NewSelect);
3499
28
}
3500
3501
// Pull a free FP operation out of a select so it may fold into uses.
3502
//
3503
// select c, (fneg x), (fneg y) -> fneg (select c, x, y)
3504
// select c, (fneg x), k -> fneg (select c, x, (fneg k))
3505
//
3506
// select c, (fabs x), (fabs y) -> fabs (select c, x, y)
3507
// select c, (fabs x), +k -> fabs (select c, x, k)
3508
static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
3509
14.5k
                                    SDValue N) {
3510
14.5k
  SelectionDAG &DAG = DCI.DAG;
3511
14.5k
  SDValue Cond = N.getOperand(0);
3512
14.5k
  SDValue LHS = N.getOperand(1);
3513
14.5k
  SDValue RHS = N.getOperand(2);
3514
14.5k
3515
14.5k
  EVT VT = N.getValueType();
3516
14.5k
  if ((LHS.getOpcode() == ISD::FABS && 
RHS.getOpcode() == ISD::FABS69
) ||
3517
14.5k
      
(14.5k
LHS.getOpcode() == ISD::FNEG14.5k
&&
RHS.getOpcode() == ISD::FNEG145
)) {
3518
28
    return distributeOpThroughSelect(DCI, LHS.getOpcode(),
3519
28
                                     SDLoc(N), Cond, LHS, RHS);
3520
28
  }
3521
14.5k
3522
14.5k
  bool Inv = false;
3523
14.5k
  if (RHS.getOpcode() == ISD::FABS || 
RHS.getOpcode() == ISD::FNEG14.5k
) {
3524
65
    std::swap(LHS, RHS);
3525
65
    Inv = true;
3526
65
  }
3527
14.5k
3528
14.5k
  // TODO: Support vector constants.
3529
14.5k
  ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
3530
14.5k
  if ((LHS.getOpcode() == ISD::FNEG || 
LHS.getOpcode() == ISD::FABS14.3k
) &&
CRHS220
) {
3531
87
    SDLoc SL(N);
3532
87
    // If one side is an fneg/fabs and the other is a constant, we can push the
3533
87
    // fneg/fabs down. If it's an fabs, the constant needs to be non-negative.
3534
87
    SDValue NewLHS = LHS.getOperand(0);
3535
87
    SDValue NewRHS = RHS;
3536
87
3537
87
    // Careful: if the neg can be folded up, don't try to pull it back down.
3538
87
    bool ShouldFoldNeg = true;
3539
87
3540
87
    if (NewLHS.hasOneUse()) {
3541
70
      unsigned Opc = NewLHS.getOpcode();
3542
70
      if (LHS.getOpcode() == ISD::FNEG && 
fnegFoldsIntoOp(Opc)36
)
3543
12
        ShouldFoldNeg = false;
3544
70
      if (LHS.getOpcode() == ISD::FABS && 
Opc == ISD::FMUL34
)
3545
0
        ShouldFoldNeg = false;
3546
70
    }
3547
87
3548
87
    if (ShouldFoldNeg) {
3549
75
      if (LHS.getOpcode() == ISD::FNEG)
3550
41
        NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3551
34
      else if (CRHS->isNegative())
3552
26
        return SDValue();
3553
49
3554
49
      if (Inv)
3555
12
        std::swap(NewLHS, NewRHS);
3556
49
3557
49
      SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,
3558
49
                                      Cond, NewLHS, NewRHS);
3559
49
      DCI.AddToWorklist(NewSelect.getNode());
3560
49
      return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);
3561
49
    }
3562
87
  }
3563
14.4k
3564
14.4k
  return SDValue();
3565
14.4k
}
3566
3567
3568
SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3569
14.5k
                                                   DAGCombinerInfo &DCI) const {
3570
14.5k
  if (SDValue Folded = foldFreeOpFromSelect(DCI, SDValue(N, 0)))
3571
77
    return Folded;
3572
14.4k
3573
14.4k
  SDValue Cond = N->getOperand(0);
3574
14.4k
  if (Cond.getOpcode() != ISD::SETCC)
3575
1.73k
    return SDValue();
3576
12.7k
3577
12.7k
  EVT VT = N->getValueType(0);
3578
12.7k
  SDValue LHS = Cond.getOperand(0);
3579
12.7k
  SDValue RHS = Cond.getOperand(1);
3580
12.7k
  SDValue CC = Cond.getOperand(2);
3581
12.7k
3582
12.7k
  SDValue True = N->getOperand(1);
3583
12.7k
  SDValue False = N->getOperand(2);
3584
12.7k
3585
12.7k
  if (Cond.hasOneUse()) { // TODO: Look for multiple select uses.
3586
5.96k
    SelectionDAG &DAG = DCI.DAG;
3587
5.96k
    if (DAG.isConstantValueOfAnyType(True) &&
3588
5.96k
        
!DAG.isConstantValueOfAnyType(False)1.89k
) {
3589
751
      // Swap cmp + select pair to move constant to false input.
3590
751
      // This will allow using VOPC cndmasks more often.
3591
751
      // select (setcc x, y), k, x -> select (setccinv x, y), x, k
3592
751
3593
751
      SDLoc SL(N);
3594
751
      ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3595
751
                                            LHS.getValueType().isInteger());
3596
751
3597
751
      SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
3598
751
      return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3599
751
    }
3600
5.21k
3601
5.21k
    if (VT == MVT::f32 && 
Subtarget->hasFminFmaxLegacy()990
) {
3602
443
      SDValue MinMax
3603
443
        = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3604
443
      // Revisit this node so we can catch min3/max3/med3 patterns.
3605
443
      //DCI.AddToWorklist(MinMax.getNode());
3606
443
      return MinMax;
3607
443
    }
3608
11.5k
  }
3609
11.5k
3610
11.5k
  // There's no reason to not do this if the condition has other uses.
3611
11.5k
  return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
3612
11.5k
}
3613
3614
50
static bool isInv2Pi(const APFloat &APF) {
3615
50
  static const APFloat KF16(APFloat::IEEEhalf(), APInt(16, 0x3118));
3616
50
  static const APFloat KF32(APFloat::IEEEsingle(), APInt(32, 0x3e22f983));
3617
50
  static const APFloat KF64(APFloat::IEEEdouble(), APInt(64, 0x3fc45f306dc9c882));
3618
50
3619
50
  return APF.bitwiseIsEqual(KF16) ||
3620
50
         
APF.bitwiseIsEqual(KF32)46
||
3621
50
         
APF.bitwiseIsEqual(KF64)38
;
3622
50
}
3623
3624
// 0 and 1.0 / (0.5 * pi) do not have inline immmediates, so there is an
3625
// additional cost to negate them.
3626
206
bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
3627
206
  if (const ConstantFPSDNode *C = isConstOrConstSplatFP(N)) {
3628
154
    if (C->isZero() && 
!C->isNegative()65
)
3629
49
      return true;
3630
105
3631
105
    if (Subtarget->hasInv2PiInlineImm() && 
isInv2Pi(C->getValueAPF())50
)
3632
16
      return true;
3633
141
  }
3634
141
3635
141
  return false;
3636
141
}
3637
3638
141
static unsigned inverseMinMax(unsigned Opc) {
3639
141
  switch (Opc) {
3640
141
  case ISD::FMAXNUM:
3641
54
    return ISD::FMINNUM;
3642
141
  case ISD::FMINNUM:
3643
75
    return ISD::FMAXNUM;
3644
141
  case ISD::FMAXNUM_IEEE:
3645
4
    return ISD::FMINNUM_IEEE;
3646
141
  case ISD::FMINNUM_IEEE:
3647
4
    return ISD::FMAXNUM_IEEE;
3648
141
  case AMDGPUISD::FMAX_LEGACY:
3649
2
    return AMDGPUISD::FMIN_LEGACY;
3650
141
  case AMDGPUISD::FMIN_LEGACY:
3651
2
    return  AMDGPUISD::FMAX_LEGACY;
3652
141
  default:
3653
0
    llvm_unreachable("invalid min/max opcode");
3654
141
  }
3655
141
}
3656
3657
SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3658
4.22k
                                                 DAGCombinerInfo &DCI) const {
3659
4.22k
  SelectionDAG &DAG = DCI.DAG;
3660
4.22k
  SDValue N0 = N->getOperand(0);
3661
4.22k
  EVT VT = N->getValueType(0);
3662
4.22k
3663
4.22k
  unsigned Opc = N0.getOpcode();
3664
4.22k
3665
4.22k
  // If the input has multiple uses and we can either fold the negate down, or
3666
4.22k
  // the other uses cannot, give up. This both prevents unprofitable
3667
4.22k
  // transformations and infinite loops: we won't repeatedly try to fold around
3668
4.22k
  // a negate that has no 'good' form.
3669
4.22k
  if (N0.hasOneUse()) {
3670
3.23k
    // This may be able to fold into the source, but at a code size cost. Don't
3671
3.23k
    // fold if the fold into the user is free.
3672
3.23k
    if (allUsesHaveSourceMods(N, 0))
3673
1.10k
      return SDValue();
3674
988
  } else {
3675
988
    if (fnegFoldsIntoOp(Opc) &&
3676
988
        
(363
allUsesHaveSourceMods(N)363
||
!allUsesHaveSourceMods(N0.getNode())105
))
3677
302
      return SDValue();
3678
2.81k
  }
3679
2.81k
3680
2.81k
  SDLoc SL(N);
3681
2.81k
  switch (Opc) {
3682
2.81k
  case ISD::FADD: {
3683
126
    if (!mayIgnoreSignedZero(N0))
3684
98
      return SDValue();
3685
28
3686
28
    // (fneg (fadd x, y)) -> (fadd (fneg x), (fneg y))
3687
28
    SDValue LHS = N0.getOperand(0);
3688
28
    SDValue RHS = N0.getOperand(1);
3689
28
3690
28
    if (LHS.getOpcode() != ISD::FNEG)
3691
20
      LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3692
8
    else
3693
8
      LHS = LHS.getOperand(0);
3694
28
3695
28
    if (RHS.getOpcode() != ISD::FNEG)
3696
24
      RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3697
4
    else
3698
4
      RHS = RHS.getOperand(0);
3699
28
3700
28
    SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3701
28
    if (Res.getOpcode() != ISD::FADD)
3702
4
      return SDValue(); // Op got folded away.
3703
24
    if (!N0.hasOneUse())
3704
4
      DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3705
24
    return Res;
3706
24
  }
3707
88
  case ISD::FMUL:
3708
88
  case AMDGPUISD::FMUL_LEGACY: {
3709
88
    // (fneg (fmul x, y)) -> (fmul x, (fneg y))
3710
88
    // (fneg (fmul_legacy x, y)) -> (fmul_legacy x, (fneg y))
3711
88
    SDValue LHS = N0.getOperand(0);
3712
88
    SDValue RHS = N0.getOperand(1);
3713
88
3714
88
    if (LHS.getOpcode() == ISD::FNEG)
3715
16
      LHS = LHS.getOperand(0);
3716
72
    else if (RHS.getOpcode() == ISD::FNEG)
3717
4
      RHS = RHS.getOperand(0);
3718
68
    else
3719
68
      RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3720
88
3721
88
    SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3722
88
    if (Res.getOpcode() != Opc)
3723
0
      return SDValue(); // Op got folded away.
3724
88
    if (!N0.hasOneUse())
3725
9
      DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3726
88
    return Res;
3727
88
  }
3728
88
  case ISD::FMA:
3729
83
  case ISD::FMAD: {
3730
83
    if (!mayIgnoreSignedZero(N0))
3731
59
      return SDValue();
3732
24
3733
24
    // (fneg (fma x, y, z)) -> (fma x, (fneg y), (fneg z))
3734
24
    SDValue LHS = N0.getOperand(0);
3735
24
    SDValue MHS = N0.getOperand(1);
3736
24
    SDValue RHS = N0.getOperand(2);
3737
24
3738
24
    if (LHS.getOpcode() == ISD::FNEG)
3739
10
      LHS = LHS.getOperand(0);
3740
14
    else if (MHS.getOpcode() == ISD::FNEG)
3741
2
      MHS = MHS.getOperand(0);
3742
12
    else
3743
12
      MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);
3744
24
3745
24
    if (RHS.getOpcode() != ISD::FNEG)
3746
20
      RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3747
4
    else
3748
4
      RHS = RHS.getOperand(0);
3749
24
3750
24
    SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);
3751
24
    if (Res.getOpcode() != Opc)
3752
0
      return SDValue(); // Op got folded away.
3753
24
    if (!N0.hasOneUse())
3754
4
      DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3755
24
    return Res;
3756
24
  }
3757
206
  case ISD::FMAXNUM:
3758
206
  case ISD::FMINNUM:
3759
206
  case ISD::FMAXNUM_IEEE:
3760
206
  case ISD::FMINNUM_IEEE:
3761
206
  case AMDGPUISD::FMAX_LEGACY:
3762
206
  case AMDGPUISD::FMIN_LEGACY: {
3763
206
    // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y)
3764
206
    // fneg (fminnum x, y) -> fmaxnum (fneg x), (fneg y)
3765
206
    // fneg (fmax_legacy x, y) -> fmin_legacy (fneg x), (fneg y)
3766
206
    // fneg (fmin_legacy x, y) -> fmax_legacy (fneg x), (fneg y)
3767
206
3768
206
    SDValue LHS = N0.getOperand(0);
3769
206
    SDValue RHS = N0.getOperand(1);
3770
206
3771
206
    // 0 doesn't have a negated inline immediate.
3772
206
    // TODO: This constant check should be generalized to other operations.
3773
206
    if (isConstantCostlierToNegate(RHS))
3774
65
      return SDValue();
3775
141
3776
141
    SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);
3777
141
    SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
3778
141
    unsigned Opposite = inverseMinMax(Opc);
3779
141
3780
141
    SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3781
141
    if (Res.getOpcode() != Opposite)
3782
0
      return SDValue(); // Op got folded away.
3783
141
    if (!N0.hasOneUse())
3784
16
      DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3785
141
    return Res;
3786
141
  }
3787
141
  case AMDGPUISD::FMED3: {
3788
12
    SDValue Ops[3];
3789
48
    for (unsigned I = 0; I < 3; 
++I36
)
3790
36
      Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3791
12
3792
12
    SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3793
12
    if (Res.getOpcode() != AMDGPUISD::FMED3)
3794
0
      return SDValue(); // Op got folded away.
3795
12
    if (!N0.hasOneUse())
3796
2
      DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
3797
12
    return Res;
3798
12
  }
3799
96
  case ISD::FP_EXTEND:
3800
96
  case ISD::FTRUNC:
3801
96
  case ISD::FRINT:
3802
96
  case ISD::FNEARBYINT: // XXX - Should fround be handled?
3803
96
  case ISD::FSIN:
3804
96
  case ISD::FCANONICALIZE:
3805
96
  case AMDGPUISD::RCP:
3806
96
  case AMDGPUISD::RCP_LEGACY:
3807
96
  case AMDGPUISD::RCP_IFLAG:
3808
96
  case AMDGPUISD::SIN_HW: {
3809
96
    SDValue CvtSrc = N0.getOperand(0);
3810
96
    if (CvtSrc.getOpcode() == ISD::FNEG) {
3811
14
      // (fneg (fp_extend (fneg x))) -> (fp_extend x)
3812
14
      // (fneg (rcp (fneg x))) -> (rcp x)
3813
14
      return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
3814
14
    }
3815
82
3816
82
    if (!N0.hasOneUse())
3817
30
      return SDValue();
3818
52
3819
52
    // (fneg (fp_extend x)) -> (fp_extend (fneg x))
3820
52
    // (fneg (rcp x)) -> (rcp (fneg x))
3821
52
    SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3822
52
    return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3823
52
  }
3824
52
  case ISD::FP_ROUND: {
3825
16
    SDValue CvtSrc = N0.getOperand(0);
3826
16
3827
16
    if (CvtSrc.getOpcode() == ISD::FNEG) {
3828
0
      // (fneg (fp_round (fneg x))) -> (fp_round x)
3829
0
      return DAG.getNode(ISD::FP_ROUND, SL, VT,
3830
0
                         CvtSrc.getOperand(0), N0.getOperand(1));
3831
0
    }
3832
16
3833
16
    if (!N0.hasOneUse())
3834
8
      return SDValue();
3835
8
3836
8
    // (fneg (fp_round x)) -> (fp_round (fneg x))
3837
8
    SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3838
8
    return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
3839
8
  }
3840
29
  case ISD::FP16_TO_FP: {
3841
29
    // v_cvt_f32_f16 supports source modifiers on pre-VI targets without legal
3842
29
    // f16, but legalization of f16 fneg ends up pulling it out of the source.
3843
29
    // Put the fneg back as a legal source operation that can be matched later.
3844
29
    SDLoc SL(N);
3845
29
3846
29
    SDValue Src = N0.getOperand(0);
3847
29
    EVT SrcVT = Src.getValueType();
3848
29
3849
29
    // fneg (fp16_to_fp x) -> fp16_to_fp (xor x, 0x8000)
3850
29
    SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,
3851
29
                                  DAG.getConstant(0x8000, SL, SrcVT));
3852
29
    return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);
3853
8
  }
3854
2.15k
  default:
3855
2.15k
    return SDValue();
3856
2.81k
  }
3857
2.81k
}
3858
3859
SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3860
2.01k
                                                 DAGCombinerInfo &DCI) const {
3861
2.01k
  SelectionDAG &DAG = DCI.DAG;
3862
2.01k
  SDValue N0 = N->getOperand(0);
3863
2.01k
3864
2.01k
  if (!N0.hasOneUse())
3865
320
    return SDValue();
3866
1.69k
3867
1.69k
  switch (N0.getOpcode()) {
3868
1.69k
  case ISD::FP16_TO_FP: {
3869
19
    assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal");
3870
19
    SDLoc SL(N);
3871
19
    SDValue Src = N0.getOperand(0);
3872
19
    EVT SrcVT = Src.getValueType();
3873
19
3874
19
    // fabs (fp16_to_fp x) -> fp16_to_fp (and x, 0x7fff)
3875
19
    SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,
3876
19
                                  DAG.getConstant(0x7fff, SL, SrcVT));
3877
19
    return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);
3878
1.69k
  }
3879
1.69k
  default:
3880
1.67k
    return SDValue();
3881
1.69k
  }
3882
1.69k
}
3883
3884
SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
3885
1.10k
                                                DAGCombinerInfo &DCI) const {
3886
1.10k
  const auto *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3887
1.10k
  if (!CFP)
3888
1.10k
    return SDValue();
3889
2
3890
2
  // XXX - Should this flush denormals?
3891
2
  const APFloat &Val = CFP->getValueAPF();
3892
2
  APFloat One(Val.getSemantics(), "1.0");
3893
2
  return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
3894
2
}
3895
3896
SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
3897
1.01M
                                                DAGCombinerInfo &DCI) const {
3898
1.01M
  SelectionDAG &DAG = DCI.DAG;
3899
1.01M
  SDLoc DL(N);
3900
1.01M
3901
1.01M
  switch(N->getOpcode()) {
3902
1.01M
  default:
3903
185k
    break;
3904
1.01M
  case ISD::BITCAST: {
3905
127k
    EVT DestVT = N->getValueType(0);
3906
127k
3907
127k
    // Push casts through vector builds. This helps avoid emitting a large
3908
127k
    // number of copies when materializing floating point vector constants.
3909
127k
    //
3910
127k
    // vNt1 bitcast (vNt0 (build_vector t0:x, t0:y)) =>
3911
127k
    //   vnt1 = build_vector (t1 (bitcast t0:x)), (t1 (bitcast t0:y))
3912
127k
    if (DestVT.isVector()) {
3913
44.2k
      SDValue Src = N->getOperand(0);
3914
44.2k
      if (Src.getOpcode() == ISD::BUILD_VECTOR) {
3915
6.81k
        EVT SrcVT = Src.getValueType();
3916
6.81k
        unsigned NElts = DestVT.getVectorNumElements();
3917
6.81k
3918
6.81k
        if (SrcVT.getVectorNumElements() == NElts) {
3919
3.09k
          EVT DestEltVT = DestVT.getVectorElementType();
3920
3.09k
3921
3.09k
          SmallVector<SDValue, 8> CastedElts;
3922
3.09k
          SDLoc SL(N);
3923
20.1k
          for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; 
++I17.0k
) {
3924
17.0k
            SDValue Elt = Src.getOperand(I);
3925
17.0k
            CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));
3926
17.0k
          }
3927
3.09k
3928
3.09k
          return DAG.getBuildVector(DestVT, SL, CastedElts);
3929
3.09k
        }
3930
123k
      }
3931
44.2k
    }
3932
123k
3933
123k
    if (DestVT.getSizeInBits() != 64 && 
!DestVT.isVector()64.9k
)
3934
43.1k
      break;
3935
80.8k
3936
80.8k
    // Fold bitcasts of constants.
3937
80.8k
    //
3938
80.8k
    // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
3939
80.8k
    // TODO: Generalize and move to DAGCombiner
3940
80.8k
    SDValue Src = N->getOperand(0);
3941
80.8k
    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
3942
510
      if (Src.getValueType() == MVT::i64) {
3943
404
        SDLoc SL(N);
3944
404
        uint64_t CVal = C->getZExtValue();
3945
404
        SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3946
404
                                 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3947
404
                                 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3948
404
        return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
3949
404
      }
3950
80.4k
    }
3951
80.4k
3952
80.4k
    if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
3953
35
      const APInt &Val = C->getValueAPF().bitcastToAPInt();
3954
35
      SDLoc SL(N);
3955
35
      uint64_t CVal = Val.getZExtValue();
3956
35
      SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3957
35
                                DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
3958
35
                                DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
3959
35
3960
35
      return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);
3961
35
    }
3962
80.3k
3963
80.3k
    break;
3964
80.3k
  }
3965
80.3k
  case ISD::SHL: {
3966
35.1k
    if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3967
13.7k
      break;
3968
21.4k
3969
21.4k
    return performShlCombine(N, DCI);
3970
21.4k
  }
3971
102k
  case ISD::SRL: {
3972
102k
    if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3973
38.2k
      break;
3974
63.9k
3975
63.9k
    return performSrlCombine(N, DCI);
3976
63.9k
  }
3977
63.9k
  case ISD::SRA: {
3978
13.1k
    if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3979
6.44k
      break;
3980
6.71k
3981
6.71k
    return performSraCombine(N, DCI);
3982
6.71k
  }
3983
59.4k
  case ISD::TRUNCATE:
3984
59.4k
    return performTruncateCombine(N, DCI);
3985
9.62k
  case ISD::MUL:
3986
9.62k
    return performMulCombine(N, DCI);
3987
6.71k
  case ISD::MULHS:
3988
117
    return performMulhsCombine(N, DCI);
3989
6.71k
  case ISD::MULHU:
3990
4.51k
    return performMulhuCombine(N, DCI);
3991
8.25k
  case AMDGPUISD::MUL_I24:
3992
8.25k
  case AMDGPUISD::MUL_U24:
3993
8.25k
  case AMDGPUISD::MULHI_I24:
3994
8.25k
  case AMDGPUISD::MULHI_U24: {
3995
8.25k
    if (SDValue V = simplifyI24(N, DCI))
3996
735
      return V;
3997
7.52k
    return SDValue();
3998
7.52k
  }
3999
7.52k
  case AMDGPUISD::MUL_LOHI_I24:
4000
128
  case AMDGPUISD::MUL_LOHI_U24:
4001
128
    return performMulLoHi24Combine(N, DCI);
4002
14.5k
  case ISD::SELECT:
4003
14.5k
    return performSelectCombine(N, DCI);
4004
4.22k
  case ISD::FNEG:
4005
4.22k
    return performFNegCombine(N, DCI);
4006
2.01k
  case ISD::FABS:
4007
2.01k
    return performFAbsCombine(N, DCI);
4008
397
  case AMDGPUISD::BFE_I32:
4009
397
  case AMDGPUISD::BFE_U32: {
4010
397
    assert(!N->getValueType(0).isVector() &&
4011
397
           "Vector handling of BFE not implemented");
4012
397
    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
4013
397
    if (!Width)
4014
12
      break;
4015
385
4016
385
    uint32_t WidthVal = Width->getZExtValue() & 0x1f;
4017
385
    if (WidthVal == 0)
4018
22
      return DAG.getConstant(0, DL, MVT::i32);
4019
363
4020
363
    ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
4021
363
    if (!Offset)
4022
8
      break;
4023
355
4024
355
    SDValue BitsFrom = N->getOperand(0);
4025
355
    uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
4026
355
4027
355
    bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
4028
355
4029
355
    if (OffsetVal == 0) {
4030
58
      // This is already sign / zero extended, so try to fold away extra BFEs.
4031
58
      unsigned SignBits =  Signed ? 
(32 - WidthVal + 1)32
:
(32 - WidthVal)26
;
4032
58
4033
58
      unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
4034
58
      if (OpSignBits >= SignBits)
4035
34
        return BitsFrom;
4036
24
4037
24
      EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
4038
24
      if (Signed) {
4039
18
        // This is a sign_extend_inreg. Replace it to take advantage of existing
4040
18
        // DAG Combines. If not eliminated, we will match back to BFE during
4041
18
        // selection.
4042
18
4043
18
        // TODO: The sext_inreg of extended types ends, although we can could
4044
18
        // handle them in a single BFE.
4045
18
        return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
4046
18
                           DAG.getValueType(SmallVT));
4047
18
      }
4048
6
4049
6
      return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
4050
6
    }
4051
297
4052
297
    if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
4053
48
      if (Signed) {
4054
24
        return constantFoldBFE<int32_t>(DAG,
4055
24
                                        CVal->getSExtValue(),
4056
24
                                        OffsetVal,
4057
24
                                        WidthVal,
4058
24
                                        DL);
4059
24
      }
4060
24
4061
24
      return constantFoldBFE<uint32_t>(DAG,
4062
24
                                       CVal->getZExtValue(),
4063
24
                                       OffsetVal,
4064
24
                                       WidthVal,
4065
24
                                       DL);
4066
24
    }
4067
249
4068
249
    if ((OffsetVal + WidthVal) >= 32 &&
4069
249
        
!(99
Subtarget->hasSDWA()99
&&
OffsetVal == 1682
&&
WidthVal == 162
)) {
4070
97
      SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
4071
97
      return DAG.getNode(Signed ? 
ISD::SRA16
:
ISD::SRL81
, DL, MVT::i32,
4072
97
                         BitsFrom, ShiftVal);
4073
97
    }
4074
152
4075
152
    if (BitsFrom.hasOneUse()) {
4076
38
      APInt Demanded = APInt::getBitsSet(32,
4077
38
                                         OffsetVal,
4078
38
                                         OffsetVal + WidthVal);
4079
38
4080
38
      KnownBits Known;
4081
38
      TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
4082
38
                                            !DCI.isBeforeLegalizeOps());
4083
38
      const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4084
38
      if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) ||
4085
38
          
TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)30
) {
4086
14
        DCI.CommitTargetLoweringOpt(TLO);
4087
14
      }
4088
38
    }
4089
152
4090
152
    break;
4091
152
  }
4092
277k
  case ISD::LOAD:
4093
277k
    return performLoadCombine(N, DCI);
4094
157k
  case ISD::STORE:
4095
157k
    return performStoreCombine(N, DCI);
4096
511
  case AMDGPUISD::RCP:
4097
511
  case AMDGPUISD::RCP_IFLAG:
4098
511
    return performRcpCombine(N, DCI);
4099
13.2k
  case ISD::AssertZext:
4100
13.2k
  case ISD::AssertSext:
4101
13.2k
    return performAssertSZExtCombine(N, DCI);
4102
367k
  }
4103
367k
  return SDValue();
4104
367k
}
4105
4106
//===----------------------------------------------------------------------===//
4107
// Helper functions
4108
//===----------------------------------------------------------------------===//
4109
4110
SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4111
                                                   const TargetRegisterClass *RC,
4112
                                                   unsigned Reg, EVT VT,
4113
                                                   const SDLoc &SL,
4114
23.4k
                                                   bool RawReg) const {
4115
23.4k
  MachineFunction &MF = DAG.getMachineFunction();
4116
23.4k
  MachineRegisterInfo &MRI = MF.getRegInfo();
4117
23.4k
  unsigned VReg;
4118
23.4k
4119
23.4k
  if (!MRI.isLiveIn(Reg)) {
4120
2.50k
    VReg = MRI.createVirtualRegister(RC);
4121
2.50k
    MRI.addLiveIn(Reg, VReg);
4122
20.9k
  } else {
4123
20.9k
    VReg = MRI.getLiveInVirtReg(Reg);
4124
20.9k
  }
4125
23.4k
4126
23.4k
  if (RawReg)
4127
258
    return DAG.getRegister(VReg, VT);
4128
23.2k
4129
23.2k
  return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT);
4130
23.2k
}
4131
4132
SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
4133
                                                  EVT VT,
4134
                                                  const SDLoc &SL,
4135
6
                                                  int64_t Offset) const {
4136
6
  MachineFunction &MF = DAG.getMachineFunction();
4137
6
  MachineFrameInfo &MFI = MF.getFrameInfo();
4138
6
4139
6
  int FI = MFI.CreateFixedObject(VT.getStoreSize(), Offset, true);
4140
6
  auto SrcPtrInfo = MachinePointerInfo::getStack(MF, Offset);
4141
6
  SDValue Ptr = DAG.getFrameIndex(FI, MVT::i32);
4142
6
4143
6
  return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, 4,
4144
6
                     MachineMemOperand::MODereferenceable |
4145
6
                     MachineMemOperand::MOInvariant);
4146
6
}
4147
4148
SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
4149
                                                   const SDLoc &SL,
4150
                                                   SDValue Chain,
4151
                                                   SDValue ArgVal,
4152
6
                                                   int64_t Offset) const {
4153
6
  MachineFunction &MF = DAG.getMachineFunction();
4154
6
  MachinePointerInfo DstInfo = MachinePointerInfo::getStack(MF, Offset);
4155
6
4156
6
  SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32);
4157
6
  SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, 4,
4158
6
                               MachineMemOperand::MODereferenceable);
4159
6
  return Store;
4160
6
}
4161
4162
SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
4163
                                             const TargetRegisterClass *RC,
4164
                                             EVT VT, const SDLoc &SL,
4165
4.30k
                                             const ArgDescriptor &Arg) const {
4166
4.30k
  assert(Arg && "Attempting to load missing argument");
4167
4.30k
4168
4.30k
  SDValue V = Arg.isRegister() ?
4169
4.30k
    CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) :
4170
4.30k
    
loadStackInputValue(DAG, VT, SL, Arg.getStackOffset())6
;
4171
4.30k
4172
4.30k
  if (!Arg.isMasked())
4173
4.27k
    return V;
4174
37
4175
37
  unsigned Mask = Arg.getMask();
4176
37
  unsigned Shift = countTrailingZeros<unsigned>(Mask);
4177
37
  V = DAG.getNode(ISD::SRL, SL, VT, V,
4178
37
                  DAG.getShiftAmountConstant(Shift, VT, SL));
4179
37
  return DAG.getNode(ISD::AND, SL, VT, V,
4180
37
                     DAG.getConstant(Mask >> Shift, SL, VT));
4181
37
}
4182
4183
uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
4184
59
    const MachineFunction &MF, const ImplicitParameter Param) const {
4185
59
  const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
4186
59
  const AMDGPUSubtarget &ST =
4187
59
      AMDGPUSubtarget::get(getTargetMachine(), MF.getFunction());
4188
59
  unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction());
4189
59
  unsigned Alignment = ST.getAlignmentForImplicitArgPtr();
4190
59
  uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
4191
59
                       ExplicitArgOffset;
4192
59
  switch (Param) {
4193
59
  case GRID_DIM:
4194
59
    return ArgOffset;
4195
59
  case GRID_OFFSET:
4196
0
    return ArgOffset + 4;
4197
0
  }
4198
0
  llvm_unreachable("unexpected implicit parameter type");
4199
0
}
4200
4201
0
#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
4202
4203
0
const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4204
0
  switch ((AMDGPUISD::NodeType)Opcode) {
4205
0
  case AMDGPUISD::FIRST_NUMBER: break;
4206
0
  // AMDIL DAG nodes
4207
0
  NODE_NAME_CASE(UMUL);
4208
0
  NODE_NAME_CASE(BRANCH_COND);
4209
0
4210
0
  // AMDGPU DAG nodes
4211
0
  NODE_NAME_CASE(IF)
4212
0
  NODE_NAME_CASE(ELSE)
4213
0
  NODE_NAME_CASE(LOOP)
4214
0
  NODE_NAME_CASE(CALL)
4215
0
  NODE_NAME_CASE(TC_RETURN)
4216
0
  NODE_NAME_CASE(TRAP)
4217
0
  NODE_NAME_CASE(RET_FLAG)
4218
0
  NODE_NAME_CASE(RETURN_TO_EPILOG)
4219
0
  NODE_NAME_CASE(ENDPGM)
4220
0
  NODE_NAME_CASE(DWORDADDR)
4221
0
  NODE_NAME_CASE(FRACT)
4222
0
  NODE_NAME_CASE(SETCC)
4223
0
  NODE_NAME_CASE(SETREG)
4224
0
  NODE_NAME_CASE(FMA_W_CHAIN)
4225
0
  NODE_NAME_CASE(FMUL_W_CHAIN)
4226
0
  NODE_NAME_CASE(CLAMP)
4227
0
  NODE_NAME_CASE(COS_HW)
4228
0
  NODE_NAME_CASE(SIN_HW)
4229
0
  NODE_NAME_CASE(FMAX_LEGACY)
4230
0
  NODE_NAME_CASE(FMIN_LEGACY)
4231
0
  NODE_NAME_CASE(FMAX3)
4232
0
  NODE_NAME_CASE(SMAX3)
4233
0
  NODE_NAME_CASE(UMAX3)
4234
0
  NODE_NAME_CASE(FMIN3)
4235
0
  NODE_NAME_CASE(SMIN3)
4236
0
  NODE_NAME_CASE(UMIN3)
4237
0
  NODE_NAME_CASE(FMED3)
4238
0
  NODE_NAME_CASE(SMED3)
4239
0
  NODE_NAME_CASE(UMED3)
4240
0
  NODE_NAME_CASE(FDOT2)
4241
0
  NODE_NAME_CASE(URECIP)
4242
0
  NODE_NAME_CASE(DIV_SCALE)
4243
0
  NODE_NAME_CASE(DIV_FMAS)
4244
0
  NODE_NAME_CASE(DIV_FIXUP)
4245
0
  NODE_NAME_CASE(FMAD_FTZ)
4246
0
  NODE_NAME_CASE(TRIG_PREOP)
4247
0
  NODE_NAME_CASE(RCP)
4248
0
  NODE_NAME_CASE(RSQ)
4249
0
  NODE_NAME_CASE(RCP_LEGACY)
4250
0
  NODE_NAME_CASE(RSQ_LEGACY)
4251
0
  NODE_NAME_CASE(RCP_IFLAG)
4252
0
  NODE_NAME_CASE(FMUL_LEGACY)
4253
0
  NODE_NAME_CASE(RSQ_CLAMP)
4254
0
  NODE_NAME_CASE(LDEXP)
4255
0
  NODE_NAME_CASE(FP_CLASS)
4256
0
  NODE_NAME_CASE(DOT4)
4257
0
  NODE_NAME_CASE(CARRY)
4258
0
  NODE_NAME_CASE(BORROW)
4259
0
  NODE_NAME_CASE(BFE_U32)
4260
0
  NODE_NAME_CASE(BFE_I32)
4261
0
  NODE_NAME_CASE(BFI)
4262
0
  NODE_NAME_CASE(BFM)
4263
0
  NODE_NAME_CASE(FFBH_U32)
4264
0
  NODE_NAME_CASE(FFBH_I32)
4265
0
  NODE_NAME_CASE(FFBL_B32)
4266
0
  NODE_NAME_CASE(MUL_U24)
4267
0
  NODE_NAME_CASE(MUL_I24)
4268
0
  NODE_NAME_CASE(MULHI_U24)
4269
0
  NODE_NAME_CASE(MULHI_I24)
4270
0
  NODE_NAME_CASE(MUL_LOHI_U24)
4271
0
  NODE_NAME_CASE(MUL_LOHI_I24)
4272
0
  NODE_NAME_CASE(MAD_U24)
4273
0
  NODE_NAME_CASE(MAD_I24)
4274
0
  NODE_NAME_CASE(MAD_I64_I32)
4275
0
  NODE_NAME_CASE(MAD_U64_U32)
4276
0
  NODE_NAME_CASE(PERM)
4277
0
  NODE_NAME_CASE(TEXTURE_FETCH)
4278
0
  NODE_NAME_CASE(EXPORT)
4279
0
  NODE_NAME_CASE(EXPORT_DONE)
4280
0
  NODE_NAME_CASE(R600_EXPORT)
4281
0
  NODE_NAME_CASE(CONST_ADDRESS)
4282
0
  NODE_NAME_CASE(REGISTER_LOAD)
4283
0
  NODE_NAME_CASE(REGISTER_STORE)
4284
0
  NODE_NAME_CASE(SAMPLE)
4285
0
  NODE_NAME_CASE(SAMPLEB)
4286
0
  NODE_NAME_CASE(SAMPLED)
4287
0
  NODE_NAME_CASE(SAMPLEL)
4288
0
  NODE_NAME_CASE(CVT_F32_UBYTE0)
4289
0
  NODE_NAME_CASE(CVT_F32_UBYTE1)
4290
0
  NODE_NAME_CASE(CVT_F32_UBYTE2)
4291
0
  NODE_NAME_CASE(CVT_F32_UBYTE3)
4292
0
  NODE_NAME_CASE(CVT_PKRTZ_F16_F32)
4293
0
  NODE_NAME_CASE(CVT_PKNORM_I16_F32)
4294
0
  NODE_NAME_CASE(CVT_PKNORM_U16_F32)
4295
0
  NODE_NAME_CASE(CVT_PK_I16_I32)
4296
0
  NODE_NAME_CASE(CVT_PK_U16_U32)
4297
0
  NODE_NAME_CASE(FP_TO_FP16)
4298
0
  NODE_NAME_CASE(FP16_ZEXT)
4299
0
  NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
4300
0
  NODE_NAME_CASE(CONST_DATA_PTR)
4301
0
  NODE_NAME_CASE(PC_ADD_REL_OFFSET)
4302
0
  NODE_NAME_CASE(LDS)
4303
0
  NODE_NAME_CASE(KILL)
4304
0
  NODE_NAME_CASE(DUMMY_CHAIN)
4305
0
  case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
4306
0
  NODE_NAME_CASE(INIT_EXEC)
4307
0
  NODE_NAME_CASE(INIT_EXEC_FROM_INPUT)
4308
0
  NODE_NAME_CASE(SENDMSG)
4309
0
  NODE_NAME_CASE(SENDMSGHALT)
4310
0
  NODE_NAME_CASE(INTERP_MOV)
4311
0
  NODE_NAME_CASE(INTERP_P1)
4312
0
  NODE_NAME_CASE(INTERP_P2)
4313
0
  NODE_NAME_CASE(INTERP_P1LL_F16)
4314
0
  NODE_NAME_CASE(INTERP_P1LV_F16)
4315
0
  NODE_NAME_CASE(INTERP_P2_F16)
4316
0
  NODE_NAME_CASE(LOAD_D16_HI)
4317
0
  NODE_NAME_CASE(LOAD_D16_LO)
4318
0
  NODE_NAME_CASE(LOAD_D16_HI_I8)
4319
0
  NODE_NAME_CASE(LOAD_D16_HI_U8)
4320
0
  NODE_NAME_CASE(LOAD_D16_LO_I8)
4321
0
  NODE_NAME_CASE(LOAD_D16_LO_U8)
4322
0
  NODE_NAME_CASE(STORE_MSKOR)
4323
0
  NODE_NAME_CASE(LOAD_CONSTANT)
4324
0
  NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
4325
0
  NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)
4326
0
  NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)
4327
0
  NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)
4328
0
  NODE_NAME_CASE(DS_ORDERED_COUNT)
4329
0
  NODE_NAME_CASE(ATOMIC_CMP_SWAP)
4330
0
  NODE_NAME_CASE(ATOMIC_INC)
4331
0
  NODE_NAME_CASE(ATOMIC_DEC)
4332
0
  NODE_NAME_CASE(ATOMIC_LOAD_FMIN)
4333
0
  NODE_NAME_CASE(ATOMIC_LOAD_FMAX)
4334
0
  NODE_NAME_CASE(BUFFER_LOAD)
4335
0
  NODE_NAME_CASE(BUFFER_LOAD_UBYTE)
4336
0
  NODE_NAME_CASE(BUFFER_LOAD_USHORT)
4337
0
  NODE_NAME_CASE(BUFFER_LOAD_BYTE)
4338
0
  NODE_NAME_CASE(BUFFER_LOAD_SHORT)
4339
0
  NODE_NAME_CASE(BUFFER_LOAD_FORMAT)
4340
0
  NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)
4341
0
  NODE_NAME_CASE(SBUFFER_LOAD)
4342
0
  NODE_NAME_CASE(BUFFER_STORE)
4343
0
  NODE_NAME_CASE(BUFFER_STORE_BYTE)
4344
0
  NODE_NAME_CASE(BUFFER_STORE_SHORT)
4345
0
  NODE_NAME_CASE(BUFFER_STORE_FORMAT)
4346
0
  NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)
4347
0
  NODE_NAME_CASE(BUFFER_ATOMIC_SWAP)
4348
0
  NODE_NAME_CASE(BUFFER_ATOMIC_ADD)
4349
0
  NODE_NAME_CASE(BUFFER_ATOMIC_SUB)
4350
0
  NODE_NAME_CASE(BUFFER_ATOMIC_SMIN)
4351
0
  NODE_NAME_CASE(BUFFER_ATOMIC_UMIN)
4352
0
  NODE_NAME_CASE(BUFFER_ATOMIC_SMAX)
4353
0
  NODE_NAME_CASE(BUFFER_ATOMIC_UMAX)
4354
0
  NODE_NAME_CASE(BUFFER_ATOMIC_AND)
4355
0
  NODE_NAME_CASE(BUFFER_ATOMIC_OR)
4356
0
  NODE_NAME_CASE(BUFFER_ATOMIC_XOR)
4357
0
  NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP)
4358
0
  NODE_NAME_CASE(BUFFER_ATOMIC_FADD)
4359
0
  NODE_NAME_CASE(BUFFER_ATOMIC_PK_FADD)
4360
0
  NODE_NAME_CASE(ATOMIC_FADD)
4361
0
  NODE_NAME_CASE(ATOMIC_PK_FADD)
4362
0
4363
0
  case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
4364
0
  }
4365
0
  return nullptr;
4366
0
}
4367
4368
SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4369
                                              SelectionDAG &DAG, int Enabled,
4370
                                              int &RefinementSteps,
4371
                                              bool &UseOneConstNR,
4372
8
                                              bool Reciprocal) const {
4373
8
  EVT VT = Operand.getValueType();
4374
8
4375
8
  if (VT == MVT::f32) {
4376
5
    RefinementSteps = 0;
4377
5
    return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
4378
5
  }
4379
3
4380
3
  // TODO: There is also f64 rsq instruction, but the documentation is less
4381
3
  // clear on its precision.
4382
3
4383
3
  return SDValue();
4384
3
}
4385
4386
SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4387
                                               SelectionDAG &DAG, int Enabled,
4388
336
                                               int &RefinementSteps) const {
4389
336
  EVT VT = Operand.getValueType();
4390
336
4391
336
  if (VT == MVT::f32) {
4392
300
    // Reciprocal, < 1 ulp error.
4393
300
    //
4394
300
    // This reciprocal approximation converges to < 0.5 ulp error with one
4395
300
    // newton rhapson performed with two fused multiple adds (FMAs).
4396
300
4397
300
    RefinementSteps = 0;
4398
300
    return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
4399
300
  }
4400
36
4401
36
  // TODO: There is also f64 rcp instruction, but the documentation is less
4402
36
  // clear on its precision.
4403
36
4404
36
  return SDValue();
4405
36
}
4406
4407
void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4408
    const SDValue Op, KnownBits &Known,
4409
370k
    const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
4410
370k
4411
370k
  Known.resetAll(); // Don't know anything.
4412
370k
4413
370k
  unsigned Opc = Op.getOpcode();
4414
370k
4415
370k
  switch (Opc) {
4416
370k
  default:
4417
91.6k
    break;
4418
370k
  case AMDGPUISD::CARRY:
4419
11.3k
  case AMDGPUISD::BORROW: {
4420
11.3k
    Known.Zero = APInt::getHighBitsSet(32, 31);
4421
11.3k
    break;
4422
11.3k
  }
4423
11.3k
4424
11.3k
  case AMDGPUISD::BFE_I32:
4425
758
  case AMDGPUISD::BFE_U32: {
4426
758
    ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4427
758
    if (!CWidth)
4428
0
      return;
4429
758
4430
758
    uint32_t Width = CWidth->getZExtValue() & 0x1f;
4431
758
4432
758
    if (Opc == AMDGPUISD::BFE_U32)
4433
726
      Known.Zero = APInt::getHighBitsSet(32, 32 - Width);
4434
758
4435
758
    break;
4436
758
  }
4437
4.00k
  case AMDGPUISD::FP_TO_FP16:
4438
4.00k
  case AMDGPUISD::FP16_ZEXT: {
4439
4.00k
    unsigned BitWidth = Known.getBitWidth();
4440
4.00k
4441
4.00k
    // High bits are zero.
4442
4.00k
    Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
4443
4.00k
    break;
4444
4.00k
  }
4445
88.2k
  case AMDGPUISD::MUL_U24:
4446
88.2k
  case AMDGPUISD::MUL_I24: {
4447
88.2k
    KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4448
88.2k
    KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4449
88.2k
    unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
4450
88.2k
                      RHSKnown.countMinTrailingZeros();
4451
88.2k
    Known.Zero.setLowBits(std::min(TrailZ, 32u));
4452
88.2k
4453
88.2k
    // Truncate to 24 bits.
4454
88.2k
    LHSKnown = LHSKnown.trunc(24);
4455
88.2k
    RHSKnown = RHSKnown.trunc(24);
4456
88.2k
4457
88.2k
    bool Negative = false;
4458
88.2k
    if (Opc == AMDGPUISD::MUL_I24) {
4459
21.9k
      unsigned LHSValBits = 24 - LHSKnown.countMinSignBits();
4460
21.9k
      unsigned RHSValBits = 24 - RHSKnown.countMinSignBits();
4461
21.9k
      unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4462
21.9k
      if (MaxValBits >= 32)
4463
21.9k
        break;
4464
5
      bool LHSNegative = LHSKnown.isNegative();
4465
5
      bool LHSPositive = LHSKnown.isNonNegative();
4466
5
      bool RHSNegative = RHSKnown.isNegative();
4467
5
      bool RHSPositive = RHSKnown.isNonNegative();
4468
5
      if ((!LHSNegative && 
!LHSPositive0
) || (!RHSNegative &&
!RHSPositive0
))
4469
0
        break;
4470
5
      Negative = (LHSNegative && RHSPositive) || (LHSPositive && 
RHSNegative0
);
4471
5
      if (Negative)
4472
0
        Known.One.setHighBits(32 - MaxValBits);
4473
5
      else
4474
5
        Known.Zero.setHighBits(32 - MaxValBits);
4475
66.2k
    } else {
4476
66.2k
      unsigned LHSValBits = 24 - LHSKnown.countMinLeadingZeros();
4477
66.2k
      unsigned RHSValBits = 24 - RHSKnown.countMinLeadingZeros();
4478
66.2k
      unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
4479
66.2k
      if (MaxValBits >= 32)
4480
21.1k
        break;
4481
45.1k
      Known.Zero.setHighBits(32 - MaxValBits);
4482
45.1k
    }
4483
88.2k
    
break45.1k
;
4484
88.2k
  }
4485
88.2k
  case AMDGPUISD::PERM: {
4486
26
    ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4487
26
    if (!CMask)
4488
0
      return;
4489
26
4490
26
    KnownBits LHSKnown = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
4491
26
    KnownBits RHSKnown = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
4492
26
    unsigned Sel = CMask->getZExtValue();
4493
26
4494
130
    for (unsigned I = 0; I < 32; 
I += 8104
) {
4495
104
      unsigned SelBits = Sel & 0xff;
4496
104
      if (SelBits < 4) {
4497
26
        SelBits *= 8;
4498
26
        Known.One |= ((RHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4499
26
        Known.Zero |= ((RHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4500
78
      } else if (SelBits < 7) {
4501
40
        SelBits = (SelBits & 3) * 8;
4502
40
        Known.One |= ((LHSKnown.One.getZExtValue() >> SelBits) & 0xff) << I;
4503
40
        Known.Zero |= ((LHSKnown.Zero.getZExtValue() >> SelBits) & 0xff) << I;
4504
40
      } else 
if (38
SelBits == 0x0c38
) {
4505
36
        Known.Zero |= 0xFFull << I;
4506
36
      } else 
if (2
SelBits > 0x0c2
) {
4507
0
        Known.One |= 0xFFull << I;
4508
0
      }
4509
104
      Sel >>= 8;
4510
104
    }
4511
26
    break;
4512
26
  }
4513
92
  case AMDGPUISD::BUFFER_LOAD_UBYTE:  {
4514
92
    Known.Zero.setHighBits(24);
4515
92
    break;
4516
26
  }
4517
92
  case AMDGPUISD::BUFFER_LOAD_USHORT: {
4518
92
    Known.Zero.setHighBits(16);
4519
92
    break;
4520
26
  }
4521
1.12k
  case AMDGPUISD::LDS: {
4522
1.12k
    auto GA = cast<GlobalAddressSDNode>(Op.getOperand(0).getNode());
4523
1.12k
    unsigned Align = GA->getGlobal()->getAlignment();
4524
1.12k
4525
1.12k
    Known.Zero.setHighBits(16);
4526
1.12k
    if (Align)
4527
1.07k
      Known.Zero.setLowBits(Log2_32(Align));
4528
1.12k
    break;
4529
26
  }
4530
173k
  case ISD::INTRINSIC_WO_CHAIN: {
4531
173k
    unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4532
173k
    switch (IID) {
4533
173k
    case Intrinsic::amdgcn_mbcnt_lo:
4534
5.76k
    case Intrinsic::amdgcn_mbcnt_hi: {
4535
5.76k
      const GCNSubtarget &ST =
4536
5.76k
          DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
4537
5.76k
      // These return at most the wavefront size - 1.
4538
5.76k
      unsigned Size = Op.getValueType().getSizeInBits();
4539
5.76k
      Known.Zero.setHighBits(Size - ST.getWavefrontSizeLog2());
4540
5.76k
      break;
4541
5.76k
    }
4542
167k
    default:
4543
167k
      break;
4544
173k
    }
4545
173k
  }
4546
370k
  }
4547
370k
}
4548
4549
unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
4550
    SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
4551
3.01k
    unsigned Depth) const {
4552
3.01k
  switch (Op.getOpcode()) {
4553
3.01k
  case AMDGPUISD::BFE_I32: {
4554
2
    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4555
2
    if (!Width)
4556
0
      return 1;
4557
2
4558
2
    unsigned SignBits = 32 - Width->getZExtValue() + 1;
4559
2
    if (!isNullConstant(Op.getOperand(1)))
4560
2
      return SignBits;
4561
0
4562
0
    // TODO: Could probably figure something out with non-0 offsets.
4563
0
    unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4564
0
    return std::max(SignBits, Op0SignBits);
4565
0
  }
4566
0
4567
0
  case AMDGPUISD::BFE_U32: {
4568
0
    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4569
0
    return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
4570
0
  }
4571
0
4572
1.34k
  case AMDGPUISD::CARRY:
4573
1.34k
  case AMDGPUISD::BORROW:
4574
1.34k
    return 31;
4575
1.34k
  case AMDGPUISD::BUFFER_LOAD_BYTE:
4576
0
    return 25;
4577
1.34k
  case AMDGPUISD::BUFFER_LOAD_SHORT:
4578
0
    return 17;
4579
1.34k
  case AMDGPUISD::BUFFER_LOAD_UBYTE:
4580
15
    return 24;
4581
1.34k
  case AMDGPUISD::BUFFER_LOAD_USHORT:
4582
17
    return 16;
4583
1.34k
  case AMDGPUISD::FP_TO_FP16:
4584
2
  case AMDGPUISD::FP16_ZEXT:
4585
2
    return 16;
4586
1.62k
  default:
4587
1.62k
    return 1;
4588
3.01k
  }
4589
3.01k
}
4590
4591
bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
4592
                                                        const SelectionDAG &DAG,
4593
                                                        bool SNaN,
4594
45
                                                        unsigned Depth) const {
4595
45
  unsigned Opcode = Op.getOpcode();
4596
45
  switch (Opcode) {
4597
45
  case AMDGPUISD::FMIN_LEGACY:
4598
0
  case AMDGPUISD::FMAX_LEGACY: {
4599
0
    if (SNaN)
4600
0
      return true;
4601
0
4602
0
    // TODO: Can check no nans on one of the operands for each one, but which
4603
0
    // one?
4604
0
    return false;
4605
0
  }
4606
1
  case AMDGPUISD::FMUL_LEGACY:
4607
1
  case AMDGPUISD::CVT_PKRTZ_F16_F32: {
4608
1
    if (SNaN)
4609
1
      return true;
4610
0
    return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4611
0
           DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4612
0
  }
4613
3
  case AMDGPUISD::FMED3:
4614
3
  case AMDGPUISD::FMIN3:
4615
3
  case AMDGPUISD::FMAX3:
4616
3
  case AMDGPUISD::FMAD_FTZ: {
4617
3
    if (SNaN)
4618
3
      return true;
4619
0
    return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
4620
0
           DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4621
0
           DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4622
0
  }
4623
0
  case AMDGPUISD::CVT_F32_UBYTE0:
4624
0
  case AMDGPUISD::CVT_F32_UBYTE1:
4625
0
  case AMDGPUISD::CVT_F32_UBYTE2:
4626
0
  case AMDGPUISD::CVT_F32_UBYTE3:
4627
0
    return true;
4628
0
4629
10
  case AMDGPUISD::RCP:
4630
10
  case AMDGPUISD::RSQ:
4631
10
  case AMDGPUISD::RCP_LEGACY:
4632
10
  case AMDGPUISD::RSQ_LEGACY:
4633
10
  case AMDGPUISD::RSQ_CLAMP: {
4634
10
    if (SNaN)
4635
8
      return true;
4636
2
4637
2
    // TODO: Need is known positive check.
4638
2
    return false;
4639
2
  }
4640
2
  case AMDGPUISD::LDEXP:
4641
2
  case AMDGPUISD::FRACT: {
4642
2
    if (SNaN)
4643
2
      return true;
4644
0
    return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
4645
0
  }
4646
0
  case AMDGPUISD::DIV_SCALE:
4647
0
  case AMDGPUISD::DIV_FMAS:
4648
0
  case AMDGPUISD::DIV_FIXUP:
4649
0
  case AMDGPUISD::TRIG_PREOP:
4650
0
    // TODO: Refine on operands.
4651
0
    return SNaN;
4652
0
  case AMDGPUISD::SIN_HW:
4653
0
  case AMDGPUISD::COS_HW: {
4654
0
    // TODO: Need check for infinity
4655
0
    return SNaN;
4656
0
  }
4657
29
  case ISD::INTRINSIC_WO_CHAIN: {
4658
29
    unsigned IntrinsicID
4659
29
      = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4660
29
    // TODO: Handle more intrinsics
4661
29
    switch (IntrinsicID) {
4662
29
    case Intrinsic::amdgcn_cubeid:
4663
1
      return true;
4664
29
4665
29
    case Intrinsic::amdgcn_frexp_mant: {
4666
2
      if (SNaN)
4667
2
        return true;
4668
0
      return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
4669
0
    }
4670
0
    case Intrinsic::amdgcn_cvt_pkrtz: {
4671
0
      if (SNaN)
4672
0
        return true;
4673
0
      return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
4674
0
             DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
4675
0
    }
4676
0
    case Intrinsic::amdgcn_fdot2:
4677
0
      // TODO: Refine on operand
4678
0
      return SNaN;
4679
26
    default:
4680
26
      return false;
4681
0
    }
4682
0
  }
4683
0
  default:
4684
0
    return false;
4685
45
  }
4686
45
}
4687
4688
TargetLowering::AtomicExpansionKind
4689
1.98k
AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
4690
1.98k
  switch (RMW->getOperation()) {
4691
1.98k
  case AtomicRMWInst::Nand:
4692
47
  case AtomicRMWInst::FAdd:
4693
47
  case AtomicRMWInst::FSub:
4694
47
    return AtomicExpansionKind::CmpXChg;
4695
1.93k
  default:
4696
1.93k
    return AtomicExpansionKind::None;
4697
1.98k
  }
4698
1.98k
}