Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the InstructionSelector class for
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/// AMDGPU.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
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#include "AMDGPU.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/IR/InstrTypes.h"
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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#undef AMDGPUSubtarget
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}
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namespace llvm {
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class AMDGPUInstrInfo;
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class AMDGPURegisterBankInfo;
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class GCNSubtarget;
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class MachineInstr;
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class MachineOperand;
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class MachineRegisterInfo;
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class SIInstrInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class AMDGPUInstructionSelector : public InstructionSelector {
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public:
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  AMDGPUInstructionSelector(const GCNSubtarget &STI,
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                            const AMDGPURegisterBankInfo &RBI,
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                            const AMDGPUTargetMachine &TM);
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  bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
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  static const char *getName();
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private:
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  struct GEPInfo {
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    const MachineInstr &GEP;
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    SmallVector<unsigned, 2> SgprParts;
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    SmallVector<unsigned, 2> VgprParts;
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    int64_t Imm;
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    GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
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  };
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  bool isInstrUniform(const MachineInstr &MI) const;
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  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
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  /// tblgen-erated 'select' implementation.
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  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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  MachineOperand getSubOperand64(MachineOperand &MO,
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                                 const TargetRegisterClass &SubRC,
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                                 unsigned SubIdx) const;
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  bool selectCOPY(MachineInstr &I) const;
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  bool selectPHI(MachineInstr &I) const;
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  bool selectG_TRUNC(MachineInstr &I) const;
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  bool selectG_SZA_EXT(MachineInstr &I) const;
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  bool selectG_CONSTANT(MachineInstr &I) const;
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  bool selectG_AND_OR_XOR(MachineInstr &I) const;
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  bool selectG_ADD_SUB(MachineInstr &I) const;
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  bool selectG_EXTRACT(MachineInstr &I) const;
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  bool selectG_MERGE_VALUES(MachineInstr &I) const;
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  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
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  bool selectG_GEP(MachineInstr &I) const;
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  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
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  bool selectG_INSERT(MachineInstr &I) const;
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  bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
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                                        CodeGenCoverage &CoverageInfo) const;
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  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
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  bool selectG_ICMP(MachineInstr &I) const;
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  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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                       SmallVectorImpl<GEPInfo> &AddrInfo) const;
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  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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  bool selectG_LOAD(MachineInstr &I) const;
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  bool selectG_SELECT(MachineInstr &I) const;
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  bool selectG_STORE(MachineInstr &I) const;
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  bool selectG_BRCOND(MachineInstr &I) const;
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  bool selectG_FRAME_INDEX(MachineInstr &I) const;
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  std::pair<Register, unsigned>
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  selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
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  InstructionSelector::ComplexRendererFns
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  selectVCSRC(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectVSRC0(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectVOP3Mods0(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectVOP3OMods(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectVOP3Mods(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectSmrdImm(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectSmrdImm32(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectSmrdSgpr(MachineOperand &Root) const;
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  template <bool Signed>
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  InstructionSelector::ComplexRendererFns
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  selectFlatOffsetImpl(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectFlatOffset(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectFlatOffsetSigned(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectMUBUFScratchOffen(MachineOperand &Root) const;
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  InstructionSelector::ComplexRendererFns
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  selectMUBUFScratchOffset(MachineOperand &Root) const;
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  const SIInstrInfo &TII;
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  const SIRegisterInfo &TRI;
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  const AMDGPURegisterBankInfo &RBI;
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  const AMDGPUTargetMachine &TM;
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  const GCNSubtarget &STI;
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  bool EnableLateStructurizeCFG;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#define AMDGPUSubtarget GCNSubtarget
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#undef AMDGPUSubtarget
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "AMDGPUGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // End llvm namespace.
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#endif