Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
/// \file
10
/// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11
//
12
//===----------------------------------------------------------------------===//
13
//
14
15
#include "AMDGPUAsmPrinter.h"
16
#include "AMDGPUSubtarget.h"
17
#include "AMDGPUTargetMachine.h"
18
#include "MCTargetDesc/AMDGPUInstPrinter.h"
19
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20
#include "R600AsmPrinter.h"
21
#include "SIInstrInfo.h"
22
#include "llvm/CodeGen/MachineBasicBlock.h"
23
#include "llvm/CodeGen/MachineInstr.h"
24
#include "llvm/IR/Constants.h"
25
#include "llvm/IR/Function.h"
26
#include "llvm/IR/GlobalVariable.h"
27
#include "llvm/MC/MCCodeEmitter.h"
28
#include "llvm/MC/MCContext.h"
29
#include "llvm/MC/MCExpr.h"
30
#include "llvm/MC/MCInst.h"
31
#include "llvm/MC/MCObjectStreamer.h"
32
#include "llvm/MC/MCStreamer.h"
33
#include "llvm/Support/ErrorHandling.h"
34
#include "llvm/Support/Format.h"
35
#include <algorithm>
36
37
using namespace llvm;
38
39
namespace {
40
41
class AMDGPUMCInstLower {
42
  MCContext &Ctx;
43
  const TargetSubtargetInfo &ST;
44
  const AsmPrinter &AP;
45
46
  const MCExpr *getLongBranchBlockExpr(const MachineBasicBlock &SrcBB,
47
                                       const MachineOperand &MO) const;
48
49
public:
50
  AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST,
51
                    const AsmPrinter &AP);
52
53
  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
54
55
  /// Lower a MachineInstr to an MCInst
56
  void lower(const MachineInstr *MI, MCInst &OutMI) const;
57
58
};
59
60
class R600MCInstLower : public AMDGPUMCInstLower {
61
public:
62
  R600MCInstLower(MCContext &ctx, const R600Subtarget &ST,
63
                  const AsmPrinter &AP);
64
65
  /// Lower a MachineInstr to an MCInst
66
  void lower(const MachineInstr *MI, MCInst &OutMI) const;
67
};
68
69
70
} // End anonymous namespace
71
72
#include "AMDGPUGenMCPseudoLowering.inc"
73
74
AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
75
                                     const TargetSubtargetInfo &st,
76
                                     const AsmPrinter &ap):
77
514k
  Ctx(ctx), ST(st), AP(ap) { }
78
79
1.78k
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
80
1.78k
  switch (MOFlags) {
81
1.78k
  default:
82
78
    return MCSymbolRefExpr::VK_None;
83
1.78k
  case SIInstrInfo::MO_GOTPCREL:
84
0
    return MCSymbolRefExpr::VK_GOTPCREL;
85
1.78k
  case SIInstrInfo::MO_GOTPCREL32_LO:
86
327
    return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
87
1.78k
  case SIInstrInfo::MO_GOTPCREL32_HI:
88
327
    return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
89
1.78k
  case SIInstrInfo::MO_REL32_LO:
90
410
    return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
91
1.78k
  case SIInstrInfo::MO_REL32_HI:
92
385
    return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
93
1.78k
  case SIInstrInfo::MO_ABS32_LO:
94
258
    return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
95
1.78k
  case SIInstrInfo::MO_ABS32_HI:
96
0
    return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
97
1.78k
  }
98
1.78k
}
99
100
const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
101
  const MachineBasicBlock &SrcBB,
102
37
  const MachineOperand &MO) const {
103
37
  const MCExpr *DestBBSym
104
37
    = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx);
105
37
  const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
106
37
107
37
  // FIXME: The first half of this assert should be removed. This should
108
37
  // probably be PC relative instead of using the source block symbol, and
109
37
  // therefore the indirect branch expansion should use a bundle.
110
37
  assert(
111
37
      skipDebugInstructionsForward(SrcBB.begin(), SrcBB.end())->getOpcode() ==
112
37
          AMDGPU::S_GETPC_B64 &&
113
37
      ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
114
37
115
37
  // s_getpc_b64 returns the address of next instruction.
116
37
  const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
117
37
  SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
118
37
119
37
  if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD)
120
29
    return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
121
8
122
8
  assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD);
123
8
  return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
124
8
}
125
126
bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
127
2.43M
                                     MCOperand &MCOp) const {
128
2.43M
  switch (MO.getType()) {
129
2.43M
  default:
130
0
    llvm_unreachable("unknown operand type");
131
2.43M
  case MachineOperand::MO_Immediate:
132
1.48M
    MCOp = MCOperand::createImm(MO.getImm());
133
1.48M
    return true;
134
2.43M
  case MachineOperand::MO_Register:
135
948k
    MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
136
948k
    return true;
137
2.43M
  case MachineOperand::MO_MachineBasicBlock: {
138
1.84k
    if (MO.getTargetFlags() != 0) {
139
37
      MCOp = MCOperand::createExpr(
140
37
        getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
141
1.81k
    } else {
142
1.81k
      MCOp = MCOperand::createExpr(
143
1.81k
        MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
144
1.81k
    }
145
1.84k
146
1.84k
    return true;
147
2.43M
  }
148
2.43M
  case MachineOperand::MO_GlobalAddress: {
149
1.78k
    const GlobalValue *GV = MO.getGlobal();
150
1.78k
    SmallString<128> SymbolName;
151
1.78k
    AP.getNameWithPrefix(SymbolName, GV);
152
1.78k
    MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
153
1.78k
    const MCExpr *Expr =
154
1.78k
      MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
155
1.78k
    int64_t Offset = MO.getOffset();
156
1.78k
    if (Offset != 0) {
157
1.44k
      Expr = MCBinaryExpr::createAdd(Expr,
158
1.44k
                                     MCConstantExpr::create(Offset, Ctx), Ctx);
159
1.44k
    }
160
1.78k
    MCOp = MCOperand::createExpr(Expr);
161
1.78k
    return true;
162
2.43M
  }
163
2.43M
  case MachineOperand::MO_ExternalSymbol: {
164
1.12k
    MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName()));
165
1.12k
    Sym->setExternal(true);
166
1.12k
    const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
167
1.12k
    MCOp = MCOperand::createExpr(Expr);
168
1.12k
    return true;
169
2.43M
  }
170
2.43M
  case MachineOperand::MO_RegisterMask:
171
0
    // Regmasks are like implicit defs.
172
0
    return false;
173
2.43M
  }
174
2.43M
}
175
176
427k
void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
177
427k
  unsigned Opcode = MI->getOpcode();
178
427k
  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
179
427k
180
427k
  // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
181
427k
  // need to select it to the subtarget specific version, and there's no way to
182
427k
  // do that with a single pseudo source operation.
183
427k
  if (Opcode == AMDGPU::S_SETPC_B64_return)
184
2.19k
    Opcode = AMDGPU::S_SETPC_B64;
185
425k
  else if (Opcode == AMDGPU::SI_CALL) {
186
645
    // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
187
645
    // called function (which we need to remove here).
188
645
    OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
189
645
    MCOperand Dest, Src;
190
645
    lowerOperand(MI->getOperand(0), Dest);
191
645
    lowerOperand(MI->getOperand(1), Src);
192
645
    OutMI.addOperand(Dest);
193
645
    OutMI.addOperand(Src);
194
645
    return;
195
424k
  } else if (Opcode == AMDGPU::SI_TCRETURN) {
196
48
    // TODO: How to use branch immediate and avoid register+add?
197
48
    Opcode = AMDGPU::S_SETPC_B64;
198
48
  }
199
427k
200
427k
  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
201
426k
  if (MCOpcode == -1) {
202
0
    LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
203
0
    C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
204
0
                "a target-specific version: " + Twine(MI->getOpcode()));
205
0
  }
206
426k
207
426k
  OutMI.setOpcode(MCOpcode);
208
426k
209
1.40M
  for (const MachineOperand &MO : MI->explicit_operands()) {
210
1.40M
    MCOperand MCOp;
211
1.40M
    lowerOperand(MO, MCOp);
212
1.40M
    OutMI.addOperand(MCOp);
213
1.40M
  }
214
426k
}
215
216
bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
217
56
                                    MCOperand &MCOp) const {
218
56
  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
219
56
  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
220
56
  return MCInstLowering.lowerOperand(MO, MCOp);
221
56
}
222
223
static const MCExpr *lowerAddrSpaceCast(const TargetMachine &TM,
224
                                        const Constant *CV,
225
56
                                        MCContext &OutContext) {
226
56
  // TargetMachine does not support llvm-style cast. Use C++-style cast.
227
56
  // This is safe since TM is always of type AMDGPUTargetMachine or its
228
56
  // derived class.
229
56
  auto &AT = static_cast<const AMDGPUTargetMachine&>(TM);
230
56
  auto *CE = dyn_cast<ConstantExpr>(CV);
231
56
232
56
  // Lower null pointers in private and local address space.
233
56
  // Clang generates addrspacecast for null pointers in private and local
234
56
  // address space, which needs to be lowered.
235
56
  if (CE && CE->getOpcode() == Instruction::AddrSpaceCast) {
236
56
    auto Op = CE->getOperand(0);
237
56
    auto SrcAddr = Op->getType()->getPointerAddressSpace();
238
56
    if (Op->isNullValue() && AT.getNullPointerValue(SrcAddr) == 0) {
239
56
      auto DstAddr = CE->getType()->getPointerAddressSpace();
240
56
      return MCConstantExpr::create(AT.getNullPointerValue(DstAddr),
241
56
        OutContext);
242
56
    }
243
0
  }
244
0
  return nullptr;
245
0
}
246
247
28
const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) {
248
28
  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
249
28
    return E;
250
0
  return AsmPrinter::lowerConstant(CV);
251
0
}
252
253
431k
void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
254
431k
  if (emitPseudoExpansionLowering(*OutStreamer, MI))
255
28
    return;
256
431k
257
431k
  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
258
431k
  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
259
431k
260
431k
  StringRef Err;
261
431k
  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
262
0
    LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
263
0
    C.emitError("Illegal instruction detected: " + Err);
264
0
    MI->print(errs());
265
0
  }
266
431k
267
431k
  if (MI->isBundle()) {
268
884
    const MachineBasicBlock *MBB = MI->getParent();
269
884
    MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
270
3.40k
    while (I != MBB->instr_end() && I->isInsideBundle()) {
271
2.52k
      EmitInstruction(&*I);
272
2.52k
      ++I;
273
2.52k
    }
274
430k
  } else {
275
430k
    // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
276
430k
    // placeholder terminator instructions and should only be printed as
277
430k
    // comments.
278
430k
    if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
279
682
      if (isVerbose()) {
280
678
        SmallVector<char, 16> BBStr;
281
678
        raw_svector_ostream Str(BBStr);
282
678
283
678
        const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
284
678
        const MCSymbolRefExpr *Expr
285
678
          = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
286
678
        Expr->print(Str, MAI);
287
678
        OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
288
678
      }
289
682
290
682
      return;
291
682
    }
292
429k
293
429k
    if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
294
2.02k
      if (isVerbose())
295
2.01k
        OutStreamer->emitRawComment(" return to shader part epilog");
296
2.02k
      return;
297
2.02k
    }
298
427k
299
427k
    if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
300
14
      if (isVerbose())
301
14
        OutStreamer->emitRawComment(" wave barrier");
302
14
      return;
303
14
    }
304
427k
305
427k
    if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
306
35
      if (isVerbose())
307
34
        OutStreamer->emitRawComment(" divergent unreachable");
308
35
      return;
309
35
    }
310
427k
311
427k
    MCInst TmpInst;
312
427k
    MCInstLowering.lower(MI, TmpInst);
313
427k
    EmitToStreamer(*OutStreamer, TmpInst);
314
427k
315
#ifdef EXPENSIVE_CHECKS
316
    // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
317
    // work correctly for the generic CPU).
318
    //
319
    // The isPseudo check really shouldn't be here, but unfortunately there are
320
    // some negative lit tests that depend on being able to continue through
321
    // here even when pseudo instructions haven't been lowered.
322
    if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU())) {
323
      SmallVector<MCFixup, 4> Fixups;
324
      SmallVector<char, 16> CodeBytes;
325
      raw_svector_ostream CodeStream(CodeBytes);
326
327
      std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
328
          *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
329
      InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
330
331
      assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
332
    }
333
#endif
334
335
427k
    if (DumpCodeInstEmitter) {
336
14
      // Disassemble instruction/operands to text
337
14
      DisasmLines.resize(DisasmLines.size() + 1);
338
14
      std::string &DisasmLine = DisasmLines.back();
339
14
      raw_string_ostream DisasmStream(DisasmLine);
340
14
341
14
      AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
342
14
                                    *STI.getRegisterInfo());
343
14
      InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
344
14
345
14
      // Disassemble instruction/operands to hex representation.
346
14
      SmallVector<MCFixup, 4> Fixups;
347
14
      SmallVector<char, 16> CodeBytes;
348
14
      raw_svector_ostream CodeStream(CodeBytes);
349
14
350
14
      DumpCodeInstEmitter->encodeInstruction(
351
14
          TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
352
14
      HexLines.resize(HexLines.size() + 1);
353
14
      std::string &HexLine = HexLines.back();
354
14
      raw_string_ostream HexStream(HexLine);
355
14
356
32
      for (size_t i = 0; i < CodeBytes.size(); 
i += 418
) {
357
18
        unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
358
18
        HexStream << format("%s%08X", (i > 0 ? 
" "4
:
""14
), CodeDWord);
359
18
      }
360
14
361
14
      DisasmStream.flush();
362
14
      DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
363
14
    }
364
427k
  }
365
431k
}
366
367
R600MCInstLower::R600MCInstLower(MCContext &Ctx, const R600Subtarget &ST,
368
                                 const AsmPrinter &AP) :
369
83.6k
        AMDGPUMCInstLower(Ctx, ST, AP) { }
370
371
83.6k
void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
372
83.6k
  OutMI.setOpcode(MI->getOpcode());
373
1.02M
  for (const MachineOperand &MO : MI->explicit_operands()) {
374
1.02M
    MCOperand MCOp;
375
1.02M
    lowerOperand(MO, MCOp);
376
1.02M
    OutMI.addOperand(MCOp);
377
1.02M
  }
378
83.6k
}
379
380
83.6k
void R600AsmPrinter::EmitInstruction(const MachineInstr *MI) {
381
83.6k
  const R600Subtarget &STI = MF->getSubtarget<R600Subtarget>();
382
83.6k
  R600MCInstLower MCInstLowering(OutContext, STI, *this);
383
83.6k
384
83.6k
  StringRef Err;
385
83.6k
  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
386
0
    LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
387
0
    C.emitError("Illegal instruction detected: " + Err);
388
0
    MI->print(errs());
389
0
  }
390
83.6k
391
83.6k
  if (MI->isBundle()) {
392
0
    const MachineBasicBlock *MBB = MI->getParent();
393
0
    MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
394
0
    while (I != MBB->instr_end() && I->isInsideBundle()) {
395
0
      EmitInstruction(&*I);
396
0
      ++I;
397
0
    }
398
83.6k
  } else {
399
83.6k
    MCInst TmpInst;
400
83.6k
    MCInstLowering.lower(MI, TmpInst);
401
83.6k
    EmitToStreamer(*OutStreamer, TmpInst);
402
83.6k
 }
403
83.6k
}
404
405
28
const MCExpr *R600AsmPrinter::lowerConstant(const Constant *CV) {
406
28
  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
407
28
    return E;
408
0
  return AsmPrinter::lowerConstant(CV);
409
0
}