Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
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//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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using namespace llvm;
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AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) {
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  static const unsigned SubRegs[] = {
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    AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
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    AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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    AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
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    AMDGPU::sub15, AMDGPU::sub16, AMDGPU::sub17, AMDGPU::sub18, AMDGPU::sub19,
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    AMDGPU::sub20, AMDGPU::sub21, AMDGPU::sub22, AMDGPU::sub23, AMDGPU::sub24,
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    AMDGPU::sub25, AMDGPU::sub26, AMDGPU::sub27, AMDGPU::sub28, AMDGPU::sub29,
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    AMDGPU::sub30, AMDGPU::sub31
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  };
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  assert(Channel < array_lengthof(SubRegs));
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  return SubRegs[Channel];
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}
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3.23M
void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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3.23M
  MCRegAliasIterator R(Reg, this, true);
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3.23M
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  for (; R.isValid(); 
++R27.8M
)
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    Reserved.set(*R);
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3.23M
}
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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// Forced to be here by one .inc
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const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
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  const MachineFunction *MF) const {
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  CallingConv::ID CC = MF->getFunction().getCallingConv();
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  switch (CC) {
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  case CallingConv::C:
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  case CallingConv::Fast:
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  case CallingConv::Cold:
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    return CSR_AMDGPU_HighRegs_SaveList;
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  default: {
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    // Dummy to not crash RegisterClassInfo.
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    static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
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    return &NoCalleeSavedReg;
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  }
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  }
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}
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const MCPhysReg *
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SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
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  return nullptr;
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}
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const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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                                                     CallingConv::ID CC) const {
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  switch (CC) {
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  case CallingConv::C:
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  case CallingConv::Fast:
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  case CallingConv::Cold:
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    return CSR_AMDGPU_HighRegs_RegMask;
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  default:
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    return nullptr;
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  }
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}
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Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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  const SIFrameLowering *TFI =
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      MF.getSubtarget<GCNSubtarget>().getFrameLowering();
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  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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  return TFI->hasFP(MF) ? 
FuncInfo->getFrameOffsetReg()1.00k
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                        : 
FuncInfo->getStackPtrOffsetReg()10.3k
;
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}
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const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const {
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  return CSR_AMDGPU_AllVGPRs_RegMask;
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}
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const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const {
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  return CSR_AMDGPU_AllAllocatableSRegs_RegMask;
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}