Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Line
Count
Source (jump to first uncovered line)
1
//=======- GCNDPPCombine.cpp - optimization for DPP instructions ---==========//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
// The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
9
// operand. If any of the use instruction cannot be combined with the mov the
10
// whole sequence is reverted.
11
//
12
// $old = ...
13
// $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
14
//                            dpp_controls..., $row_mask, $bank_mask, $bound_ctrl
15
// $res = VALU $dpp_value [, src1]
16
//
17
// to
18
//
19
// $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
20
//                 dpp_controls..., $row_mask, $bank_mask, $combined_bound_ctrl
21
//
22
// Combining rules :
23
//
24
// if $row_mask and $bank_mask are fully enabled (0xF) and
25
//    $bound_ctrl==DPP_BOUND_ZERO or $old==0
26
// -> $combined_old = undef,
27
//    $combined_bound_ctrl = DPP_BOUND_ZERO
28
//
29
// if the VALU op is binary and
30
//    $bound_ctrl==DPP_BOUND_OFF and
31
//    $old==identity value (immediate) for the VALU op
32
// -> $combined_old = src1,
33
//    $combined_bound_ctrl = DPP_BOUND_OFF
34
//
35
// Otherwise cancel.
36
//
37
// The mov_dpp instruction should reside in the same BB as all its uses
38
//===----------------------------------------------------------------------===//
39
40
#include "AMDGPU.h"
41
#include "AMDGPUSubtarget.h"
42
#include "SIInstrInfo.h"
43
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
44
#include "llvm/ADT/SmallVector.h"
45
#include "llvm/ADT/Statistic.h"
46
#include "llvm/CodeGen/MachineBasicBlock.h"
47
#include "llvm/CodeGen/MachineFunction.h"
48
#include "llvm/CodeGen/MachineFunctionPass.h"
49
#include "llvm/CodeGen/MachineInstr.h"
50
#include "llvm/CodeGen/MachineInstrBuilder.h"
51
#include "llvm/CodeGen/MachineOperand.h"
52
#include "llvm/CodeGen/MachineRegisterInfo.h"
53
#include "llvm/CodeGen/TargetRegisterInfo.h"
54
#include "llvm/Pass.h"
55
#include <cassert>
56
57
using namespace llvm;
58
59
#define DEBUG_TYPE "gcn-dpp-combine"
60
61
STATISTIC(NumDPPMovsCombined, "Number of DPP moves combined.");
62
63
namespace {
64
65
class GCNDPPCombine : public MachineFunctionPass {
66
  MachineRegisterInfo *MRI;
67
  const SIInstrInfo *TII;
68
69
  using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
70
71
  MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
72
73
  MachineInstr *createDPPInst(MachineInstr &OrigMI,
74
                              MachineInstr &MovMI,
75
                              RegSubRegPair CombOldVGPR,
76
                              MachineOperand *OldOpnd,
77
                              bool CombBCZ) const;
78
79
  MachineInstr *createDPPInst(MachineInstr &OrigMI,
80
                              MachineInstr &MovMI,
81
                              RegSubRegPair CombOldVGPR,
82
                              bool CombBCZ) const;
83
84
  bool hasNoImmOrEqual(MachineInstr &MI,
85
                       unsigned OpndName,
86
                       int64_t Value,
87
                       int64_t Mask = -1) const;
88
89
  bool combineDPPMov(MachineInstr &MI) const;
90
91
public:
92
  static char ID;
93
94
2.38k
  GCNDPPCombine() : MachineFunctionPass(ID) {
95
2.38k
    initializeGCNDPPCombinePass(*PassRegistry::getPassRegistry());
96
2.38k
  }
97
98
  bool runOnMachineFunction(MachineFunction &MF) override;
99
100
27.6k
  StringRef getPassName() const override { return "GCN DPP Combine"; }
101
102
2.36k
  void getAnalysisUsage(AnalysisUsage &AU) const override {
103
2.36k
    AU.setPreservesCFG();
104
2.36k
    MachineFunctionPass::getAnalysisUsage(AU);
105
2.36k
  }
106
};
107
108
} // end anonymous namespace
109
110
INITIALIZE_PASS(GCNDPPCombine, DEBUG_TYPE, "GCN DPP Combine", false, false)
111
112
char GCNDPPCombine::ID = 0;
113
114
char &llvm::GCNDPPCombineID = GCNDPPCombine::ID;
115
116
0
FunctionPass *llvm::createGCNDPPCombinePass() {
117
0
  return new GCNDPPCombine();
118
0
}
119
120
227
static int getDPPOp(unsigned Op) {
121
227
  auto DPP32 = AMDGPU::getDPPOp32(Op);
122
227
  if (DPP32 != -1)
123
116
    return DPP32;
124
111
125
111
  auto E32 = AMDGPU::getVOPe32(Op);
126
111
  return E32 != -1 ? AMDGPU::getDPPOp32(E32) : 
-10
;
127
111
}
128
129
// tracks the register operand definition and returns:
130
//   1. immediate operand used to initialize the register if found
131
//   2. nullptr if the register operand is undef
132
//   3. the operand itself otherwise
133
278
MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
134
278
  auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI);
135
278
  if (!Def)
136
1
    return nullptr;
137
277
138
277
  switch(Def->getOpcode()) {
139
277
  
default: break6
;
140
277
  case AMDGPU::IMPLICIT_DEF:
141
14
    return nullptr;
142
277
  case AMDGPU::COPY:
143
257
  case AMDGPU::V_MOV_B32_e32: {
144
257
    auto &Op1 = Def->getOperand(1);
145
257
    if (Op1.isImm())
146
257
      return &Op1;
147
0
    break;
148
0
  }
149
6
  }
150
6
  return &OldOpnd;
151
6
}
152
153
MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
154
                                           MachineInstr &MovMI,
155
                                           RegSubRegPair CombOldVGPR,
156
227
                                           bool CombBCZ) const {
157
227
  assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
158
227
  assert(TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg() ==
159
227
         TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)->getReg());
160
227
161
227
  auto OrigOp = OrigMI.getOpcode();
162
227
  auto DPPOp = getDPPOp(OrigOp);
163
227
  if (DPPOp == -1) {
164
0
    LLVM_DEBUG(dbgs() << "  failed: no DPP opcode\n");
165
0
    return nullptr;
166
0
  }
167
227
168
227
  auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
169
227
                         OrigMI.getDebugLoc(), TII->get(DPPOp));
170
227
  bool Fail = false;
171
227
  do {
172
227
    auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
173
227
    assert(Dst);
174
227
    DPPInst.add(*Dst);
175
227
    int NumOperands = 1;
176
227
177
227
    const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);
178
227
    if (OldIdx != -1) {
179
227
      assert(OldIdx == NumOperands);
180
227
      assert(isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI));
181
227
      DPPInst.addReg(CombOldVGPR.Reg, 0, CombOldVGPR.SubReg);
182
227
      ++NumOperands;
183
227
    } else {
184
0
      // TODO: this discards MAC/FMA instructions for now, let's add it later
185
0
      LLVM_DEBUG(dbgs() << "  failed: no old operand in DPP instruction,"
186
0
                           " TBD\n");
187
0
      Fail = true;
188
0
      break;
189
0
    }
190
227
191
227
    if (auto *Mod0 = TII->getNamedOperand(OrigMI,
192
2
                                          AMDGPU::OpName::src0_modifiers)) {
193
2
      assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
194
2
                                          AMDGPU::OpName::src0_modifiers));
195
2
      assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
196
2
      DPPInst.addImm(Mod0->getImm());
197
2
      ++NumOperands;
198
2
    }
199
227
    auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
200
227
    assert(Src0);
201
227
    if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
202
0
      LLVM_DEBUG(dbgs() << "  failed: src0 is illegal\n");
203
0
      Fail = true;
204
0
      break;
205
0
    }
206
227
    DPPInst.add(*Src0);
207
227
    DPPInst->getOperand(NumOperands).setIsKill(false);
208
227
    ++NumOperands;
209
227
210
227
    if (auto *Mod1 = TII->getNamedOperand(OrigMI,
211
2
                                          AMDGPU::OpName::src1_modifiers)) {
212
2
      assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
213
2
                                          AMDGPU::OpName::src1_modifiers));
214
2
      assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
215
2
      DPPInst.addImm(Mod1->getImm());
216
2
      ++NumOperands;
217
2
    }
218
227
    if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
219
224
      if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
220
0
        LLVM_DEBUG(dbgs() << "  failed: src1 is illegal\n");
221
0
        Fail = true;
222
0
        break;
223
0
      }
224
224
      DPPInst.add(*Src1);
225
224
      ++NumOperands;
226
224
    }
227
227
228
227
    if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
229
0
      if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
230
0
        LLVM_DEBUG(dbgs() << "  failed: src2 is illegal\n");
231
0
        Fail = true;
232
0
        break;
233
0
      }
234
0
      DPPInst.add(*Src2);
235
0
    }
236
227
237
227
    DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
238
227
    DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
239
227
    DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
240
227
    DPPInst.addImm(CombBCZ ? 
159
:
0168
);
241
227
  } while (false);
242
227
243
227
  if (Fail) {
244
0
    DPPInst.getInstr()->eraseFromParent();
245
0
    return nullptr;
246
0
  }
247
227
  LLVM_DEBUG(dbgs() << "  combined:  " << *DPPInst.getInstr());
248
227
  return DPPInst.getInstr();
249
227
}
250
251
168
static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
252
168
  assert(OldOpnd->isImm());
253
168
  switch (OrigMIOp) {
254
168
  
default: break0
;
255
168
  case AMDGPU::V_ADD_U32_e32:
256
107
  case AMDGPU::V_ADD_U32_e64:
257
107
  case AMDGPU::V_ADD_I32_e32:
258
107
  case AMDGPU::V_ADD_I32_e64:
259
107
  case AMDGPU::V_OR_B32_e32:
260
107
  case AMDGPU::V_OR_B32_e64:
261
107
  case AMDGPU::V_SUBREV_U32_e32:
262
107
  case AMDGPU::V_SUBREV_U32_e64:
263
107
  case AMDGPU::V_SUBREV_I32_e32:
264
107
  case AMDGPU::V_SUBREV_I32_e64:
265
107
  case AMDGPU::V_MAX_U32_e32:
266
107
  case AMDGPU::V_MAX_U32_e64:
267
107
  case AMDGPU::V_XOR_B32_e32:
268
107
  case AMDGPU::V_XOR_B32_e64:
269
107
    if (OldOpnd->getImm() == 0)
270
107
      return true;
271
0
    break;
272
27
  case AMDGPU::V_AND_B32_e32:
273
27
  case AMDGPU::V_AND_B32_e64:
274
27
  case AMDGPU::V_MIN_U32_e32:
275
27
  case AMDGPU::V_MIN_U32_e64:
276
27
    if (static_cast<uint32_t>(OldOpnd->getImm()) ==
277
27
        std::numeric_limits<uint32_t>::max())
278
27
      return true;
279
0
    break;
280
15
  case AMDGPU::V_MIN_I32_e32:
281
15
  case AMDGPU::V_MIN_I32_e64:
282
15
    if (static_cast<int32_t>(OldOpnd->getImm()) ==
283
15
        std::numeric_limits<int32_t>::max())
284
15
      return true;
285
0
    break;
286
15
  case AMDGPU::V_MAX_I32_e32:
287
15
  case AMDGPU::V_MAX_I32_e64:
288
15
    if (static_cast<int32_t>(OldOpnd->getImm()) ==
289
15
        std::numeric_limits<int32_t>::min())
290
15
      return true;
291
0
    break;
292
4
  case AMDGPU::V_MUL_I32_I24_e32:
293
4
  case AMDGPU::V_MUL_I32_I24_e64:
294
4
  case AMDGPU::V_MUL_U32_U24_e32:
295
4
  case AMDGPU::V_MUL_U32_U24_e64:
296
4
    if (OldOpnd->getImm() == 1)
297
4
      return true;
298
0
    break;
299
0
  }
300
0
  return false;
301
0
}
302
303
MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
304
                                           MachineInstr &MovMI,
305
                                           RegSubRegPair CombOldVGPR,
306
                                           MachineOperand *OldOpndValue,
307
229
                                           bool CombBCZ) const {
308
229
  assert(CombOldVGPR.Reg);
309
229
  if (!CombBCZ && 
OldOpndValue170
&&
OldOpndValue->isImm()170
) {
310
170
    auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
311
170
    if (!Src1 || 
!Src1->isReg()168
) {
312
2
      LLVM_DEBUG(dbgs() << "  failed: no src1 or it isn't a register\n");
313
2
      return nullptr;
314
2
    }
315
168
    if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
316
0
      LLVM_DEBUG(dbgs() << "  failed: old immediate isn't an identity\n");
317
0
      return nullptr;
318
0
    }
319
168
    CombOldVGPR = getRegSubRegPair(*Src1);
320
168
    if (!isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI)) {
321
0
      LLVM_DEBUG(dbgs() << "  failed: src1 isn't a VGPR32 register\n");
322
0
      return nullptr;
323
0
    }
324
227
  }
325
227
  return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ);
326
227
}
327
328
// returns true if MI doesn't have OpndName immediate operand or the
329
// operand has Value
330
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
331
452
                                    int64_t Value, int64_t Mask) const {
332
452
  auto *Imm = TII->getNamedOperand(MI, OpndName);
333
452
  if (!Imm)
334
329
    return true;
335
123
336
123
  assert(Imm->isImm());
337
123
  return (Imm->getImm() & Mask) == Value;
338
123
}
339
340
279
bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
341
279
  assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
342
279
  LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
343
279
344
279
  auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
345
279
  assert(DstOpnd && DstOpnd->isReg());
346
279
  auto DPPMovReg = DstOpnd->getReg();
347
279
  if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
348
1
    LLVM_DEBUG(dbgs() << "  failed: EXEC mask should remain the same"
349
1
                         " for all uses\n");
350
1
    return false;
351
1
  }
352
278
353
278
  auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
354
278
  assert(RowMaskOpnd && RowMaskOpnd->isImm());
355
278
  auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
356
278
  assert(BankMaskOpnd && BankMaskOpnd->isImm());
357
278
  const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
358
278
                            
BankMaskOpnd->getImm() == 0xF186
;
359
278
360
278
  auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
361
278
  assert(BCZOpnd && BCZOpnd->isImm());
362
278
  bool BoundCtrlZero = BCZOpnd->getImm();
363
278
364
278
  auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
365
278
  assert(OldOpnd && OldOpnd->isReg());
366
278
367
278
  auto * const OldOpndValue = getOldOpndValue(*OldOpnd);
368
278
  // OldOpndValue is either undef (IMPLICIT_DEF) or immediate or something else
369
278
  // We could use: assert(!OldOpndValue || OldOpndValue->isImm())
370
278
  // but the third option is used to distinguish undef from non-immediate
371
278
  // to reuse IMPLICIT_DEF instruction later
372
278
  assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd);
373
278
374
278
  bool CombBCZ = false;
375
278
376
278
  if (MaskAllLanes && 
BoundCtrlZero116
) { // [1]
377
12
    CombBCZ = true;
378
266
  } else {
379
266
    if (!OldOpndValue || 
!OldOpndValue->isImm()260
) {
380
12
      LLVM_DEBUG(dbgs() << "  failed: the DPP mov isn't combinable\n");
381
12
      return false;
382
12
    }
383
254
384
254
    if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
385
1
      LLVM_DEBUG(dbgs() <<
386
1
        "  failed: old reg def and mov should be in the same BB\n");
387
1
      return false;
388
1
    }
389
253
390
253
    if (OldOpndValue->getImm() == 0) {
391
180
      if (MaskAllLanes) {
392
74
        assert(!BoundCtrlZero); // by check [1]
393
74
        CombBCZ = true;
394
74
      }
395
180
    } else 
if (73
BoundCtrlZero73
) {
396
4
      assert(!MaskAllLanes); // by check [1]
397
4
      LLVM_DEBUG(dbgs() <<
398
4
        "  failed: old!=0 and bctrl:0 and not all lanes isn't combinable\n");
399
4
      return false;
400
4
    }
401
261
  }
402
261
403
261
  LLVM_DEBUG(dbgs() << "  old=";
404
261
    if (!OldOpndValue)
405
261
      dbgs() << "undef";
406
261
    else
407
261
      dbgs() << *OldOpndValue;
408
261
    dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
409
261
410
261
  SmallVector<MachineInstr*, 4> OrigMIs, DPPMIs;
411
261
  auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
412
261
  // try to reuse previous old reg if its undefined (IMPLICIT_DEF)
413
261
  if (CombBCZ && 
OldOpndValue86
) { // CombOldVGPR should be undef
414
77
    CombOldVGPR = RegSubRegPair(
415
77
      MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
416
77
    auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
417
77
                             TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
418
77
    DPPMIs.push_back(UndefInst.getInstr());
419
77
  }
420
261
421
261
  OrigMIs.push_back(&MovMI);
422
261
  bool Rollback = true;
423
266
  for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
424
266
    Rollback = true;
425
266
426
266
    auto &OrigMI = *Use.getParent();
427
266
    LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
428
266
429
266
    auto OrigOp = OrigMI.getOpcode();
430
266
    if (TII->isVOP3(OrigOp)) {
431
114
      if (!TII->hasVALU32BitEncoding(OrigOp)) {
432
0
        LLVM_DEBUG(dbgs() << "  failed: VOP3 hasn't e32 equivalent\n");
433
0
        break;
434
0
      }
435
114
      // check if other than abs|neg modifiers are set (opsel for example)
436
114
      const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
437
114
      if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
438
114
          
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask)113
||
439
114
          
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0)113
||
440
114
          
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)112
) {
441
3
        LLVM_DEBUG(dbgs() << "  failed: VOP3 has non-default modifiers\n");
442
3
        break;
443
3
      }
444
152
    } else if (!TII->isVOP1(OrigOp) && 
!TII->isVOP2(OrigOp)147
) {
445
32
      LLVM_DEBUG(dbgs() << "  failed: not VOP1/2/3\n");
446
32
      break;
447
32
    }
448
231
449
231
    LLVM_DEBUG(dbgs() << "  combining: " << OrigMI);
450
231
    if (&Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) {
451
30
      if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
452
28
                                        OldOpndValue, CombBCZ)) {
453
28
        DPPMIs.push_back(DPPInst);
454
28
        Rollback = false;
455
28
      }
456
201
    } else if (OrigMI.isCommutable() &&
457
201
               &Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
458
201
      auto *BB = OrigMI.getParent();
459
201
      auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
460
201
      BB->insert(OrigMI, NewMI);
461
201
      if (TII->commuteInstruction(*NewMI)) {
462
199
        LLVM_DEBUG(dbgs() << "  commuted:  " << *NewMI);
463
199
        if (auto *DPPInst = createDPPInst(*NewMI, MovMI, CombOldVGPR,
464
199
                                          OldOpndValue, CombBCZ)) {
465
199
          DPPMIs.push_back(DPPInst);
466
199
          Rollback = false;
467
199
        }
468
199
      } else
469
201
        LLVM_DEBUG(dbgs() << "  failed: cannot be commuted\n");
470
201
      NewMI->eraseFromParent();
471
201
    } else
472
201
      
LLVM_DEBUG0
(dbgs() << " failed: no suitable operands\n");
473
231
    if (Rollback)
474
4
      break;
475
227
    OrigMIs.push_back(&OrigMI);
476
227
  }
477
261
478
261
  for (auto *MI : *(Rollback? 
&DPPMIs39
:
&OrigMIs222
))
479
473
    MI->eraseFromParent();
480
261
481
261
  return !Rollback;
482
261
}
483
484
25.2k
bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
485
25.2k
  auto &ST = MF.getSubtarget<GCNSubtarget>();
486
25.2k
  if (!ST.hasDPP() || 
skipFunction(MF.getFunction())15.7k
)
487
9.54k
    return false;
488
15.6k
489
15.6k
  MRI = &MF.getRegInfo();
490
15.6k
  TII = ST.getInstrInfo();
491
15.6k
492
15.6k
  assert(MRI->isSSA() && "Must be run on SSA");
493
15.6k
494
15.6k
  bool Changed = false;
495
17.3k
  for (auto &MBB : MF) {
496
406k
    for (auto I = MBB.rbegin(), E = MBB.rend(); I != E;) {
497
389k
      auto &MI = *I++;
498
389k
      if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && 
combineDPPMov(MI)279
) {
499
222
        Changed = true;
500
222
        ++NumDPPMovsCombined;
501
222
      }
502
389k
    }
503
17.3k
  }
504
15.6k
  return Changed;
505
15.6k
}