Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
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//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file provides AMDGPU specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "AMDGPUELFStreamer.h"
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#include "AMDGPUInstPrinter.h"
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#include "AMDGPUMCAsmInfo.h"
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#include "AMDGPUTargetStreamer.h"
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#include "SIDefines.h"
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#include "TargetInfo/AMDGPUTargetInfo.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "AMDGPUGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "AMDGPUGenSubtargetInfo.inc"
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#define NoSchedModel NoSchedModelR600
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#define GET_SUBTARGETINFO_MC_DESC
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#include "R600GenSubtargetInfo.inc"
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#undef NoSchedModelR600
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#define GET_REGINFO_MC_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "R600GenRegisterInfo.inc"
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static MCInstrInfo *createAMDGPUMCInstrInfo() {
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  MCInstrInfo *X = new MCInstrInfo();
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  InitAMDGPUMCInstrInfo(X);
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  return X;
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}
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static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
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  MCRegisterInfo *X = new MCRegisterInfo();
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  if (TT.getArch() == Triple::r600)
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    InitR600MCRegisterInfo(X, 0);
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  else
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    InitAMDGPUMCRegisterInfo(X, 0);
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  return X;
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}
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static MCSubtargetInfo *
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createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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  if (TT.getArch() == Triple::r600)
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    return createR600MCSubtargetInfoImpl(TT, CPU, FS);
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  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
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                                                unsigned SyntaxVariant,
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                                                const MCAsmInfo &MAI,
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                                                const MCInstrInfo &MII,
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                                                const MCRegisterInfo &MRI) {
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  if (T.getArch() == Triple::r600)
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    return new R600InstPrinter(MAI, MII, MRI);
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  else
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    return new AMDGPUInstPrinter(MAI, MII, MRI);
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}
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static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
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                                                      formatted_raw_ostream &OS,
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                                                      MCInstPrinter *InstPrint,
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                                                      bool isVerboseAsm) {
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  return new AMDGPUTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
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                                                   MCStreamer &S,
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                                                   const MCSubtargetInfo &STI) {
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  return new AMDGPUTargetELFStreamer(S, STI);
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}
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static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
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                                    std::unique_ptr<MCAsmBackend> &&MAB,
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                                    std::unique_ptr<MCObjectWriter> &&OW,
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                                    std::unique_ptr<MCCodeEmitter> &&Emitter,
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                                    bool RelaxAll) {
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  return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
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                                 std::move(Emitter), RelaxAll);
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}
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namespace {
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class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
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public:
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  explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
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      : MCInstrAnalysis(Info) {}
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  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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                      uint64_t &Target) const override {
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    if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
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        Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
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            MCOI::OPERAND_PCREL)
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      return false;
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    int64_t Imm = Inst.getOperand(0).getImm();
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    // Our branches take a simm16, but we need two extra bits to account for
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    // the factor of 4.
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    APInt SignedOffset(18, Imm * 4, true);
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    Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
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    return true;
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  }
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};
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} // end anonymous namespace
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static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) {
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  return new AMDGPUMCInstrAnalysis(Info);
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}
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extern "C" void LLVMInitializeAMDGPUTargetMC() {
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  TargetRegistry::RegisterMCInstrInfo(getTheGCNTarget(), createAMDGPUMCInstrInfo);
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  TargetRegistry::RegisterMCInstrInfo(getTheAMDGPUTarget(), createR600MCInstrInfo);
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  for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
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    RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
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    TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
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    TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
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    TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
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    TargetRegistry::RegisterMCInstrAnalysis(*T, createAMDGPUMCInstrAnalysis);
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    TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
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    TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
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  }
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  // R600 specific registration
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  TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
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                                        createR600MCCodeEmitter);
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  TargetRegistry::RegisterObjectTargetStreamer(
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      getTheAMDGPUTarget(), createAMDGPUObjectTargetStreamer);
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  // GCN specific registration
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  TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
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                                        createSIMCCodeEmitter);
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  TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
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                                            createAMDGPUAsmTargetStreamer);
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  TargetRegistry::RegisterObjectTargetStreamer(
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      getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
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}