Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- SIMCCodeEmitter.cpp - SI Code Emitter -----------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
/// \file
10
/// The SI code emitter produces machine code that can be executed
11
/// directly on the GPU device.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "AMDGPU.h"
16
#include "AMDGPURegisterInfo.h"
17
#include "MCTargetDesc/AMDGPUFixupKinds.h"
18
#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
19
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20
#include "SIDefines.h"
21
#include "Utils/AMDGPUBaseInfo.h"
22
#include "llvm/MC/MCCodeEmitter.h"
23
#include "llvm/MC/MCContext.h"
24
#include "llvm/MC/MCExpr.h"
25
#include "llvm/MC/MCFixup.h"
26
#include "llvm/MC/MCInst.h"
27
#include "llvm/MC/MCInstrDesc.h"
28
#include "llvm/MC/MCInstrInfo.h"
29
#include "llvm/MC/MCRegisterInfo.h"
30
#include "llvm/MC/MCSubtargetInfo.h"
31
#include "llvm/MC/MCSymbol.h"
32
#include "llvm/Support/Casting.h"
33
#include "llvm/Support/ErrorHandling.h"
34
#include "llvm/Support/MathExtras.h"
35
#include "llvm/Support/raw_ostream.h"
36
#include <cassert>
37
#include <cstdint>
38
#include <cstdlib>
39
40
using namespace llvm;
41
42
namespace {
43
44
class SIMCCodeEmitter : public  AMDGPUMCCodeEmitter {
45
  const MCRegisterInfo &MRI;
46
47
  /// Encode an fp or int literal
48
  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
49
                          const MCSubtargetInfo &STI) const;
50
51
public:
52
  SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
53
                  MCContext &ctx)
54
684
      : AMDGPUMCCodeEmitter(mcii), MRI(mri) {}
55
  SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
56
  SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
57
58
  /// Encode the instruction and write it to the OS.
59
  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
60
                         SmallVectorImpl<MCFixup> &Fixups,
61
                         const MCSubtargetInfo &STI) const override;
62
63
  /// \returns the encoding for an MCOperand.
64
  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
65
                             SmallVectorImpl<MCFixup> &Fixups,
66
                             const MCSubtargetInfo &STI) const override;
67
68
  /// Use a fixup to encode the simm16 field for SOPP branch
69
  ///        instructions.
70
  unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
71
                             SmallVectorImpl<MCFixup> &Fixups,
72
                             const MCSubtargetInfo &STI) const override;
73
74
  unsigned getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
75
                              SmallVectorImpl<MCFixup> &Fixups,
76
                              const MCSubtargetInfo &STI) const override;
77
78
  unsigned getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
79
                                  SmallVectorImpl<MCFixup> &Fixups,
80
                                  const MCSubtargetInfo &STI) const override;
81
82
  unsigned getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
83
                                SmallVectorImpl<MCFixup> &Fixups,
84
                                const MCSubtargetInfo &STI) const override;
85
};
86
87
} // end anonymous namespace
88
89
MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
90
                                           const MCRegisterInfo &MRI,
91
684
                                           MCContext &Ctx) {
92
684
  return new SIMCCodeEmitter(MCII, MRI, Ctx);
93
684
}
94
95
// Returns the encoding value to use if the given integer is an integer inline
96
// immediate value, or 0 if it is not.
97
template <typename IntTy>
98
143k
static uint32_t getIntInlineImmEncoding(IntTy Imm) {
99
143k
  if (Imm >= 0 && 
Imm <= 6477.8k
)
100
32.7k
    return 128 + Imm;
101
110k
102
110k
  if (Imm >= -16 && 
Imm <= -173.9k
)
103
28.9k
    return 192 + std::abs(Imm);
104
82.0k
105
82.0k
  return 0;
106
82.0k
}
SIMCCodeEmitter.cpp:unsigned int getIntInlineImmEncoding<int>(int)
Line
Count
Source
98
80.4k
static uint32_t getIntInlineImmEncoding(IntTy Imm) {
99
80.4k
  if (Imm >= 0 && 
Imm <= 6442.5k
)
100
19.6k
    return 128 + Imm;
101
60.8k
102
60.8k
  if (Imm >= -16 && 
Imm <= -138.8k
)
103
15.9k
    return 192 + std::abs(Imm);
104
44.8k
105
44.8k
  return 0;
106
44.8k
}
SIMCCodeEmitter.cpp:unsigned int getIntInlineImmEncoding<long long>(long long)
Line
Count
Source
98
33.6k
static uint32_t getIntInlineImmEncoding(IntTy Imm) {
99
33.6k
  if (Imm >= 0 && 
Imm <= 6420.4k
)
100
6.80k
    return 128 + Imm;
101
26.8k
102
26.8k
  if (Imm >= -16 && 
Imm <= -120.3k
)
103
6.71k
    return 192 + std::abs(Imm);
104
20.1k
105
20.1k
  return 0;
106
20.1k
}
SIMCCodeEmitter.cpp:unsigned int getIntInlineImmEncoding<short>(short)
Line
Count
Source
98
29.5k
static uint32_t getIntInlineImmEncoding(IntTy Imm) {
99
29.5k
  if (Imm >= 0 && 
Imm <= 6414.9k
)
100
6.31k
    return 128 + Imm;
101
23.2k
102
23.2k
  if (Imm >= -16 && 
Imm <= -114.8k
)
103
6.21k
    return 192 + std::abs(Imm);
104
16.9k
105
16.9k
  return 0;
106
16.9k
}
107
108
29.5k
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
109
29.5k
  uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
110
29.5k
  if (IntImm != 0)
111
12.5k
    return IntImm;
112
16.9k
113
16.9k
  if (Val == 0x3800) // 0.5
114
6.24k
    return 240;
115
10.7k
116
10.7k
  if (Val == 0xB800) // -0.5
117
22
    return 241;
118
10.7k
119
10.7k
  if (Val == 0x3C00) // 1.0
120
26
    return 242;
121
10.6k
122
10.6k
  if (Val == 0xBC00) // -1.0
123
30
    return 243;
124
10.6k
125
10.6k
  if (Val == 0x4000) // 2.0
126
24
    return 244;
127
10.6k
128
10.6k
  if (Val == 0xC000) // -2.0
129
22
    return 245;
130
10.6k
131
10.6k
  if (Val == 0x4400) // 4.0
132
26
    return 246;
133
10.5k
134
10.5k
  if (Val == 0xC400) // -4.0
135
6.19k
    return 247;
136
4.40k
137
4.40k
  if (Val == 0x3118 && // 1.0 / (2.0 * pi)
138
4.40k
      
STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]30
)
139
30
    return 248;
140
4.37k
141
4.37k
  return 255;
142
4.37k
}
143
144
80.4k
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
145
80.4k
  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
146
80.4k
  if (IntImm != 0)
147
35.5k
    return IntImm;
148
44.8k
149
44.8k
  if (Val == FloatToBits(0.5f))
150
14.8k
    return 240;
151
29.9k
152
29.9k
  if (Val == FloatToBits(-0.5f))
153
3
    return 241;
154
29.9k
155
29.9k
  if (Val == FloatToBits(1.0f))
156
79
    return 242;
157
29.9k
158
29.9k
  if (Val == FloatToBits(-1.0f))
159
76
    return 243;
160
29.8k
161
29.8k
  if (Val == FloatToBits(2.0f))
162
8
    return 244;
163
29.8k
164
29.8k
  if (Val == FloatToBits(-2.0f))
165
260
    return 245;
166
29.5k
167
29.5k
  if (Val == FloatToBits(4.0f))
168
61
    return 246;
169
29.5k
170
29.5k
  if (Val == FloatToBits(-4.0f))
171
14.8k
    return 247;
172
14.6k
173
14.6k
  if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
174
14.6k
      
STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]97
)
175
61
    return 248;
176
14.6k
177
14.6k
  return 255;
178
14.6k
}
179
180
33.6k
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
181
33.6k
  uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
182
33.6k
  if (IntImm != 0)
183
13.5k
    return IntImm;
184
20.1k
185
20.1k
  if (Val == DoubleToBits(0.5))
186
6.57k
    return 240;
187
13.5k
188
13.5k
  if (Val == DoubleToBits(-0.5))
189
1
    return 241;
190
13.5k
191
13.5k
  if (Val == DoubleToBits(1.0))
192
4
    return 242;
193
13.5k
194
13.5k
  if (Val == DoubleToBits(-1.0))
195
43
    return 243;
196
13.5k
197
13.5k
  if (Val == DoubleToBits(2.0))
198
2
    return 244;
199
13.5k
200
13.5k
  if (Val == DoubleToBits(-2.0))
201
1
    return 245;
202
13.5k
203
13.5k
  if (Val == DoubleToBits(4.0))
204
40
    return 246;
205
13.4k
206
13.4k
  if (Val == DoubleToBits(-4.0))
207
6.51k
    return 247;
208
6.97k
209
6.97k
  if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
210
6.97k
      
STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]37
)
211
37
    return 248;
212
6.94k
213
6.94k
  return 255;
214
6.94k
}
215
216
uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
217
                                         const MCOperandInfo &OpInfo,
218
452k
                                         const MCSubtargetInfo &STI) const {
219
452k
  int64_t Imm;
220
452k
  if (MO.isExpr()) {
221
330
    const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
222
330
    if (!C)
223
330
      return 255;
224
0
225
0
    Imm = C->getValue();
226
451k
  } else {
227
451k
228
451k
    assert(!MO.isFPImm());
229
451k
230
451k
    if (!MO.isImm())
231
308k
      return ~0;
232
143k
233
143k
    Imm = MO.getImm();
234
143k
  }
235
452k
236
452k
  switch (OpInfo.OperandType) {
237
143k
  case AMDGPU::OPERAND_REG_IMM_INT32:
238
80.2k
  case AMDGPU::OPERAND_REG_IMM_FP32:
239
80.2k
  case AMDGPU::OPERAND_REG_INLINE_C_INT32:
240
80.2k
  case AMDGPU::OPERAND_REG_INLINE_C_FP32:
241
80.2k
  case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
242
80.2k
  case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
243
80.2k
    return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
244
80.2k
245
80.2k
  case AMDGPU::OPERAND_REG_IMM_INT64:
246
33.6k
  case AMDGPU::OPERAND_REG_IMM_FP64:
247
33.6k
  case AMDGPU::OPERAND_REG_INLINE_C_INT64:
248
33.6k
  case AMDGPU::OPERAND_REG_INLINE_C_FP64:
249
33.6k
    return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
250
33.6k
251
33.6k
  case AMDGPU::OPERAND_REG_IMM_INT16:
252
28.9k
  case AMDGPU::OPERAND_REG_IMM_FP16:
253
28.9k
  case AMDGPU::OPERAND_REG_INLINE_C_INT16:
254
28.9k
  case AMDGPU::OPERAND_REG_INLINE_C_FP16:
255
28.9k
  case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
256
28.9k
  case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
257
28.9k
    // FIXME Is this correct? What do inline immediates do on SI for f16 src
258
28.9k
    // which does not have f16 support?
259
28.9k
    return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
260
28.9k
261
28.9k
  case AMDGPU::OPERAND_REG_IMM_V2INT16:
262
758
  case AMDGPU::OPERAND_REG_IMM_V2FP16:
263
758
    if (!isUInt<16>(Imm) && 
STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]251
)
264
194
      return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
265
564
    LLVM_FALLTHROUGH;
266
564
  case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
267
564
  case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
268
564
  case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
269
564
  case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
270
564
    uint16_t Lo16 = static_cast<uint16_t>(Imm);
271
564
    uint32_t Encoding = getLit16Encoding(Lo16, STI);
272
564
    return Encoding;
273
564
  }
274
564
  default:
275
0
    llvm_unreachable("invalid operand size");
276
143k
  }
277
143k
}
278
279
void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
280
                                       SmallVectorImpl<MCFixup> &Fixups,
281
451k
                                       const MCSubtargetInfo &STI) const {
282
451k
  verifyInstructionPredicates(MI,
283
451k
                              computeAvailableFeatures(STI.getFeatureBits()));
284
451k
285
451k
  uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
286
451k
  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
287
451k
  unsigned bytes = Desc.getSize();
288
451k
289
3.56M
  for (unsigned i = 0; i < bytes; 
i++3.11M
) {
290
3.11M
    OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
291
3.11M
  }
292
451k
293
451k
  // NSA encoding.
294
451k
  if (AMDGPU::isGFX10(STI) && 
Desc.TSFlags & SIInstrFlags::MIMG200k
) {
295
424
    int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
296
424
                                            AMDGPU::OpName::vaddr0);
297
424
    int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
298
424
                                           AMDGPU::OpName::srsrc);
299
424
    assert(vaddr0 >= 0 && srsrc > vaddr0);
300
424
    unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
301
424
    unsigned NumPadding = (-NumExtraAddrs) & 3;
302
424
303
1.12k
    for (unsigned i = 0; i < NumExtraAddrs; 
++i701
)
304
701
      OS.write((uint8_t)getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i),
305
701
                                          Fixups, STI));
306
675
    for (unsigned i = 0; i < NumPadding; 
++i251
)
307
251
      OS.write(0);
308
424
  }
309
451k
310
451k
  if ((bytes > 8 && 
STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]0
) ||
311
451k
      (bytes > 4 && 
!STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]327k
))
312
178k
    return;
313
273k
314
273k
  // Check for additional literals in SRC0/1/2 (Op 1/2/3)
315
1.45M
  
for (unsigned i = 0, e = Desc.getNumOperands(); 273k
i < e;
++i1.18M
) {
316
1.19M
317
1.19M
    // Check if this operand should be encoded as [SV]Src
318
1.19M
    if (!AMDGPU::isSISrcOperand(Desc, i))
319
830k
      continue;
320
367k
321
367k
    // Is this operand a literal immediate?
322
367k
    const MCOperand &Op = MI.getOperand(i);
323
367k
    if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
324
354k
      continue;
325
13.0k
326
13.0k
    // Yes! Encode it
327
13.0k
    int64_t Imm = 0;
328
13.0k
329
13.0k
    if (Op.isImm())
330
12.9k
      Imm = Op.getImm();
331
165
    else if (Op.isExpr()) {
332
165
      if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
333
0
        Imm = C->getValue();
334
165
335
165
    } else 
if (0
!Op.isExpr()0
) // Exprs will be replaced with a fixup value.
336
0
      llvm_unreachable("Must be immediate or expr");
337
13.0k
338
65.4k
    
for (unsigned j = 0; 13.0k
j < 4;
j++52.3k
) {
339
52.3k
      OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
340
52.3k
    }
341
13.0k
342
13.0k
    // Only one literal value allowed
343
13.0k
    break;
344
13.0k
  }
345
273k
}
346
347
unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
348
                                            SmallVectorImpl<MCFixup> &Fixups,
349
703
                                            const MCSubtargetInfo &STI) const {
350
703
  const MCOperand &MO = MI.getOperand(OpNo);
351
703
352
703
  if (MO.isExpr()) {
353
132
    const MCExpr *Expr = MO.getExpr();
354
132
    MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
355
132
    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
356
132
    return 0;
357
132
  }
358
571
359
571
  return getMachineOpValue(MI, MO, Fixups, STI);
360
571
}
361
362
unsigned
363
SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
364
                                    SmallVectorImpl<MCFixup> &Fixups,
365
135k
                                    const MCSubtargetInfo &STI) const {
366
135k
  using namespace AMDGPU::SDWA;
367
135k
368
135k
  uint64_t RegEnc = 0;
369
135k
370
135k
  const MCOperand &MO = MI.getOperand(OpNo);
371
135k
372
135k
  if (MO.isReg()) {
373
132k
    unsigned Reg = MO.getReg();
374
132k
    RegEnc |= MRI.getEncodingValue(Reg);
375
132k
    RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
376
132k
    if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
377
15.1k
      RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
378
15.1k
    }
379
132k
    return RegEnc;
380
132k
  } else {
381
2.96k
    const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
382
2.96k
    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
383
2.96k
    if (Enc != ~0U && Enc != 255) {
384
2.96k
      return Enc | SDWA9EncValues::SRC_SGPR_MASK;
385
2.96k
    }
386
0
  }
387
0
388
0
  llvm_unreachable("Unsupported operand kind");
389
0
  return 0;
390
0
}
391
392
unsigned
393
SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
394
                                        SmallVectorImpl<MCFixup> &Fixups,
395
25.3k
                                        const MCSubtargetInfo &STI) const {
396
25.3k
  using namespace AMDGPU::SDWA;
397
25.3k
398
25.3k
  uint64_t RegEnc = 0;
399
25.3k
400
25.3k
  const MCOperand &MO = MI.getOperand(OpNo);
401
25.3k
402
25.3k
  unsigned Reg = MO.getReg();
403
25.3k
  if (Reg != AMDGPU::VCC && 
Reg != AMDGPU::VCC_LO24.6k
) {
404
24.4k
    RegEnc |= MRI.getEncodingValue(Reg);
405
24.4k
    RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
406
24.4k
    RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
407
24.4k
  }
408
25.3k
  return RegEnc;
409
25.3k
}
410
411
unsigned
412
SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
413
                                      SmallVectorImpl<MCFixup> &Fixups,
414
1.29k
                                      const MCSubtargetInfo &STI) const {
415
1.29k
  unsigned Reg = MI.getOperand(OpNo).getReg();
416
1.29k
  uint64_t Enc = MRI.getEncodingValue(Reg);
417
1.29k
418
1.29k
  // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
419
1.29k
  // instructions use acc[0:1] modifier bits to distinguish. These bits are
420
1.29k
  // encoded as a virtual 9th bit of the register for these operands.
421
1.29k
  if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
422
1.29k
      
MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg)800
)
423
650
    Enc |= 512;
424
1.29k
425
1.29k
  return Enc;
426
1.29k
}
427
428
217
static bool needsPCRel(const MCExpr *Expr) {
429
217
  switch (Expr->getKind()) {
430
217
  case MCExpr::SymbolRef: {
431
144
    auto *SE = cast<MCSymbolRefExpr>(Expr);
432
144
    MCSymbolRefExpr::VariantKind Kind = SE->getKind();
433
144
    return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO &&
434
144
           
Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI138
;
435
217
  }
436
217
  case MCExpr::Binary: {
437
71
    auto *BE = cast<MCBinaryExpr>(Expr);
438
71
    if (BE->getOpcode() == MCBinaryExpr::Sub)
439
21
      return false;
440
50
    return needsPCRel(BE->getLHS()) || 
needsPCRel(BE->getRHS())0
;
441
50
  }
442
50
  case MCExpr::Unary:
443
2
    return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
444
50
  case MCExpr::Target:
445
0
  case MCExpr::Constant:
446
0
    return false;
447
0
  }
448
0
  llvm_unreachable("invalid kind");
449
0
}
450
451
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
452
                                            const MCOperand &MO,
453
                                       SmallVectorImpl<MCFixup> &Fixups,
454
2.09M
                                       const MCSubtargetInfo &STI) const {
455
2.09M
  if (MO.isReg())
456
952k
    return MRI.getEncodingValue(MO.getReg());
457
1.14M
458
1.14M
  if (MO.isExpr() && 
MO.getExpr()->getKind() != MCExpr::Constant165
) {
459
165
    // FIXME: If this is expression is PCRel or not should not depend on what
460
165
    // the expression looks like. Given that this is just a general expression,
461
165
    // it should probably be FK_Data_4 and whatever is producing
462
165
    //
463
165
    //    s_add_u32 s2, s2, (extern_const_addrspace+16
464
165
    //
465
165
    // And expecting a PCRel should instead produce
466
165
    //
467
165
    // .Ltmp1:
468
165
    //   s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
469
165
    MCFixupKind Kind;
470
165
    if (needsPCRel(MO.getExpr()))
471
138
      Kind = FK_PCRel_4;
472
27
    else
473
27
      Kind = FK_Data_4;
474
165
475
165
    const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
476
165
    uint32_t Offset = Desc.getSize();
477
165
    assert(Offset == 4 || Offset == 8);
478
165
479
165
    Fixups.push_back(
480
165
      MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
481
165
  }
482
1.14M
483
1.14M
  // Figure out the operand number, needed for isSrcOperand check
484
1.14M
  unsigned OpNo = 0;
485
5.87M
  for (unsigned e = MI.getNumOperands(); OpNo < e; 
++OpNo4.73M
) {
486
5.87M
    if (&MO == &MI.getOperand(OpNo))
487
1.14M
      break;
488
5.87M
  }
489
1.14M
490
1.14M
  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
491
1.14M
  if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
492
81.5k
    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
493
81.5k
    if (Enc != ~0U &&
494
81.5k
        (Enc != 255 || 
Desc.getSize() == 413.2k
||
Desc.getSize() == 8340
))
495
81.5k
      return Enc;
496
1.06M
497
1.06M
  } else if (MO.isImm())
498
1.06M
    return MO.getImm();
499
0
500
0
  llvm_unreachable("Encoding of this operand type is not supported yet.");
501
0
  return 0;
502
0
}
503
504
#define ENABLE_INSTR_PREDICATE_VERIFIER
505
#include "AMDGPUGenMCCodeEmitter.inc"