Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
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//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
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  RCW.RegWeight = 0;
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  RCW.WeightLimit = 0;
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}
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#define GET_REGINFO_TARGET_DESC
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#include "R600GenRegisterInfo.inc"
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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  BitVector Reserved(getNumRegs());
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  const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
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  const R600InstrInfo *TII = ST.getInstrInfo();
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  reserveRegisterTuples(Reserved, R600::ZERO);
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  reserveRegisterTuples(Reserved, R600::HALF);
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  reserveRegisterTuples(Reserved, R600::ONE);
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  reserveRegisterTuples(Reserved, R600::ONE_INT);
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  reserveRegisterTuples(Reserved, R600::NEG_HALF);
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  reserveRegisterTuples(Reserved, R600::NEG_ONE);
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  reserveRegisterTuples(Reserved, R600::PV_X);
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  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
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  reserveRegisterTuples(Reserved, R600::ALU_CONST);
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  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
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  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
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  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
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  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
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  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
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  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
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                        E = R600::R600_AddrRegClass.end(); I != E; 
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) {
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    reserveRegisterTuples(Reserved, *I);
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  }
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  TII->reserveIndirectRegisters(Reserved, MF, *this);
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  return Reserved;
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}
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// Dummy to not crash RegisterClassInfo.
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static const MCPhysReg CalleeSavedReg = R600::NoRegister;
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const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
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  const MachineFunction *) const {
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  return &CalleeSavedReg;
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}
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Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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  return R600::NoRegister;
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
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  return GET_REG_INDEX(getEncodingValue(Reg));
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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                                                                   MVT VT) const {
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  switch(VT.SimpleTy) {
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  default:
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  case MVT::i32: return &R600::R600_TReg32RegClass;
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  }
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}
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const RegClassWeight &R600RegisterInfo::getRegClassWeight(
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  const TargetRegisterClass *RC) const {
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  return RCW;
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}
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bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
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  assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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  switch (Reg) {
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  case R600::OQAP:
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  case R600::OQBP:
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  case R600::AR_X:
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    return false;
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  default:
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    return true;
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  }
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}
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void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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                                           int SPAdj,
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                                           unsigned FIOperandNum,
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                                           RegScavenger *RS) const {
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  llvm_unreachable("Subroutines not supported yet");
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}
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void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
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  MCRegAliasIterator R(Reg, this, true);
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  for (; R.isValid(); 
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)
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    Reserved.set(*R);
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}