Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/SIDefines.h
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//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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namespace llvm {
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namespace SIInstrFlags {
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// This needs to be kept in sync with the field bits in InstSI.
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enum : uint64_t {
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  // Low bits - basic encoding information.
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  SALU = 1 << 0,
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  VALU = 1 << 1,
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  // SALU instruction formats.
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  SOP1 = 1 << 2,
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  SOP2 = 1 << 3,
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  SOPC = 1 << 4,
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  SOPK = 1 << 5,
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  SOPP = 1 << 6,
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  // VALU instruction formats.
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  VOP1 = 1 << 7,
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  VOP2 = 1 << 8,
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  VOPC = 1 << 9,
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 // TODO: Should this be spilt into VOP3 a and b?
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  VOP3 = 1 << 10,
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  VOP3P = 1 << 12,
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  VINTRP = 1 << 13,
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  SDWA = 1 << 14,
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  DPP = 1 << 15,
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  // Memory instruction formats.
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  MUBUF = 1 << 16,
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  MTBUF = 1 << 17,
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  SMRD = 1 << 18,
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  MIMG = 1 << 19,
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  EXP = 1 << 20,
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  FLAT = 1 << 21,
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  DS = 1 << 22,
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  // Pseudo instruction formats.
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  VGPRSpill = 1 << 23,
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  SGPRSpill = 1 << 24,
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  // High bits - other information.
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  VM_CNT = UINT64_C(1) << 32,
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  EXP_CNT = UINT64_C(1) << 33,
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  LGKM_CNT = UINT64_C(1) << 34,
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  WQM = UINT64_C(1) << 35,
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  DisableWQM = UINT64_C(1) << 36,
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  Gather4 = UINT64_C(1) << 37,
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  SOPK_ZEXT = UINT64_C(1) << 38,
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  SCALAR_STORE = UINT64_C(1) << 39,
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  FIXED_SIZE = UINT64_C(1) << 40,
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  VOPAsmPrefer32Bit = UINT64_C(1) << 41,
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  VOP3_OPSEL = UINT64_C(1) << 42,
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  maybeAtomic = UINT64_C(1) << 43,
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  renamedInGFX9 = UINT64_C(1) << 44,
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  // Is a clamp on FP type.
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  FPClamp = UINT64_C(1) << 45,
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  // Is an integer clamp
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  IntClamp = UINT64_C(1) << 46,
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  // Clamps lo component of register.
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  ClampLo = UINT64_C(1) << 47,
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  // Clamps hi component of register.
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  // ClampLo and ClampHi set for packed clamp.
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  ClampHi = UINT64_C(1) << 48,
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  // Is a packed VOP3P instruction.
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  IsPacked = UINT64_C(1) << 49,
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  // Is a D16 buffer instruction.
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  D16Buf = UINT64_C(1) << 50,
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  // FLAT instruction accesses FLAT_GLBL or FLAT_SCRATCH segment.
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  IsNonFlatSeg = UINT64_C(1) << 51,
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  // Uses floating point double precision rounding mode
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  FPDPRounding = UINT64_C(1) << 52,
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  // Instruction is FP atomic.
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  FPAtomic = UINT64_C(1) << 53,
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  // Is a MFMA instruction.
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  IsMAI = UINT64_C(1) << 54
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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// The result is true if any of these tests are true.
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enum ClassFlags : unsigned {
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  S_NAN = 1 << 0,        // Signaling NaN
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  Q_NAN = 1 << 1,        // Quiet NaN
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  N_INFINITY = 1 << 2,   // Negative infinity
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  N_NORMAL = 1 << 3,     // Negative normal
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  N_SUBNORMAL = 1 << 4,  // Negative subnormal
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  N_ZERO = 1 << 5,       // Negative zero
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  P_ZERO = 1 << 6,       // Positive zero
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  P_SUBNORMAL = 1 << 7,  // Positive subnormal
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  P_NORMAL = 1 << 8,     // Positive normal
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  P_INFINITY = 1 << 9    // Positive infinity
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};
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}
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namespace AMDGPU {
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  enum OperandType : unsigned {
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    /// Operands with register or 32-bit immediate
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    OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
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    OPERAND_REG_IMM_INT64,
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    OPERAND_REG_IMM_INT16,
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    OPERAND_REG_IMM_FP32,
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    OPERAND_REG_IMM_FP64,
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    OPERAND_REG_IMM_FP16,
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    OPERAND_REG_IMM_V2FP16,
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    OPERAND_REG_IMM_V2INT16,
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    /// Operands with register or inline constant
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    OPERAND_REG_INLINE_C_INT16,
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    OPERAND_REG_INLINE_C_INT32,
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    OPERAND_REG_INLINE_C_INT64,
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    OPERAND_REG_INLINE_C_FP16,
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    OPERAND_REG_INLINE_C_FP32,
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    OPERAND_REG_INLINE_C_FP64,
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    OPERAND_REG_INLINE_C_V2FP16,
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    OPERAND_REG_INLINE_C_V2INT16,
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    /// Operands with an AccVGPR register or inline constant
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    OPERAND_REG_INLINE_AC_INT16,
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    OPERAND_REG_INLINE_AC_INT32,
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    OPERAND_REG_INLINE_AC_FP16,
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    OPERAND_REG_INLINE_AC_FP32,
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    OPERAND_REG_INLINE_AC_V2FP16,
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    OPERAND_REG_INLINE_AC_V2INT16,
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    OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
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    OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16,
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    OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
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    OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16,
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    OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
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    OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16,
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    OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
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    OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
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    // Operand for source modifiers for VOP instructions
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    OPERAND_INPUT_MODS,
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    // Operand for SDWA instructions
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    OPERAND_SDWA_VOPC_DST,
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    /// Operand with 32-bit immediate that uses the constant bus.
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    OPERAND_KIMM32,
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    OPERAND_KIMM16
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  };
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}
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// Input operand modifiers bit-masks
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// NEG and SEXT share same bit-mask because they can't be set simultaneously.
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namespace SISrcMods {
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  enum : unsigned {
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   NEG = 1 << 0,   // Floating-point negate modifier
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   ABS = 1 << 1,   // Floating-point absolute modifier
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   SEXT = 1 << 0,  // Integer sign-extend modifier
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   NEG_HI = ABS,   // Floating-point negate high packed component modifier.
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   OP_SEL_0 = 1 << 2,
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   OP_SEL_1 = 1 << 3,
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   DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
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  };
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}
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namespace SIOutMods {
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  enum : unsigned {
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    NONE = 0,
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    MUL2 = 1,
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    MUL4 = 2,
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    DIV2 = 3
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  };
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}
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namespace AMDGPU {
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namespace VGPRIndexMode {
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enum Id : unsigned { // id of symbolic names
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  ID_SRC0 = 0,
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  ID_SRC1,
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  ID_SRC2,
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  ID_DST,
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  ID_MIN = ID_SRC0,
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  ID_MAX = ID_DST
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};
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enum EncBits : unsigned {
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  OFF = 0,
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  SRC0_ENABLE = 1 << ID_SRC0,
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  SRC1_ENABLE = 1 << ID_SRC1,
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  SRC2_ENABLE = 1 << ID_SRC2,
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  DST_ENABLE = 1 << ID_DST,
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  ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE
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};
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} // namespace VGPRIndexMode
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} // namespace AMDGPU
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namespace AMDGPUAsmVariants {
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  enum : unsigned {
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    DEFAULT = 0,
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    VOP3 = 1,
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    SDWA = 2,
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    SDWA9 = 3,
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    DPP = 4
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  };
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}
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namespace AMDGPU {
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namespace EncValues { // Encoding values of enum9/8/7 operands
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enum : unsigned {
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  SGPR_MIN = 0,
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  SGPR_MAX_SI = 101,
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  SGPR_MAX_GFX10 = 105,
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  TTMP_VI_MIN = 112,
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  TTMP_VI_MAX = 123,
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  TTMP_GFX9_GFX10_MIN = 108,
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  TTMP_GFX9_GFX10_MAX = 123,
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  INLINE_INTEGER_C_MIN = 128,
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  INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
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  INLINE_INTEGER_C_MAX = 208,
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  INLINE_FLOATING_C_MIN = 240,
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  INLINE_FLOATING_C_MAX = 248,
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  LITERAL_CONST = 255,
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  VGPR_MIN = 256,
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  VGPR_MAX = 511
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};
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} // namespace EncValues
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} // namespace AMDGPU
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namespace AMDGPU {
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namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
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enum Id { // Message ID, width(4) [3:0].
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  ID_UNKNOWN_ = -1,
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  ID_INTERRUPT = 1,
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  ID_GS,
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  ID_GS_DONE,
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  ID_GS_ALLOC_REQ = 9,
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  ID_GET_DOORBELL = 10,
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  ID_SYSMSG = 15,
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  ID_GAPS_LAST_, // Indicate that sequence has gaps.
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  ID_GAPS_FIRST_ = ID_INTERRUPT,
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  ID_SHIFT_ = 0,
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  ID_WIDTH_ = 4,
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  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
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};
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enum Op { // Both GS and SYS operation IDs.
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  OP_UNKNOWN_ = -1,
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  OP_SHIFT_ = 4,
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  OP_NONE_ = 0,
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  // Bits used for operation encoding
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  OP_WIDTH_ = 3,
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  OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
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  // GS operations are encoded in bits 5:4
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  OP_GS_NOP = 0,
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  OP_GS_CUT,
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  OP_GS_EMIT,
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  OP_GS_EMIT_CUT,
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  OP_GS_LAST_,
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  OP_GS_FIRST_ = OP_GS_NOP,
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  // SYS operations are encoded in bits 6:4
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  OP_SYS_ECC_ERR_INTERRUPT = 1,
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  OP_SYS_REG_RD,
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  OP_SYS_HOST_TRAP_ACK,
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  OP_SYS_TTRACE_PC,
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  OP_SYS_LAST_,
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  OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
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};
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enum StreamId : unsigned { // Stream ID, (2) [9:8].
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  STREAM_ID_NONE_ = 0,
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  STREAM_ID_DEFAULT_ = 0,
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  STREAM_ID_LAST_ = 4,
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  STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
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  STREAM_ID_SHIFT_ = 8,
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  STREAM_ID_WIDTH_=  2,
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  STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
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};
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} // namespace SendMsg
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namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
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enum Id { // HwRegCode, (6) [5:0]
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  ID_UNKNOWN_ = -1,
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  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
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  ID_MODE = 1,
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  ID_STATUS = 2,
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  ID_TRAPSTS = 3,
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  ID_HW_ID = 4,
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  ID_GPR_ALLOC = 5,
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  ID_LDS_ALLOC = 6,
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  ID_IB_STS = 7,
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  ID_MEM_BASES = 15,
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  ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
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  ID_TBA_LO = 16,
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  ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO,
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  ID_TBA_HI = 17,
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  ID_TMA_LO = 18,
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  ID_TMA_HI = 19,
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  ID_FLAT_SCR_LO = 20,
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  ID_FLAT_SCR_HI = 21,
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  ID_XNACK_MASK = 22,
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  ID_POPS_PACKER = 25,
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  ID_SYMBOLIC_LAST_ = 26,
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  ID_SHIFT_ = 0,
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  ID_WIDTH_ = 6,
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  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
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};
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enum Offset : unsigned { // Offset, (5) [10:6]
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  OFFSET_DEFAULT_ = 0,
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  OFFSET_SHIFT_ = 6,
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  OFFSET_WIDTH_ = 5,
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  OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
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  OFFSET_MEM_VIOL = 8,
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  OFFSET_SRC_SHARED_BASE = 16,
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  OFFSET_SRC_PRIVATE_BASE = 0
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};
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enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
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  WIDTH_M1_DEFAULT_ = 31,
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  WIDTH_M1_SHIFT_ = 11,
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  WIDTH_M1_WIDTH_ = 5,
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  WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
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  WIDTH_M1_SRC_SHARED_BASE = 15,
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  WIDTH_M1_SRC_PRIVATE_BASE = 15
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};
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// Some values from WidthMinusOne mapped into Width domain.
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enum Width : unsigned {
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  WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1,
364
};
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} // namespace Hwreg
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namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
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enum Id : unsigned { // id of symbolic names
371
  ID_QUAD_PERM = 0,
372
  ID_BITMASK_PERM,
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  ID_SWAP,
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  ID_REVERSE,
375
  ID_BROADCAST
376
};
377
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enum EncBits : unsigned {
379
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  // swizzle mode encodings
381
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  QUAD_PERM_ENC         = 0x8000,
383
  QUAD_PERM_ENC_MASK    = 0xFF00,
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  BITMASK_PERM_ENC      = 0x0000,
386
  BITMASK_PERM_ENC_MASK = 0x8000,
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  // QUAD_PERM encodings
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  LANE_MASK             = 0x3,
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  LANE_MAX              = LANE_MASK,
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  LANE_SHIFT            = 2,
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  LANE_NUM              = 4,
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  // BITMASK_PERM encodings
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  BITMASK_MASK          = 0x1F,
398
  BITMASK_MAX           = BITMASK_MASK,
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  BITMASK_WIDTH         = 5,
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  BITMASK_AND_SHIFT     = 0,
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  BITMASK_OR_SHIFT      = 5,
403
  BITMASK_XOR_SHIFT     = 10
404
};
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} // namespace Swizzle
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namespace SDWA {
409
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enum SdwaSel : unsigned {
411
  BYTE_0 = 0,
412
  BYTE_1 = 1,
413
  BYTE_2 = 2,
414
  BYTE_3 = 3,
415
  WORD_0 = 4,
416
  WORD_1 = 5,
417
  DWORD = 6,
418
};
419
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enum DstUnused : unsigned {
421
  UNUSED_PAD = 0,
422
  UNUSED_SEXT = 1,
423
  UNUSED_PRESERVE = 2,
424
};
425
426
enum SDWA9EncValues : unsigned {
427
  SRC_SGPR_MASK = 0x100,
428
  SRC_VGPR_MASK = 0xFF,
429
  VOPC_DST_VCC_MASK = 0x80,
430
  VOPC_DST_SGPR_MASK = 0x7F,
431
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  SRC_VGPR_MIN = 0,
433
  SRC_VGPR_MAX = 255,
434
  SRC_SGPR_MIN = 256,
435
  SRC_SGPR_MAX_SI = 357,
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  SRC_SGPR_MAX_GFX10 = 361,
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  SRC_TTMP_MIN = 364,
438
  SRC_TTMP_MAX = 379,
439
};
440
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} // namespace SDWA
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namespace DPP {
444
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enum DppCtrl : unsigned {
446
  QUAD_PERM_FIRST   = 0,
447
  QUAD_PERM_LAST    = 0xFF,
448
  DPP_UNUSED1       = 0x100,
449
  ROW_SHL0          = 0x100,
450
  ROW_SHL_FIRST     = 0x101,
451
  ROW_SHL_LAST      = 0x10F,
452
  DPP_UNUSED2       = 0x110,
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  ROW_SHR0          = 0x110,
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  ROW_SHR_FIRST     = 0x111,
455
  ROW_SHR_LAST      = 0x11F,
456
  DPP_UNUSED3       = 0x120,
457
  ROW_ROR0          = 0x120,
458
  ROW_ROR_FIRST     = 0x121,
459
  ROW_ROR_LAST      = 0x12F,
460
  WAVE_SHL1         = 0x130,
461
  DPP_UNUSED4_FIRST = 0x131,
462
  DPP_UNUSED4_LAST  = 0x133,
463
  WAVE_ROL1         = 0x134,
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  DPP_UNUSED5_FIRST = 0x135,
465
  DPP_UNUSED5_LAST  = 0x137,
466
  WAVE_SHR1         = 0x138,
467
  DPP_UNUSED6_FIRST = 0x139,
468
  DPP_UNUSED6_LAST  = 0x13B,
469
  WAVE_ROR1         = 0x13C,
470
  DPP_UNUSED7_FIRST = 0x13D,
471
  DPP_UNUSED7_LAST  = 0x13F,
472
  ROW_MIRROR        = 0x140,
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  ROW_HALF_MIRROR   = 0x141,
474
  BCAST15           = 0x142,
475
  BCAST31           = 0x143,
476
  DPP_UNUSED8_FIRST = 0x144,
477
  DPP_UNUSED8_LAST  = 0x14F,
478
  ROW_SHARE_FIRST   = 0x150,
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  ROW_SHARE_LAST    = 0x15F,
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  ROW_XMASK_FIRST   = 0x160,
481
  ROW_XMASK_LAST    = 0x16F,
482
  DPP_LAST          = ROW_XMASK_LAST
483
};
484
485
enum DppFiMode {
486
  DPP_FI_0  = 0,
487
  DPP_FI_1  = 1,
488
  DPP8_FI_0 = 0xE9,
489
  DPP8_FI_1 = 0xEA,
490
};
491
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} // namespace DPP
493
} // namespace AMDGPU
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2.49k
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
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2.49k
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
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2.53k
#define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
498
190
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
499
119
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
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0
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
501
14
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
502
0
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
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#define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
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2.89k
#define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
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2.89k
#define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
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17.6k
#define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
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23.1k
#define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
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#define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
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#define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
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23.1k
#define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
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22.4k
#define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
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#define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
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23.1k
#define   S_00B84C_TRAP_HANDLER(x)                                    (((x) & 0x1) << 6)
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22.4k
#define   G_00B84C_TRAP_HANDLER(x)                                    (((x) >> 6) & 0x1)
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#define   C_00B84C_TRAP_HANDLER                                       0xFFFFFFBF
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23.1k
#define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
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22.4k
#define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
519
#define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
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23.1k
#define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
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22.4k
#define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
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#define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
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23.1k
#define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
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22.4k
#define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
525
#define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
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23.1k
#define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
527
#define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
528
#define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
529
23.1k
#define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
530
22.4k
#define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
531
#define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
532
/* CIK */
533
23.1k
#define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
534
#define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
535
#define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
536
/*     */
537
23.1k
#define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
538
#define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
539
#define   C_00B84C_LDS_SIZE                                           0xFF007FFF
540
23.1k
#define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
541
#define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
542
#define   C_00B84C_EXCP_EN
543
544
2.49k
#define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
545
2.49k
#define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
546
547
35.2k
#define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
548
23.1k
#define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
549
#define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
550
#define   C_00B848_VGPRS                                              0xFFFFFFC0
551
23.1k
#define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
552
#define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
553
#define   C_00B848_SGPRS                                              0xFFFFFC3F
554
23.1k
#define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
555
#define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
556
#define   C_00B848_PRIORITY                                           0xFFFFF3FF
557
23.1k
#define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
558
#define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
559
#define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
560
23.1k
#define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
561
#define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
562
#define   C_00B848_PRIV                                               0xFFEFFFFF
563
23.1k
#define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
564
#define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
565
#define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
566
23.1k
#define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
567
#define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
568
#define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
569
23.1k
#define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
570
#define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
571
#define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
572
23.2k
#define   S_00B848_WGP_MODE(x)                                        (((
x58
) & 0x1) << 29)
573
4
#define   G_00B848_WGP_MODE(x)                                        (((x) >> 29) & 0x1)
574
#define   C_00B848_WGP_MODE                                           0xDFFFFFFF
575
23.2k
#define   S_00B848_MEM_ORDERED(x)                                     (((x) & 0x1) << 30)
576
4
#define   G_00B848_MEM_ORDERED(x)                                     (((x) >> 30) & 0x1)
577
#define   C_00B848_MEM_ORDERED                                        0xBFFFFFFF
578
#define   S_00B848_FWD_PROGRESS(x)                                    (((x) & 0x1) << 31)
579
4
#define   G_00B848_FWD_PROGRESS(x)                                    (((x) >> 31) & 0x1)
580
#define   C_00B848_FWD_PROGRESS                                       0x7FFFFFFF
581
582
583
// Helpers for setting FLOAT_MODE
584
#define FP_ROUND_ROUND_TO_NEAREST 0
585
#define FP_ROUND_ROUND_TO_INF 1
586
#define FP_ROUND_ROUND_TO_NEGINF 2
587
#define FP_ROUND_ROUND_TO_ZERO 3
588
589
// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
590
// precision.
591
23.1k
#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
592
23.2k
#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
593
594
69.5k
#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
595
#define FP_DENORM_FLUSH_OUT 1
596
#define FP_DENORM_FLUSH_IN 2
597
23.2k
#define FP_DENORM_FLUSH_NONE 3
598
599
600
// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
601
// precision.
602
23.1k
#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
603
23.1k
#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
604
605
17.6k
#define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
606
17.6k
#define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
607
608
2.82k
#define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
609
2.82k
#define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
610
611
#define R_028B54_VGT_SHADER_STAGES_EN                                 0x028B54
612
2
#define   S_028B54_HS_W32_EN(x)                                       (((x) & 0x1) << 21)
613
2
#define   S_028B54_GS_W32_EN(x)                                       (((x) & 0x1) << 22)
614
1
#define   S_028B54_VS_W32_EN(x)                                       (((x) & 0x1) << 23)
615
#define R_0286D8_SPI_PS_IN_CONTROL                                    0x0286D8
616
0
#define   S_0286D8_PS_W32_EN(x)                                       (((x) & 0x1) << 15)
617
#define R_00B800_COMPUTE_DISPATCH_INITIATOR                           0x00B800
618
1
#define   S_00B800_CS_W32_EN(x)                                       (((x) & 0x1) << 15)
619
620
20.4k
#define R_SPILLED_SGPRS         0x4
621
20.4k
#define R_SPILLED_VGPRS         0x8
622
} // End namespace llvm
623
624
#endif