Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "SIMachineFunctionInfo.h"
10
#include "AMDGPUArgumentUsageInfo.h"
11
#include "AMDGPUSubtarget.h"
12
#include "SIRegisterInfo.h"
13
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
14
#include "Utils/AMDGPUBaseInfo.h"
15
#include "llvm/ADT/Optional.h"
16
#include "llvm/CodeGen/MachineBasicBlock.h"
17
#include "llvm/CodeGen/MachineFrameInfo.h"
18
#include "llvm/CodeGen/MachineFunction.h"
19
#include "llvm/CodeGen/MachineRegisterInfo.h"
20
#include "llvm/IR/CallingConv.h"
21
#include "llvm/IR/Function.h"
22
#include <cassert>
23
#include <vector>
24
25
#define MAX_LANES 64
26
27
using namespace llvm;
28
29
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
30
  : AMDGPUMachineFunction(MF),
31
    Mode(MF.getFunction()),
32
    PrivateSegmentBuffer(false),
33
    DispatchPtr(false),
34
    QueuePtr(false),
35
    KernargSegmentPtr(false),
36
    DispatchID(false),
37
    FlatScratchInit(false),
38
    WorkGroupIDX(false),
39
    WorkGroupIDY(false),
40
    WorkGroupIDZ(false),
41
    WorkGroupInfo(false),
42
    PrivateSegmentWaveByteOffset(false),
43
    WorkItemIDX(false),
44
    WorkItemIDY(false),
45
    WorkItemIDZ(false),
46
    ImplicitBufferPtr(false),
47
    ImplicitArgPtr(false),
48
    GITPtrHigh(0xffffffff),
49
    HighBitsOf32BitAddress(0),
50
31.2k
    GDSSize(0) {
51
31.2k
  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
52
31.2k
  const Function &F = MF.getFunction();
53
31.2k
  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
54
31.2k
  WavesPerEU = ST.getWavesPerEU(F);
55
31.2k
56
31.2k
  Occupancy = getMaxWavesPerEU();
57
31.2k
  limitOccupancy(MF);
58
31.2k
  CallingConv::ID CC = F.getCallingConv();
59
31.2k
60
31.2k
  if (CC == CallingConv::AMDGPU_KERNEL || 
CC == CallingConv::SPIR_KERNEL10.7k
) {
61
20.5k
    if (!F.arg_empty())
62
18.5k
      KernargSegmentPtr = true;
63
20.5k
    WorkGroupIDX = true;
64
20.5k
    WorkItemIDX = true;
65
20.5k
  } else 
if (10.7k
CC == CallingConv::AMDGPU_PS10.7k
) {
66
2.54k
    PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
67
2.54k
  }
68
31.2k
69
31.2k
  if (!isEntryFunction()) {
70
7.72k
    // Non-entry functions have no special inputs for now, other registers
71
7.72k
    // required for scratch access.
72
7.72k
    ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
73
7.72k
    ScratchWaveOffsetReg = AMDGPU::SGPR33;
74
7.72k
75
7.72k
    // TODO: Pick a high register, and shift down, similar to a kernel.
76
7.72k
    FrameOffsetReg = AMDGPU::SGPR34;
77
7.72k
    StackPtrOffsetReg = AMDGPU::SGPR32;
78
7.72k
79
7.72k
    ArgInfo.PrivateSegmentBuffer =
80
7.72k
      ArgDescriptor::createRegister(ScratchRSrcReg);
81
7.72k
    ArgInfo.PrivateSegmentWaveByteOffset =
82
7.72k
      ArgDescriptor::createRegister(ScratchWaveOffsetReg);
83
7.72k
84
7.72k
    if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
85
12
      ImplicitArgPtr = true;
86
23.5k
  } else {
87
23.5k
    if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
88
57
      KernargSegmentPtr = true;
89
57
      MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
90
57
                                 MaxKernArgAlign);
91
57
    }
92
23.5k
  }
93
31.2k
94
31.2k
  if (F.hasFnAttribute("amdgpu-work-group-id-x"))
95
34
    WorkGroupIDX = true;
96
31.2k
97
31.2k
  if (F.hasFnAttribute("amdgpu-work-group-id-y"))
98
50
    WorkGroupIDY = true;
99
31.2k
100
31.2k
  if (F.hasFnAttribute("amdgpu-work-group-id-z"))
101
48
    WorkGroupIDZ = true;
102
31.2k
103
31.2k
  if (F.hasFnAttribute("amdgpu-work-item-id-x"))
104
35
    WorkItemIDX = true;
105
31.2k
106
31.2k
  if (F.hasFnAttribute("amdgpu-work-item-id-y"))
107
166
    WorkItemIDY = true;
108
31.2k
109
31.2k
  if (F.hasFnAttribute("amdgpu-work-item-id-z"))
110
93
    WorkItemIDZ = true;
111
31.2k
112
31.2k
  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
113
31.2k
  bool HasStackObjects = FrameInfo.hasStackObjects();
114
31.2k
115
31.2k
  if (isEntryFunction()) {
116
23.5k
    // X, XY, and XYZ are the only supported combinations, so make sure Y is
117
23.5k
    // enabled if Z is.
118
23.5k
    if (WorkItemIDZ)
119
85
      WorkItemIDY = true;
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23.5k
121
23.5k
    PrivateSegmentWaveByteOffset = true;
122
23.5k
123
23.5k
    // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
124
23.5k
    if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
125
23.5k
        
(6.38k
CC == CallingConv::AMDGPU_HS6.38k
||
CC == CallingConv::AMDGPU_GS6.36k
))
126
73
      ArgInfo.PrivateSegmentWaveByteOffset =
127
73
          ArgDescriptor::createRegister(AMDGPU::SGPR5);
128
23.5k
  }
129
31.2k
130
31.2k
  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
131
31.2k
  if (isAmdHsaOrMesa) {
132
7.13k
    PrivateSegmentBuffer = true;
133
7.13k
134
7.13k
    if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
135
51
      DispatchPtr = true;
136
7.13k
137
7.13k
    if (F.hasFnAttribute("amdgpu-queue-ptr"))
138
73
      QueuePtr = true;
139
7.13k
140
7.13k
    if (F.hasFnAttribute("amdgpu-dispatch-id"))
141
16
      DispatchID = true;
142
24.1k
  } else if (ST.isMesaGfxShader(F)) {
143
176
    ImplicitBufferPtr = true;
144
176
  }
145
31.2k
146
31.2k
  if (F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
147
36
    KernargSegmentPtr = true;
148
31.2k
149
31.2k
  if (ST.hasFlatAddressSpace() && 
isEntryFunction()23.4k
&&
isAmdHsaOrMesa17.1k
) {
150
4.43k
    auto hasNonSpillStackObjects = [&]() {
151
4.43k
      // Avoid expensive checking if there's no stack objects.
152
4.43k
      if (!HasStackObjects)
153
4.28k
        return false;
154
148
      for (auto OI = FrameInfo.getObjectIndexBegin(),
155
150
                OE = FrameInfo.getObjectIndexEnd(); OI != OE; 
++OI2
)
156
148
        if (!FrameInfo.isSpillSlotObjectIndex(OI))
157
146
          return true;
158
148
      // All stack objects are spill slots.
159
148
      
return false2
;
160
148
    };
161
4.43k
    // TODO: This could be refined a lot. The attribute is a poor way of
162
4.43k
    // detecting calls that may require it before argument lowering.
163
4.43k
    if (hasNonSpillStackObjects() || 
F.hasFnAttribute("amdgpu-flat-scratch")4.28k
)
164
432
      FlatScratchInit = true;
165
4.43k
  }
166
31.2k
167
31.2k
  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
168
31.2k
  StringRef S = A.getValueAsString();
169
31.2k
  if (!S.empty())
170
4
    S.consumeInteger(0, GITPtrHigh);
171
31.2k
172
31.2k
  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
173
31.2k
  S = A.getValueAsString();
174
31.2k
  if (!S.empty())
175
16
    S.consumeInteger(0, HighBitsOf32BitAddress);
176
31.2k
177
31.2k
  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
178
31.2k
  if (!S.empty())
179
48
    S.consumeInteger(0, GDSSize);
180
31.2k
}
181
182
83.1k
void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
183
83.1k
  limitOccupancy(getMaxWavesPerEU());
184
83.1k
  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
185
83.1k
  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
186
83.1k
                 MF.getFunction()));
187
83.1k
}
188
189
unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
190
4.55k
  const SIRegisterInfo &TRI) {
191
4.55k
  ArgInfo.PrivateSegmentBuffer =
192
4.55k
    ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
193
4.55k
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
194
4.55k
  NumUserSGPRs += 4;
195
4.55k
  return ArgInfo.PrivateSegmentBuffer.getRegister();
196
4.55k
}
197
198
40
unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
199
40
  ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
200
40
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
201
40
  NumUserSGPRs += 2;
202
40
  return ArgInfo.DispatchPtr.getRegister();
203
40
}
204
205
60
unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
206
60
  ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
207
60
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
208
60
  NumUserSGPRs += 2;
209
60
  return ArgInfo.QueuePtr.getRegister();
210
60
}
211
212
18.4k
unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
213
18.4k
  ArgInfo.KernargSegmentPtr
214
18.4k
    = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
215
18.4k
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
216
18.4k
  NumUserSGPRs += 2;
217
18.4k
  return ArgInfo.KernargSegmentPtr.getRegister();
218
18.4k
}
219
220
6
unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
221
6
  ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
222
6
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
223
6
  NumUserSGPRs += 2;
224
6
  return ArgInfo.DispatchID.getRegister();
225
6
}
226
227
431
unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
228
431
  ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
229
431
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
230
431
  NumUserSGPRs += 2;
231
431
  return ArgInfo.FlatScratchInit.getRegister();
232
431
}
233
234
175
unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
235
175
  ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
236
175
    getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
237
175
  NumUserSGPRs += 2;
238
175
  return ArgInfo.ImplicitBufferPtr.getRegister();
239
175
}
240
241
143
static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
242
7.62k
  for (unsigned I = 0; CSRegs[I]; 
++I7.48k
) {
243
7.60k
    if (CSRegs[I] == Reg)
244
116
      return true;
245
7.60k
  }
246
143
247
143
  
return false27
;
248
143
}
249
250
/// \p returns true if \p NumLanes slots are available in VGPRs already used for
251
/// SGPR spilling.
252
//
253
// FIXME: This only works after processFunctionBeforeFrameFinalized
254
bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
255
140
                                                      unsigned NumNeed) const {
256
140
  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
257
140
  unsigned WaveSize = ST.getWavefrontSize();
258
140
  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
259
140
}
260
261
/// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
262
bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
263
1.77k
                                                    int FI) {
264
1.77k
  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
265
1.77k
266
1.77k
  // This has already been allocated.
267
1.77k
  if (!SpillLanes.empty())
268
859
    return true;
269
916
270
916
  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
271
916
  const SIRegisterInfo *TRI = ST.getRegisterInfo();
272
916
  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
273
916
  MachineRegisterInfo &MRI = MF.getRegInfo();
274
916
  unsigned WaveSize = ST.getWavefrontSize();
275
916
276
916
  unsigned Size = FrameInfo.getObjectSize(FI);
277
916
  assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
278
916
  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
279
916
280
916
  int NumLanes = Size / 4;
281
916
282
916
  const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
283
916
284
916
  // Make sure to handle the case where a wide SGPR spill may span between two
285
916
  // VGPRs.
286
2.55k
  for (int I = 0; I < NumLanes; 
++I, ++NumVGPRSpillLanes1.63k
) {
287
1.64k
    unsigned LaneVGPR;
288
1.64k
    unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
289
1.64k
290
1.64k
    if (VGPRIndex == 0) {
291
206
      LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
292
206
      if (LaneVGPR == AMDGPU::NoRegister) {
293
4
        // We have no VGPRs left for spilling SGPRs. Reset because we will not
294
4
        // partially spill the SGPR to VGPRs.
295
4
        SGPRToVGPRSpills.erase(FI);
296
4
        NumVGPRSpillLanes -= I;
297
4
        return false;
298
4
      }
299
202
300
202
      Optional<int> CSRSpillFI;
301
202
      if ((FrameInfo.hasCalls() || 
!isEntryFunction()90
) &&
CSRegs143
&&
302
202
          
isCalleeSavedReg(CSRegs, LaneVGPR)143
) {
303
116
        CSRSpillFI = FrameInfo.CreateSpillStackObject(4, 4);
304
116
      }
305
202
306
202
      SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
307
202
308
202
      // Add this register as live-in to all blocks to avoid machine verifer
309
202
      // complaining about use of an undefined physical register.
310
202
      for (MachineBasicBlock &BB : MF)
311
442
        BB.addLiveIn(LaneVGPR);
312
1.43k
    } else {
313
1.43k
      LaneVGPR = SpillVGPRs.back().VGPR;
314
1.43k
    }
315
1.64k
316
1.64k
    SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
317
1.63k
  }
318
916
319
916
  
return true912
;
320
916
}
321
322
/// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
323
/// Either AGPR is spilled to VGPR to vice versa.
324
/// Returns true if a \p FI can be eliminated completely.
325
bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
326
                                                    int FI,
327
91
                                                    bool isAGPRtoVGPR) {
328
91
  MachineRegisterInfo &MRI = MF.getRegInfo();
329
91
  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
330
91
  const GCNSubtarget &ST =  MF.getSubtarget<GCNSubtarget>();
331
91
332
91
  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
333
91
334
91
  auto &Spill = VGPRToAGPRSpills[FI];
335
91
336
91
  // This has already been allocated.
337
91
  if (!Spill.Lanes.empty())
338
48
    return Spill.FullyAllocated;
339
43
340
43
  unsigned Size = FrameInfo.getObjectSize(FI);
341
43
  unsigned NumLanes = Size / 4;
342
43
  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
343
43
344
43
  const TargetRegisterClass &RC =
345
43
      isAGPRtoVGPR ? 
AMDGPU::VGPR_32RegClass7
:
AMDGPU::AGPR_32RegClass36
;
346
43
  auto Regs = RC.getRegisters();
347
43
348
43
  auto &SpillRegs = isAGPRtoVGPR ? 
SpillAGPR7
:
SpillVGPR36
;
349
43
  const SIRegisterInfo *TRI = ST.getRegisterInfo();
350
43
  Spill.FullyAllocated = true;
351
43
352
43
  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
353
43
  // once.
354
43
  BitVector OtherUsedRegs;
355
43
  OtherUsedRegs.resize(TRI->getNumRegs());
356
43
357
43
  const uint32_t *CSRMask =
358
43
      TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
359
43
  if (CSRMask)
360
0
    OtherUsedRegs.setBitsInMask(CSRMask);
361
43
362
43
  // TODO: Should include register tuples, but doesn't matter with current
363
43
  // usage.
364
43
  for (MCPhysReg Reg : SpillAGPR)
365
10
    OtherUsedRegs.set(Reg);
366
43
  for (MCPhysReg Reg : SpillVGPR)
367
1.40k
    OtherUsedRegs.set(Reg);
368
43
369
43
  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
370
387
  for (unsigned I = 0; I < NumLanes; 
++I344
) {
371
352
    NextSpillReg = std::find_if(
372
3.52k
        NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
373
3.52k
          return MRI.isAllocatable(Reg) && 
!MRI.isPhysRegUsed(Reg)1.80k
&&
374
3.52k
                 
!OtherUsedRegs[Reg]351
;
375
3.52k
        });
376
352
377
352
    if (NextSpillReg == Regs.end()) { // Registers exhausted
378
8
      Spill.FullyAllocated = false;
379
8
      break;
380
8
    }
381
344
382
344
    OtherUsedRegs.set(*NextSpillReg);
383
344
    SpillRegs.push_back(*NextSpillReg);
384
344
    Spill.Lanes[I] = *NextSpillReg++;
385
344
  }
386
43
387
43
  return Spill.FullyAllocated;
388
43
}
389
390
25.4k
void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
391
25.4k
  // The FP spill hasn't been inserted yet, so keep it around.
392
25.4k
  for (auto &R : SGPRToVGPRSpills) {
393
905
    if (R.first != FramePointerSaveIndex)
394
787
      MFI.RemoveStackObject(R.first);
395
905
  }
396
25.4k
397
25.4k
  // All other SPGRs must be allocated on the default stack, so reset the stack
398
25.4k
  // ID.
399
29.1k
  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
400
25.4k
       
++i3.68k
)
401
3.68k
    if (i != FramePointerSaveIndex)
402
3.56k
      MFI.setStackID(i, TargetStackID::Default);
403
25.4k
404
25.4k
  for (auto &R : VGPRToAGPRSpills) {
405
43
    if (R.second.FullyAllocated)
406
35
      MFI.RemoveStackObject(R.first);
407
43
  }
408
25.4k
}
409
410
23.7k
MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
411
23.7k
  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
412
23.7k
  return AMDGPU::SGPR0 + NumUserSGPRs;
413
23.7k
}
414
415
40.7k
MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
416
40.7k
  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
417
40.7k
}
418
419
static yaml::StringValue regToString(unsigned Reg,
420
23.2k
                                     const TargetRegisterInfo &TRI) {
421
23.2k
  yaml::StringValue Dest;
422
23.2k
  {
423
23.2k
    raw_string_ostream OS(Dest.Value);
424
23.2k
    OS << printReg(Reg, &TRI);
425
23.2k
  }
426
23.2k
  return Dest;
427
23.2k
}
428
429
static Optional<yaml::SIArgumentInfo>
430
convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
431
5.80k
                    const TargetRegisterInfo &TRI) {
432
5.80k
  yaml::SIArgumentInfo AI;
433
5.80k
434
5.80k
  auto convertArg = [&](Optional<yaml::SIArgument> &A,
435
98.7k
                        const ArgDescriptor &Arg) {
436
98.7k
    if (!Arg)
437
87.0k
      return false;
438
11.6k
439
11.6k
    // Create a register or stack argument.
440
11.6k
    yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
441
11.6k
    if (Arg.isRegister()) {
442
11.6k
      raw_string_ostream OS(SA.RegisterName.Value);
443
11.6k
      OS << printReg(Arg.getRegister(), &TRI);
444
11.6k
    } else
445
2
      SA.StackOffset = Arg.getStackOffset();
446
11.6k
    // Check and update the optional mask.
447
11.6k
    if (Arg.isMasked())
448
2
      SA.Mask = Arg.getMask();
449
11.6k
450
11.6k
    A = SA;
451
11.6k
    return true;
452
11.6k
  };
453
5.80k
454
5.80k
  bool Any = false;
455
5.80k
  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
456
5.80k
  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
457
5.80k
  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
458
5.80k
  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
459
5.80k
  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
460
5.80k
  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
461
5.80k
  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
462
5.80k
  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
463
5.80k
  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
464
5.80k
  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
465
5.80k
  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
466
5.80k
  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
467
5.80k
                    ArgInfo.PrivateSegmentWaveByteOffset);
468
5.80k
  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
469
5.80k
  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
470
5.80k
  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
471
5.80k
  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
472
5.80k
  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
473
5.80k
474
5.80k
  if (Any)
475
5.61k
    return AI;
476
194
477
194
  return None;
478
194
}
479
480
yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
481
  const llvm::SIMachineFunctionInfo& MFI,
482
  const TargetRegisterInfo &TRI)
483
  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
484
    MaxKernArgAlign(MFI.getMaxKernArgAlign()),
485
    LDSSize(MFI.getLDSSize()),
486
    IsEntryFunction(MFI.isEntryFunction()),
487
    NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
488
    MemoryBound(MFI.isMemoryBound()),
489
    WaveLimiter(MFI.needsWaveLimiter()),
490
    ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
491
    ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
492
    FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
493
    StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
494
    ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
495
5.80k
    Mode(MFI.getMode()) {}
496
497
6.00k
void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
498
6.00k
  MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
499
6.00k
}
500
501
bool SIMachineFunctionInfo::initializeBaseYamlFields(
502
5.60k
  const yaml::SIMachineFunctionInfo &YamlMFI) {
503
5.60k
  ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
504
5.60k
  MaxKernArgAlign = YamlMFI.MaxKernArgAlign;
505
5.60k
  LDSSize = YamlMFI.LDSSize;
506
5.60k
  IsEntryFunction = YamlMFI.IsEntryFunction;
507
5.60k
  NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
508
5.60k
  MemoryBound = YamlMFI.MemoryBound;
509
5.60k
  WaveLimiter = YamlMFI.WaveLimiter;
510
5.60k
  return false;
511
5.60k
}