Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition for SIRegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
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#include "AMDGPURegisterInfo.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class GCNSubtarget;
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class LiveIntervals;
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class MachineRegisterInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo final : public AMDGPURegisterInfo {
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private:
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  unsigned SGPRSetID;
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  unsigned VGPRSetID;
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  unsigned AGPRSetID;
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  BitVector SGPRPressureSets;
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  BitVector VGPRPressureSets;
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  BitVector AGPRPressureSets;
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  bool SpillSGPRToVGPR;
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  bool SpillSGPRToSMEM;
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  bool isWave32;
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  void classifyPressureSet(unsigned PSetID, unsigned Reg,
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                           BitVector &PressureSets) const;
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public:
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  SIRegisterInfo(const GCNSubtarget &ST);
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2.75k
  bool spillSGPRToVGPR() const {
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    return SpillSGPRToVGPR;
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2.75k
  }
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1.75k
  bool spillSGPRToSMEM() const {
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    return SpillSGPRToSMEM;
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  }
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  /// Return the end register initially reserved for the scratch buffer in case
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  /// spilling is needed.
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  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
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  /// Return the end register initially reserved for the scratch wave offset in
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  /// case spilling is needed.
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  unsigned reservedPrivateSegmentWaveByteOffsetReg(
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    const MachineFunction &MF) const;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
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  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID) const override;
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  // Stack access is very expensive. CSRs are also the high registers, and we
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  // want to minimize the number of used registers.
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  unsigned getCSRFirstUseCost() const override {
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    return 100;
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  }
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  Register getFrameRegister(const MachineFunction &MF) const override;
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  bool canRealignStack(const MachineFunction &MF) const override;
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  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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  bool requiresFrameIndexReplacementScavenging(
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    const MachineFunction &MF) const override;
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  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
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  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
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  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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                                   int Idx) const override;
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  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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                                    unsigned BaseReg, int FrameIdx,
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                                    int64_t Offset) const override;
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  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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                         int64_t Offset) const override;
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  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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                          int64_t Offset) const override;
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  const TargetRegisterClass *getPointerRegClass(
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    const MachineFunction &MF, unsigned Kind = 0) const override;
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  /// If \p OnlyToVGPR is true, this will only succeed if this
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  bool spillSGPR(MachineBasicBlock::iterator MI,
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                 int FI, RegScavenger *RS,
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                 bool OnlyToVGPR = false) const;
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  bool restoreSGPR(MachineBasicBlock::iterator MI,
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                   int FI, RegScavenger *RS,
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                   bool OnlyToVGPR = false) const;
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  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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                           unsigned FIOperandNum,
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                           RegScavenger *RS) const override;
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  bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
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                                          int FI, RegScavenger *RS) const;
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  StringRef getRegAsmName(unsigned Reg) const override;
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  unsigned getHWRegIndex(unsigned Reg) const {
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    return getEncodingValue(Reg) & 0xff;
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  }
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  /// Return the 'base' register class for this register.
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  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
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  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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  /// \returns true if this class contains only SGPR registers
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  bool isSGPRClass(const TargetRegisterClass *RC) const {
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    return !hasVGPRs(RC) && 
!hasAGPRs(RC)4.27M
;
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  }
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  /// \returns true if this class ID contains only SGPR registers
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  bool isSGPRClassID(unsigned RCID) const {
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    return isSGPRClass(getRegClass(RCID));
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  }
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  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
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    const TargetRegisterClass *RC;
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    if (TargetRegisterInfo::isVirtualRegister(Reg))
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      RC = MRI.getRegClass(Reg);
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    else
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      RC = getPhysRegClass(Reg);
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    return isSGPRClass(RC);
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  }
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  /// \returns true if this class contains VGPR registers.
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  bool hasVGPRs(const TargetRegisterClass *RC) const;
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  /// \returns true if this class contains AGPR registers.
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  bool hasAGPRs(const TargetRegisterClass *RC) const;
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  /// \returns true if this class contains any vector registers.
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  bool hasVectorRegisters(const TargetRegisterClass *RC) const {
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    return hasVGPRs(RC) || 
hasAGPRs(RC)560k
;
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  }
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  /// \returns A VGPR reg class with the same width as \p SRC
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  const TargetRegisterClass *getEquivalentVGPRClass(
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                                          const TargetRegisterClass *SRC) const;
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  /// \returns An AGPR reg class with the same width as \p SRC
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  const TargetRegisterClass *getEquivalentAGPRClass(
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                                          const TargetRegisterClass *SRC) const;
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  /// \returns A SGPR reg class with the same width as \p SRC
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  const TargetRegisterClass *getEquivalentSGPRClass(
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                                           const TargetRegisterClass *VRC) const;
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  /// \returns The register class that is used for a sub-register of \p RC for
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  /// the given \p SubIdx.  If \p SubIdx equals NoSubRegister, \p RC will
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  /// be returned.
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  const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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                                            unsigned SubIdx) const;
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  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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                            unsigned DefSubReg,
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                            const TargetRegisterClass *SrcRC,
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                            unsigned SrcSubReg) const override;
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  /// \returns True if operands defined with this operand type can accept
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  /// a literal constant (i.e. any 32-bit immediate).
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  bool opCanUseLiteralConstant(unsigned OpType) const {
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    // TODO: 64-bit operands have extending behavior from 32-bit literal.
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    return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
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OpType <= AMDGPU::OPERAND_REG_IMM_LAST5.62k
;
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  }
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  /// \returns True if operands defined with this operand type can accept
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  /// an inline constant. i.e. An integer value in the range (-16, 64) or
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  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
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  bool opCanUseInlineConstant(unsigned OpType) const {
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    return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
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           OpType <= AMDGPU::OPERAND_SRC_LAST;
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  }
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  unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
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                              const TargetRegisterClass *RC,
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                              const MachineFunction &MF) const;
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  unsigned getSGPRPressureSet() const { return SGPRSetID; };
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  unsigned getVGPRPressureSet() const { return VGPRSetID; };
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  unsigned getAGPRPressureSet() const { return AGPRSetID; };
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  const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
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                                               unsigned Reg) const;
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  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
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  bool isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
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  bool isVectorRegister(const MachineRegisterInfo &MRI, unsigned Reg) const {
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    return isVGPR(MRI, Reg) || 
isAGPR(MRI, Reg)56.9k
;
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  }
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  virtual bool
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  isDivergentRegClass(const TargetRegisterClass *RC) const override {
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    return !isSGPRClass(RC);
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  }
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  bool isSGPRPressureSet(unsigned SetID) const {
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    return SGPRPressureSets.test(SetID) && 
!VGPRPressureSets.test(SetID)509k
&&
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!AGPRPressureSets.test(SetID)509k
;
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  }
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  bool isVGPRPressureSet(unsigned SetID) const {
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    return VGPRPressureSets.test(SetID) && 
!SGPRPressureSets.test(SetID)3.64k
&&
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!AGPRPressureSets.test(SetID)3.64k
;
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  }
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  bool isAGPRPressureSet(unsigned SetID) const {
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    return AGPRPressureSets.test(SetID) && 
!SGPRPressureSets.test(SetID)3.64k
&&
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!VGPRPressureSets.test(SetID)3.64k
;
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  }
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  ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
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                                     unsigned EltSize) const;
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  bool shouldCoalesce(MachineInstr *MI,
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                      const TargetRegisterClass *SrcRC,
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                      unsigned SubReg,
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                      const TargetRegisterClass *DstRC,
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                      unsigned DstSubReg,
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                      const TargetRegisterClass *NewRC,
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                      LiveIntervals &LIS) const override;
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  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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                               MachineFunction &MF) const override;
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  unsigned getRegPressureSetLimit(const MachineFunction &MF,
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                                  unsigned Idx) const override;
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  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
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  unsigned getReturnAddressReg(const MachineFunction &MF) const;
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  const TargetRegisterClass *
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  getRegClassForSizeOnBank(unsigned Size,
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                           const RegisterBank &Bank,
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                           const MachineRegisterInfo &MRI) const;
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  const TargetRegisterClass *
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  getRegClassForTypeOnBank(LLT Ty,
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                           const RegisterBank &Bank,
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                           const MachineRegisterInfo &MRI) const {
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    return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
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  }
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  const TargetRegisterClass *
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  getConstrainedRegClassForOperand(const MachineOperand &MO,
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                                 const MachineRegisterInfo &MRI) const override;
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  const TargetRegisterClass *getBoolRC() const {
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    return isWave32 ? 
&AMDGPU::SReg_32_XM0RegClass81.2k
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                    : 
&AMDGPU::SReg_64RegClass1.17M
;
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  }
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  const TargetRegisterClass *getWaveMaskRegClass() const {
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    return isWave32 ? 
&AMDGPU::SReg_32_XM0_XEXECRegClass46
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                    : 
&AMDGPU::SReg_64_XEXECRegClass327
;
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  }
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  unsigned getVCC() const;
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  const TargetRegisterClass *getRegClass(unsigned RCID) const;
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  // Find reaching register definition
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  MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
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                                MachineInstr &Use,
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                                MachineRegisterInfo &MRI,
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                                LiveIntervals *LIS) const;
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  const uint32_t *getAllVGPRRegMask() const;
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  const uint32_t *getAllAllocatableSRegMask() const;
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private:
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  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
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                           unsigned LoadStoreOp,
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                           int Index,
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                           unsigned ValueReg,
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                           bool ValueIsKill,
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                           unsigned ScratchRsrcReg,
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                           unsigned ScratchOffsetReg,
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                           int64_t InstrOffset,
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                           MachineMemOperand *MMO,
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                           RegScavenger *RS) const;
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};
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} // End namespace llvm
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#endif