Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
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//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata  -===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
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/// the PAL metadata.
13
//
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//===----------------------------------------------------------------------===//
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//
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#include "AMDGPUPALMetadata.h"
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#include "AMDGPU.h"
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#include "AMDGPUAsmPrinter.h"
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#include "MCTargetDesc/AMDGPUTargetStreamer.h"
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#include "SIDefines.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Support/AMDGPUMetadata.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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using namespace llvm::AMDGPU;
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// Read the PAL metadata from IR metadata, where it was put by the frontend.
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86
void AMDGPUPALMetadata::readFromIR(Module &M) {
32
86
  auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata.msgpack");
33
86
  if (NamedMD && 
NamedMD->getNumOperands()22
) {
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22
    // This is the new msgpack format for metadata. It is a NamedMD containing
35
22
    // an MDTuple containing an MDString containing the msgpack data.
36
22
    BlobType = ELF::NT_AMDGPU_METADATA;
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22
    auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
38
22
    if (MDN && MDN->getNumOperands()) {
39
22
      if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
40
22
        setFromMsgPackBlob(MDS->getString());
41
22
    }
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22
    return;
43
22
  }
44
64
  BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
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64
  NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
46
64
  if (!NamedMD || 
!NamedMD->getNumOperands()4
)
47
60
    return;
48
4
  // This is the old reg=value pair format for metadata. It is a NamedMD
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4
  // containing an MDTuple containing a number of MDNodes each of which is an
50
4
  // integer value, and each two integer values forms a key=value pair that we
51
4
  // store as Registers[key]=value in the map.
52
4
  auto Tuple = dyn_cast<MDTuple>(NamedMD->getOperand(0));
53
4
  if (!Tuple)
54
0
    return;
55
65
  
for (unsigned I = 0, E = Tuple->getNumOperands() & -2; 4
I != E;
I += 261
) {
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61
    auto Key = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I));
57
61
    auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
58
61
    if (!Key || !Val)
59
0
      continue;
60
61
    setRegister(Key->getZExtValue(), Val->getZExtValue());
61
61
  }
62
4
}
63
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// Set PAL metadata from a binary blob from the applicable .note record.
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// Returns false if bad format.  Blob must remain valid for the lifetime of the
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// Metadata.
67
0
bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
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0
  BlobType = Type;
69
0
  if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
70
0
    return setFromLegacyBlob(Blob);
71
0
  return setFromMsgPackBlob(Blob);
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0
}
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// Set PAL metadata from legacy (array of key=value pairs) blob.
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0
bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
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0
  auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
77
0
  for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
78
0
    setRegister(Data[I * 2], Data[I * 2 + 1]);
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0
  return true;
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0
}
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// Set PAL metadata from msgpack blob.
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22
bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
84
22
  msgpack::Reader Reader(Blob);
85
22
  return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
86
22
}
87
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// Given the calling convention, calculate the register number for rsrc1. In
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// principle the register number could change in future hardware, but we know
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// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
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// we can use fixed values.
92
748
static unsigned getRsrc1Reg(CallingConv::ID CC) {
93
748
  switch (CC) {
94
748
  default:
95
640
    return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
96
748
  case CallingConv::AMDGPU_LS:
97
5
    return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
98
748
  case CallingConv::AMDGPU_HS:
99
12
    return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
100
748
  case CallingConv::AMDGPU_ES:
101
5
    return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
102
748
  case CallingConv::AMDGPU_GS:
103
9
    return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
104
748
  case CallingConv::AMDGPU_VS:
105
11
    return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
106
748
  case CallingConv::AMDGPU_PS:
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66
    return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
108
748
  }
109
748
}
110
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// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
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// with a constant offset to access any non-register shader-specific PAL
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// metadata key.
114
1.11k
static unsigned getScratchSizeKey(CallingConv::ID CC) {
115
1.11k
  switch (CC) {
116
1.11k
  case CallingConv::AMDGPU_PS:
117
81
    return PALMD::Key::PS_SCRATCH_SIZE;
118
1.11k
  case CallingConv::AMDGPU_VS:
119
24
    return PALMD::Key::VS_SCRATCH_SIZE;
120
1.11k
  case CallingConv::AMDGPU_GS:
121
18
    return PALMD::Key::GS_SCRATCH_SIZE;
122
1.11k
  case CallingConv::AMDGPU_ES:
123
9
    return PALMD::Key::ES_SCRATCH_SIZE;
124
1.11k
  case CallingConv::AMDGPU_HS:
125
24
    return PALMD::Key::HS_SCRATCH_SIZE;
126
1.11k
  case CallingConv::AMDGPU_LS:
127
9
    return PALMD::Key::LS_SCRATCH_SIZE;
128
1.11k
  default:
129
951
    return PALMD::Key::CS_SCRATCH_SIZE;
130
1.11k
  }
131
1.11k
}
132
133
// Set the rsrc1 register in the metadata for a particular shader stage.
134
// In fact this ORs the value into any previous setting of the register.
135
394
void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
136
394
  setRegister(getRsrc1Reg(CC), Val);
137
394
}
138
139
// Set the rsrc2 register in the metadata for a particular shader stage.
140
// In fact this ORs the value into any previous setting of the register.
141
354
void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
142
354
  setRegister(getRsrc1Reg(CC) + 1, Val);
143
354
}
144
145
// Set the SPI_PS_INPUT_ENA register in the metadata.
146
// In fact this ORs the value into any previous setting of the register.
147
33
void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
148
33
  setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
149
33
}
150
151
// Set the SPI_PS_INPUT_ADDR register in the metadata.
152
// In fact this ORs the value into any previous setting of the register.
153
33
void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
154
33
  setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
155
33
}
156
157
// Get a register from the metadata, or 0 if not currently set.
158
0
unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
159
0
  auto Regs = getRegisters();
160
0
  auto It = Regs.find(MsgPackDoc.getNode(Reg));
161
0
  if (It == Regs.end())
162
0
    return 0;
163
0
  auto N = It->second;
164
0
  if (N.getKind() != msgpack::Type::UInt)
165
0
    return 0;
166
0
  return N.getUInt();
167
0
}
168
169
// Set a register in the metadata.
170
// In fact this ORs the value into any previous setting of the register.
171
2.00k
void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
172
2.00k
  if (!isLegacy()) {
173
43
    // In the new MsgPack format, ignore register numbered >= 0x10000000. It
174
43
    // is a PAL ABI pseudo-register in the old non-MsgPack format.
175
43
    if (Reg >= 0x10000000)
176
0
      return;
177
2.00k
  }
178
2.00k
  auto &N = getRegisters()[MsgPackDoc.getNode(Reg)];
179
2.00k
  if (N.getKind() == msgpack::Type::UInt)
180
1.52k
    Val |= N.getUInt();
181
2.00k
  N = N.getDocument()->getNode(Val);
182
2.00k
}
183
184
// Set the entry point name for one shader.
185
394
void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
186
394
  if (isLegacy())
187
372
    return;
188
22
  // Msgpack format.
189
22
  getHwStage(CC)[".entry_point"] = MsgPackDoc.getNode(Name, /*Copy=*/true);
190
22
}
191
192
// Set the number of used vgprs in the metadata. This is an optional
193
// advisory record for logging etc; wave dispatch actually uses the rsrc1
194
// register for the shader stage to determine the number of vgprs to
195
// allocate.
196
394
void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
197
394
  if (isLegacy()) {
198
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    // Old non-msgpack format.
199
372
    unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
200
372
                               PALMD::Key::VS_NUM_USED_VGPRS -
201
372
                               PALMD::Key::VS_SCRATCH_SIZE;
202
372
    setRegister(NumUsedVgprsKey, Val);
203
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    return;
204
372
  }
205
22
  // Msgpack format.
206
22
  getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val);
207
22
}
208
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// Set the number of used sgprs in the metadata. This is an optional advisory
210
// record for logging etc; wave dispatch actually uses the rsrc1 register for
211
// the shader stage to determine the number of sgprs to allocate.
212
394
void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
213
394
  if (isLegacy()) {
214
372
    // Old non-msgpack format.
215
372
    unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
216
372
                               PALMD::Key::VS_NUM_USED_SGPRS -
217
372
                               PALMD::Key::VS_SCRATCH_SIZE;
218
372
    setRegister(NumUsedSgprsKey, Val);
219
372
    return;
220
372
  }
221
22
  // Msgpack format.
222
22
  getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val);
223
22
}
224
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// Set the scratch size in the metadata.
226
394
void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
227
394
  if (isLegacy()) {
228
372
    // Old non-msgpack format.
229
372
    setRegister(getScratchSizeKey(CC), Val);
230
372
    return;
231
372
  }
232
22
  // Msgpack format.
233
22
  getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val);
234
22
}
235
236
// Set the hardware register bit in PAL metadata to enable wave32 on the
237
// shader of the given calling convention.
238
9
void AMDGPUPALMetadata::setWave32(unsigned CC) {
239
9
  switch (CC) {
240
9
  case CallingConv::AMDGPU_HS:
241
2
    setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
242
2
    break;
243
9
  case CallingConv::AMDGPU_GS:
244
2
    setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
245
2
    break;
246
9
  case CallingConv::AMDGPU_VS:
247
1
    setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
248
1
    break;
249
9
  case CallingConv::AMDGPU_PS:
250
0
    setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
251
0
    break;
252
9
  case CallingConv::AMDGPU_CS:
253
1
    setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
254
1
                S_00B800_CS_W32_EN(1));
255
1
    break;
256
9
  }
257
9
}
258
259
// Convert a register number to name, for display by toString().
260
// Returns nullptr if none.
261
47
static const char *getRegisterName(unsigned RegNum) {
262
47
  // Table of registers.
263
47
  static const struct RegInfo {
264
47
    unsigned Num;
265
47
    const char *Name;
266
47
  } RegInfoTable[] = {
267
47
      // Registers that code generation sets/modifies metadata for.
268
47
      {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS, "SPI_SHADER_PGM_RSRC1_VS"},
269
47
      {PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1, "SPI_SHADER_PGM_RSRC2_VS"},
270
47
      {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
271
47
      {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
272
47
      {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
273
47
      {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
274
47
      {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
275
47
      {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
276
47
      {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
277
47
      {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
278
47
      {PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
279
47
      {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
280
47
      {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
281
47
      {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
282
47
      {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
283
47
      {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
284
47
      {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
285
47
      {PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
286
47
      {PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
287
47
288
47
      // Registers not known to code generation.
289
47
      {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
290
47
      {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
291
47
      {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
292
47
      {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
293
47
      {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
294
47
      {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
295
47
296
47
      {0xa1c3, "SPI_SHADER_POS_FORMAT"},
297
47
      {0xa1b1, "SPI_VS_OUT_CONFIG"},
298
47
      {0xa207, "PA_CL_VS_OUT_CNTL"},
299
47
      {0xa204, "PA_CL_CLIP_CNTL"},
300
47
      {0xa206, "PA_CL_VTE_CNTL"},
301
47
      {0xa2f9, "PA_SU_VTX_CNTL"},
302
47
      {0xa293, "PA_SC_MODE_CNTL_1"},
303
47
      {0xa2a1, "VGT_PRIMITIVEID_EN"},
304
47
      {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
305
47
      {0x2e18, "COMPUTE_TMPRING_SIZE"},
306
47
      {0xa1b5, "SPI_INTERP_CONTROL_0"},
307
47
      {0xa1ba, "SPI_TMPRING_SIZE"},
308
47
      {0xa1c4, "SPI_SHADER_Z_FORMAT"},
309
47
      {0xa1c5, "SPI_SHADER_COL_FORMAT"},
310
47
      {0xa203, "DB_SHADER_CONTROL"},
311
47
      {0xa08f, "CB_SHADER_MASK"},
312
47
      {0xa191, "SPI_PS_INPUT_CNTL_0"},
313
47
      {0xa192, "SPI_PS_INPUT_CNTL_1"},
314
47
      {0xa193, "SPI_PS_INPUT_CNTL_2"},
315
47
      {0xa194, "SPI_PS_INPUT_CNTL_3"},
316
47
      {0xa195, "SPI_PS_INPUT_CNTL_4"},
317
47
      {0xa196, "SPI_PS_INPUT_CNTL_5"},
318
47
      {0xa197, "SPI_PS_INPUT_CNTL_6"},
319
47
      {0xa198, "SPI_PS_INPUT_CNTL_7"},
320
47
      {0xa199, "SPI_PS_INPUT_CNTL_8"},
321
47
      {0xa19a, "SPI_PS_INPUT_CNTL_9"},
322
47
      {0xa19b, "SPI_PS_INPUT_CNTL_10"},
323
47
      {0xa19c, "SPI_PS_INPUT_CNTL_11"},
324
47
      {0xa19d, "SPI_PS_INPUT_CNTL_12"},
325
47
      {0xa19e, "SPI_PS_INPUT_CNTL_13"},
326
47
      {0xa19f, "SPI_PS_INPUT_CNTL_14"},
327
47
      {0xa1a0, "SPI_PS_INPUT_CNTL_15"},
328
47
      {0xa1a1, "SPI_PS_INPUT_CNTL_16"},
329
47
      {0xa1a2, "SPI_PS_INPUT_CNTL_17"},
330
47
      {0xa1a3, "SPI_PS_INPUT_CNTL_18"},
331
47
      {0xa1a4, "SPI_PS_INPUT_CNTL_19"},
332
47
      {0xa1a5, "SPI_PS_INPUT_CNTL_20"},
333
47
      {0xa1a6, "SPI_PS_INPUT_CNTL_21"},
334
47
      {0xa1a7, "SPI_PS_INPUT_CNTL_22"},
335
47
      {0xa1a8, "SPI_PS_INPUT_CNTL_23"},
336
47
      {0xa1a9, "SPI_PS_INPUT_CNTL_24"},
337
47
      {0xa1aa, "SPI_PS_INPUT_CNTL_25"},
338
47
      {0xa1ab, "SPI_PS_INPUT_CNTL_26"},
339
47
      {0xa1ac, "SPI_PS_INPUT_CNTL_27"},
340
47
      {0xa1ad, "SPI_PS_INPUT_CNTL_28"},
341
47
      {0xa1ae, "SPI_PS_INPUT_CNTL_29"},
342
47
      {0xa1af, "SPI_PS_INPUT_CNTL_30"},
343
47
      {0xa1b0, "SPI_PS_INPUT_CNTL_31"},
344
47
345
47
      {0xa2ce, "VGT_GS_MAX_VERT_OUT"},
346
47
      {0xa2ab, "VGT_ESGS_RING_ITEMSIZE"},
347
47
      {0xa290, "VGT_GS_MODE"},
348
47
      {0xa291, "VGT_GS_ONCHIP_CNTL"},
349
47
      {0xa2d7, "VGT_GS_VERT_ITEMSIZE"},
350
47
      {0xa2d8, "VGT_GS_VERT_ITEMSIZE_1"},
351
47
      {0xa2d9, "VGT_GS_VERT_ITEMSIZE_2"},
352
47
      {0xa2da, "VGT_GS_VERT_ITEMSIZE_3"},
353
47
      {0xa298, "VGT_GSVS_RING_OFFSET_1"},
354
47
      {0xa299, "VGT_GSVS_RING_OFFSET_2"},
355
47
      {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
356
47
357
47
      {0xa2e4, "VGT_GS_INSTANCE_CNT"},
358
47
      {0xa297, "VGT_GS_PER_VS"},
359
47
      {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
360
47
      {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
361
47
362
47
      {0xa2ad, "VGT_REUSE_OFF"},
363
47
      {0xa1b8, "SPI_BARYC_CNTL"},
364
47
365
47
      {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
366
47
      {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
367
47
      {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
368
47
      {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
369
47
      {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
370
47
      {0x2c51, "SPI_SHADER_USER_DATA_VS_5"},
371
47
      {0x2c52, "SPI_SHADER_USER_DATA_VS_6"},
372
47
      {0x2c53, "SPI_SHADER_USER_DATA_VS_7"},
373
47
      {0x2c54, "SPI_SHADER_USER_DATA_VS_8"},
374
47
      {0x2c55, "SPI_SHADER_USER_DATA_VS_9"},
375
47
      {0x2c56, "SPI_SHADER_USER_DATA_VS_10"},
376
47
      {0x2c57, "SPI_SHADER_USER_DATA_VS_11"},
377
47
      {0x2c58, "SPI_SHADER_USER_DATA_VS_12"},
378
47
      {0x2c59, "SPI_SHADER_USER_DATA_VS_13"},
379
47
      {0x2c5a, "SPI_SHADER_USER_DATA_VS_14"},
380
47
      {0x2c5b, "SPI_SHADER_USER_DATA_VS_15"},
381
47
      {0x2c5c, "SPI_SHADER_USER_DATA_VS_16"},
382
47
      {0x2c5d, "SPI_SHADER_USER_DATA_VS_17"},
383
47
      {0x2c5e, "SPI_SHADER_USER_DATA_VS_18"},
384
47
      {0x2c5f, "SPI_SHADER_USER_DATA_VS_19"},
385
47
      {0x2c60, "SPI_SHADER_USER_DATA_VS_20"},
386
47
      {0x2c61, "SPI_SHADER_USER_DATA_VS_21"},
387
47
      {0x2c62, "SPI_SHADER_USER_DATA_VS_22"},
388
47
      {0x2c63, "SPI_SHADER_USER_DATA_VS_23"},
389
47
      {0x2c64, "SPI_SHADER_USER_DATA_VS_24"},
390
47
      {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
391
47
      {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
392
47
      {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
393
47
      {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
394
47
      {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
395
47
      {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
396
47
      {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
397
47
398
47
      {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
399
47
      {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
400
47
      {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
401
47
      {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
402
47
      {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
403
47
      {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
404
47
      {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
405
47
      {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
406
47
      {0x2cd4, "SPI_SHADER_USER_DATA_ES_8"},
407
47
      {0x2cd5, "SPI_SHADER_USER_DATA_ES_9"},
408
47
      {0x2cd6, "SPI_SHADER_USER_DATA_ES_10"},
409
47
      {0x2cd7, "SPI_SHADER_USER_DATA_ES_11"},
410
47
      {0x2cd8, "SPI_SHADER_USER_DATA_ES_12"},
411
47
      {0x2cd9, "SPI_SHADER_USER_DATA_ES_13"},
412
47
      {0x2cda, "SPI_SHADER_USER_DATA_ES_14"},
413
47
      {0x2cdb, "SPI_SHADER_USER_DATA_ES_15"},
414
47
      {0x2cdc, "SPI_SHADER_USER_DATA_ES_16"},
415
47
      {0x2cdd, "SPI_SHADER_USER_DATA_ES_17"},
416
47
      {0x2cde, "SPI_SHADER_USER_DATA_ES_18"},
417
47
      {0x2cdf, "SPI_SHADER_USER_DATA_ES_19"},
418
47
      {0x2ce0, "SPI_SHADER_USER_DATA_ES_20"},
419
47
      {0x2ce1, "SPI_SHADER_USER_DATA_ES_21"},
420
47
      {0x2ce2, "SPI_SHADER_USER_DATA_ES_22"},
421
47
      {0x2ce3, "SPI_SHADER_USER_DATA_ES_23"},
422
47
      {0x2ce4, "SPI_SHADER_USER_DATA_ES_24"},
423
47
      {0x2ce5, "SPI_SHADER_USER_DATA_ES_25"},
424
47
      {0x2ce6, "SPI_SHADER_USER_DATA_ES_26"},
425
47
      {0x2ce7, "SPI_SHADER_USER_DATA_ES_27"},
426
47
      {0x2ce8, "SPI_SHADER_USER_DATA_ES_28"},
427
47
      {0x2ce9, "SPI_SHADER_USER_DATA_ES_29"},
428
47
      {0x2cea, "SPI_SHADER_USER_DATA_ES_30"},
429
47
      {0x2ceb, "SPI_SHADER_USER_DATA_ES_31"},
430
47
431
47
      {0x2c0c, "SPI_SHADER_USER_DATA_PS_0"},
432
47
      {0x2c0d, "SPI_SHADER_USER_DATA_PS_1"},
433
47
      {0x2c0e, "SPI_SHADER_USER_DATA_PS_2"},
434
47
      {0x2c0f, "SPI_SHADER_USER_DATA_PS_3"},
435
47
      {0x2c10, "SPI_SHADER_USER_DATA_PS_4"},
436
47
      {0x2c11, "SPI_SHADER_USER_DATA_PS_5"},
437
47
      {0x2c12, "SPI_SHADER_USER_DATA_PS_6"},
438
47
      {0x2c13, "SPI_SHADER_USER_DATA_PS_7"},
439
47
      {0x2c14, "SPI_SHADER_USER_DATA_PS_8"},
440
47
      {0x2c15, "SPI_SHADER_USER_DATA_PS_9"},
441
47
      {0x2c16, "SPI_SHADER_USER_DATA_PS_10"},
442
47
      {0x2c17, "SPI_SHADER_USER_DATA_PS_11"},
443
47
      {0x2c18, "SPI_SHADER_USER_DATA_PS_12"},
444
47
      {0x2c19, "SPI_SHADER_USER_DATA_PS_13"},
445
47
      {0x2c1a, "SPI_SHADER_USER_DATA_PS_14"},
446
47
      {0x2c1b, "SPI_SHADER_USER_DATA_PS_15"},
447
47
      {0x2c1c, "SPI_SHADER_USER_DATA_PS_16"},
448
47
      {0x2c1d, "SPI_SHADER_USER_DATA_PS_17"},
449
47
      {0x2c1e, "SPI_SHADER_USER_DATA_PS_18"},
450
47
      {0x2c1f, "SPI_SHADER_USER_DATA_PS_19"},
451
47
      {0x2c20, "SPI_SHADER_USER_DATA_PS_20"},
452
47
      {0x2c21, "SPI_SHADER_USER_DATA_PS_21"},
453
47
      {0x2c22, "SPI_SHADER_USER_DATA_PS_22"},
454
47
      {0x2c23, "SPI_SHADER_USER_DATA_PS_23"},
455
47
      {0x2c24, "SPI_SHADER_USER_DATA_PS_24"},
456
47
      {0x2c25, "SPI_SHADER_USER_DATA_PS_25"},
457
47
      {0x2c26, "SPI_SHADER_USER_DATA_PS_26"},
458
47
      {0x2c27, "SPI_SHADER_USER_DATA_PS_27"},
459
47
      {0x2c28, "SPI_SHADER_USER_DATA_PS_28"},
460
47
      {0x2c29, "SPI_SHADER_USER_DATA_PS_29"},
461
47
      {0x2c2a, "SPI_SHADER_USER_DATA_PS_30"},
462
47
      {0x2c2b, "SPI_SHADER_USER_DATA_PS_31"},
463
47
464
47
      {0x2e40, "COMPUTE_USER_DATA_0"},
465
47
      {0x2e41, "COMPUTE_USER_DATA_1"},
466
47
      {0x2e42, "COMPUTE_USER_DATA_2"},
467
47
      {0x2e43, "COMPUTE_USER_DATA_3"},
468
47
      {0x2e44, "COMPUTE_USER_DATA_4"},
469
47
      {0x2e45, "COMPUTE_USER_DATA_5"},
470
47
      {0x2e46, "COMPUTE_USER_DATA_6"},
471
47
      {0x2e47, "COMPUTE_USER_DATA_7"},
472
47
      {0x2e48, "COMPUTE_USER_DATA_8"},
473
47
      {0x2e49, "COMPUTE_USER_DATA_9"},
474
47
      {0x2e4a, "COMPUTE_USER_DATA_10"},
475
47
      {0x2e4b, "COMPUTE_USER_DATA_11"},
476
47
      {0x2e4c, "COMPUTE_USER_DATA_12"},
477
47
      {0x2e4d, "COMPUTE_USER_DATA_13"},
478
47
      {0x2e4e, "COMPUTE_USER_DATA_14"},
479
47
      {0x2e4f, "COMPUTE_USER_DATA_15"},
480
47
481
47
      {0x2e07, "COMPUTE_NUM_THREAD_X"},
482
47
      {0x2e08, "COMPUTE_NUM_THREAD_Y"},
483
47
      {0x2e09, "COMPUTE_NUM_THREAD_Z"},
484
47
      {0xa2db, "VGT_TF_PARAM"},
485
47
      {0xa2d6, "VGT_LS_HS_CONFIG"},
486
47
      {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
487
47
      {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
488
47
      {0xa2f8, "PA_SC_AA_CONFIG"},
489
47
      {0xa310, "PA_SC_SHADER_CONTROL"},
490
47
      {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
491
47
492
47
      {0x2d0c, "SPI_SHADER_USER_DATA_LS_0"},
493
47
      {0x2d0d, "SPI_SHADER_USER_DATA_LS_1"},
494
47
      {0x2d0e, "SPI_SHADER_USER_DATA_LS_2"},
495
47
      {0x2d0f, "SPI_SHADER_USER_DATA_LS_3"},
496
47
      {0x2d10, "SPI_SHADER_USER_DATA_LS_4"},
497
47
      {0x2d11, "SPI_SHADER_USER_DATA_LS_5"},
498
47
      {0x2d12, "SPI_SHADER_USER_DATA_LS_6"},
499
47
      {0x2d13, "SPI_SHADER_USER_DATA_LS_7"},
500
47
      {0x2d14, "SPI_SHADER_USER_DATA_LS_8"},
501
47
      {0x2d15, "SPI_SHADER_USER_DATA_LS_9"},
502
47
      {0x2d16, "SPI_SHADER_USER_DATA_LS_10"},
503
47
      {0x2d17, "SPI_SHADER_USER_DATA_LS_11"},
504
47
      {0x2d18, "SPI_SHADER_USER_DATA_LS_12"},
505
47
      {0x2d19, "SPI_SHADER_USER_DATA_LS_13"},
506
47
      {0x2d1a, "SPI_SHADER_USER_DATA_LS_14"},
507
47
      {0x2d1b, "SPI_SHADER_USER_DATA_LS_15"},
508
47
      {0x2d1c, "SPI_SHADER_USER_DATA_LS_16"},
509
47
      {0x2d1d, "SPI_SHADER_USER_DATA_LS_17"},
510
47
      {0x2d1e, "SPI_SHADER_USER_DATA_LS_18"},
511
47
      {0x2d1f, "SPI_SHADER_USER_DATA_LS_19"},
512
47
      {0x2d20, "SPI_SHADER_USER_DATA_LS_20"},
513
47
      {0x2d21, "SPI_SHADER_USER_DATA_LS_21"},
514
47
      {0x2d22, "SPI_SHADER_USER_DATA_LS_22"},
515
47
      {0x2d23, "SPI_SHADER_USER_DATA_LS_23"},
516
47
      {0x2d24, "SPI_SHADER_USER_DATA_LS_24"},
517
47
      {0x2d25, "SPI_SHADER_USER_DATA_LS_25"},
518
47
      {0x2d26, "SPI_SHADER_USER_DATA_LS_26"},
519
47
      {0x2d27, "SPI_SHADER_USER_DATA_LS_27"},
520
47
      {0x2d28, "SPI_SHADER_USER_DATA_LS_28"},
521
47
      {0x2d29, "SPI_SHADER_USER_DATA_LS_29"},
522
47
      {0x2d2a, "SPI_SHADER_USER_DATA_LS_30"},
523
47
      {0x2d2b, "SPI_SHADER_USER_DATA_LS_31"},
524
47
525
47
      {0xa2aa, "IA_MULTI_VGT_PARAM"},
526
47
      {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
527
47
      {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
528
47
      {0xa2e5, "VGT_STRMOUT_CONFIG"},
529
47
      {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
530
47
      {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
531
47
      {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
532
47
      {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
533
47
      {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
534
47
535
47
      {0, nullptr}};
536
47
  auto Entry = RegInfoTable;
537
574
  for (; Entry->Num && Entry->Num != RegNum; 
++Entry527
)
538
527
    ;
539
47
  return Entry->Name;
540
47
}
541
542
// Convert the accumulated PAL metadata into an asm directive.
543
2.38k
void AMDGPUPALMetadata::toString(std::string &String) {
544
2.38k
  String.clear();
545
2.38k
  if (!BlobType)
546
2.30k
    return;
547
84
  raw_string_ostream Stream(String);
548
84
  if (isLegacy()) {
549
61
    if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
550
0
      return;
551
61
    // Old linear reg=val format.
552
61
    Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
553
61
    auto Regs = getRegisters();
554
475
    for (auto I = Regs.begin(), E = Regs.end(); I != E; 
++I414
) {
555
414
      if (I != Regs.begin())
556
353
        Stream << ',';
557
414
      unsigned Reg = I->first.getUInt();
558
414
      unsigned Val = I->second.getUInt();
559
414
      Stream << "0x" << Twine::utohexstr(Reg) << ",0x" << Twine::utohexstr(Val);
560
414
    }
561
61
    Stream << '\n';
562
61
    return;
563
61
  }
564
23
565
23
  // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
566
23
  // but first change the registers map to use names.
567
23
  MsgPackDoc.setHexMode();
568
23
  auto &RegsObj = refRegisters();
569
23
  auto OrigRegs = RegsObj.getMap();
570
23
  RegsObj = MsgPackDoc.getMapNode();
571
47
  for (auto I : OrigRegs) {
572
47
    auto Key = I.first;
573
47
    if (const char *RegName = getRegisterName(Key.getUInt())) {
574
47
      std::string KeyName = Key.toString();
575
47
      KeyName += " (";
576
47
      KeyName += RegName;
577
47
      KeyName += ')';
578
47
      Key = MsgPackDoc.getNode(KeyName, /*Copy=*/true);
579
47
    }
580
47
    RegsObj.getMap()[Key] = I.second;
581
47
  }
582
23
583
23
  // Output as YAML.
584
23
  Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
585
23
  MsgPackDoc.toYAML(Stream);
586
23
  Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
587
23
588
23
  // Restore original registers map.
589
23
  RegsObj = OrigRegs;
590
23
}
591
592
// Convert the accumulated PAL metadata into a binary blob for writing as
593
// a .note record of the specified AMD type. Returns an empty blob if
594
// there is no PAL metadata,
595
193
void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
596
193
  if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
597
5
    toLegacyBlob(Blob);
598
188
  else if (Type)
599
1
    toMsgPackBlob(Blob);
600
193
}
601
602
5
void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
603
5
  Blob.clear();
604
5
  auto Registers = getRegisters();
605
5
  if (Registers.getMap().empty())
606
0
    return;
607
5
  raw_string_ostream OS(Blob);
608
5
  support::endian::Writer EW(OS, support::endianness::little);
609
22
  for (auto I : Registers.getMap()) {
610
22
    EW.write(uint32_t(I.first.getUInt()));
611
22
    EW.write(uint32_t(I.second.getUInt()));
612
22
  }
613
5
}
614
615
1
void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
616
1
  Blob.clear();
617
1
  MsgPackDoc.writeToBlob(Blob);
618
1
}
619
620
// Set PAL metadata from YAML text. Returns false if failed.
621
2
bool AMDGPUPALMetadata::setFromString(StringRef S) {
622
2
  BlobType = ELF::NT_AMDGPU_METADATA;
623
2
  if (!MsgPackDoc.fromYAML(S))
624
0
    return false;
625
2
626
2
  // In the registers map, some keys may be of the form "0xa191
627
2
  // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
628
2
  // string. We need to turn it into a number.
629
2
  auto &RegsObj = refRegisters();
630
2
  auto OrigRegs = RegsObj;
631
2
  RegsObj = MsgPackDoc.getMapNode();
632
2
  Registers = RegsObj.getMap();
633
2
  bool Ok = true;
634
8
  for (auto I : OrigRegs.getMap()) {
635
8
    auto Key = I.first;
636
8
    if (Key.getKind() == msgpack::Type::String) {
637
8
      StringRef S = Key.getString();
638
8
      uint64_t Val;
639
8
      if (S.consumeInteger(0, Val)) {
640
0
        Ok = false;
641
0
        errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
642
0
        continue;
643
0
      }
644
8
      Key = MsgPackDoc.getNode(uint64_t(Val));
645
8
    }
646
8
    Registers.getMap()[Key] = I.second;
647
8
  }
648
2
  return Ok;
649
2
}
650
651
// Reference (create if necessary) the node for the registers map.
652
113
msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
653
113
  auto &N =
654
113
      MsgPackDoc.getRoot()
655
113
          .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")]
656
113
          .getArray(/*Convert=*/true)[0]
657
113
          .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".registers")];
658
113
  N.getMap(/*Convert=*/true);
659
113
  return N;
660
113
}
661
662
// Get (create if necessary) the registers map.
663
2.06k
msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
664
2.06k
  if (Registers.isEmpty())
665
88
    Registers = refRegisters();
666
2.06k
  return Registers.getMap();
667
2.06k
}
668
669
// Return the PAL metadata hardware shader stage name.
670
88
static const char *getStageName(CallingConv::ID CC) {
671
88
  switch (CC) {
672
88
  case CallingConv::AMDGPU_PS:
673
24
    return ".ps";
674
88
  case CallingConv::AMDGPU_VS:
675
12
    return ".vs";
676
88
  case CallingConv::AMDGPU_GS:
677
12
    return ".gs";
678
88
  case CallingConv::AMDGPU_ES:
679
8
    return ".es";
680
88
  case CallingConv::AMDGPU_HS:
681
12
    return ".hs";
682
88
  case CallingConv::AMDGPU_LS:
683
8
    return ".ls";
684
88
  default:
685
12
    return ".cs";
686
88
  }
687
88
}
688
689
// Get (create if necessary) the .hardware_stages entry for the given calling
690
// convention.
691
88
msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
692
88
  if (HwStages.isEmpty())
693
22
    HwStages = MsgPackDoc.getRoot()
694
22
                   .getMap(/*Convert=*/true)["amdpal.pipelines"]
695
22
                   .getArray(/*Convert=*/true)[0]
696
22
                   .getMap(/*Convert=*/true)[".hardware_stages"]
697
22
                   .getMap(/*Convert=*/true);
698
88
  return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
699
88
}
700
701
// Get .note record vendor name of metadata blob to be emitted.
702
193
const char *AMDGPUPALMetadata::getVendor() const {
703
193
  return isLegacy() ? 
ElfNote::NoteNameV25
:
ElfNote::NoteNameV3188
;
704
193
}
705
706
// Get .note record type of metadata blob to be emitted:
707
// ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
708
// ELF::NT_AMDGPU_METADATA (MsgPack format), or
709
// 0 (no PAL metadata).
710
193
unsigned AMDGPUPALMetadata::getType() const {
711
193
  return BlobType;
712
193
}
713
714
// Return whether the blob type is legacy PAL metadata.
715
3.85k
bool AMDGPUPALMetadata::isLegacy() const {
716
3.85k
  return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA;
717
3.85k
}
718
719
// Set legacy PAL metadata format.
720
2
void AMDGPUPALMetadata::setLegacy() {
721
2
  BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
722
2
}
723