Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Base ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <array>
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#include <cstdint>
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#define GET_INSTRINFO_HEADER
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#include "ARMGenInstrInfo.inc"
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namespace llvm {
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class ARMBaseRegisterInfo;
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class ARMSubtarget;
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class ARMBaseInstrInfo : public ARMGenInstrInfo {
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  const ARMSubtarget &Subtarget;
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protected:
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  // Can be only subclassed.
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  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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  void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
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                                unsigned LoadImmOpc, unsigned LoadOpc) const;
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  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
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  /// and \p DefIdx.
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  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
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  /// the list is modeled as <Reg:SubReg, SubIdx>.
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  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
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  /// two elements:
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  /// - %1:sub1, sub0
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  /// - %2<:0>, sub1
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  ///
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  /// \returns true if it is possible to build such an input sequence
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  /// with the pair \p MI, \p DefIdx. False otherwise.
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  ///
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  /// \pre MI.isRegSequenceLike().
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  bool getRegSequenceLikeInputs(
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      const MachineInstr &MI, unsigned DefIdx,
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      SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
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  /// and \p DefIdx.
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  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
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  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
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  /// - %1:sub1, sub0
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  ///
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  /// \returns true if it is possible to build such an input sequence
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  /// with the pair \p MI, \p DefIdx. False otherwise.
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  ///
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  /// \pre MI.isExtractSubregLike().
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  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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                                  RegSubRegPairAndIdx &InputReg) const override;
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  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
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  /// and \p DefIdx.
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  /// \p [out] BaseReg and \p [out] InsertedReg contain
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  /// the equivalent inputs of INSERT_SUBREG.
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  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
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  /// - BaseReg: %0:sub0
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  /// - InsertedReg: %1:sub1, sub3
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  ///
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  /// \returns true if it is possible to build such an input sequence
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  /// with the pair \p MI, \p DefIdx. False otherwise.
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  ///
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  /// \pre MI.isInsertSubregLike().
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  bool
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  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
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                            RegSubRegPair &BaseReg,
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                            RegSubRegPairAndIdx &InsertedReg) const override;
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  /// Commutes the operands in the given instruction.
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  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
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  ///
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  /// Do not call this method for a non-commutable instruction or for
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  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
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  /// Even though the instruction is commutable, the method may still
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  /// fail to commute the operands, null pointer is returned in such cases.
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  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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                                       unsigned OpIdx1,
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                                       unsigned OpIdx2) const override;
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  /// If the specific machine instruction is a instruction that moves/copies
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  /// value from one register to another register return true along with
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  /// @Source machine operand and @Destination machine operand.
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  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
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                       const MachineOperand *&Destination) const override;
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public:
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  // Return whether the target has an explicit NOP encoding.
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  bool hasNOP() const;
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  // Return the non-pre/post incrementing version of 'Opc'. Return 0
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  // if there is not such an opcode.
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  virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
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  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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                                      MachineInstr &MI,
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                                      LiveVariables *LV) const override;
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  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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307k
  const ARMSubtarget &getSubtarget() const { return Subtarget; }
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  ScheduleHazardRecognizer *
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  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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                               const ScheduleDAG *DAG) const override;
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  ScheduleHazardRecognizer *
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  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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                                     const ScheduleDAG *DAG) const override;
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  // Branch analysis.
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  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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                     MachineBasicBlock *&FBB,
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                     SmallVectorImpl<MachineOperand> &Cond,
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                     bool AllowModify = false) const override;
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  unsigned removeBranch(MachineBasicBlock &MBB,
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                        int *BytesRemoved = nullptr) const override;
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  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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                        const DebugLoc &DL,
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                        int *BytesAdded = nullptr) const override;
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  bool
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  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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  // Predication support.
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  bool isPredicated(const MachineInstr &MI) const override;
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  ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
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    int PIdx = MI.findFirstPredOperandIdx();
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    return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
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                      : ARMCC::AL;
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  }
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  bool PredicateInstruction(MachineInstr &MI,
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                            ArrayRef<MachineOperand> Pred) const override;
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  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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                         ArrayRef<MachineOperand> Pred2) const override;
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  bool DefinesPredicate(MachineInstr &MI,
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                        std::vector<MachineOperand> &Pred) const override;
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  bool isPredicable(const MachineInstr &MI) const override;
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  // CPSR defined in instruction
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  static bool isCPSRDefined(const MachineInstr &MI);
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  bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
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  bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
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  // Load, scaled register offset
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  bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
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  // Load, scaled register offset, not plus LSL2
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  bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
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  // Minus reg for ldstso addr mode
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  bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
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  // Scaled register offset in address mode 2
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  bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
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  // Load multiple, base reg in list
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  bool isLDMBaseRegInList(const MachineInstr &MI) const;
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  // get LDM variable defs size
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  unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
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  /// GetInstSize - Returns the size of the specified MachineInstr.
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  ///
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  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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  unsigned isLoadFromStackSlot(const MachineInstr &MI,
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                               int &FrameIndex) const override;
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  unsigned isStoreToStackSlot(const MachineInstr &MI,
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                              int &FrameIndex) const override;
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  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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                                     int &FrameIndex) const override;
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  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
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                                    int &FrameIndex) const override;
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  void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                  unsigned SrcReg, bool KillSrc,
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                  const ARMSubtarget &Subtarget) const;
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  void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                    unsigned DestReg, bool KillSrc,
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                    const ARMSubtarget &Subtarget) const;
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  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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                   bool KillSrc) const override;
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  void storeRegToStackSlot(MachineBasicBlock &MBB,
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                           MachineBasicBlock::iterator MBBI,
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                           unsigned SrcReg, bool isKill, int FrameIndex,
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                           const TargetRegisterClass *RC,
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                           const TargetRegisterInfo *TRI) const override;
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  void loadRegFromStackSlot(MachineBasicBlock &MBB,
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                            MachineBasicBlock::iterator MBBI,
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                            unsigned DestReg, int FrameIndex,
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                            const TargetRegisterClass *RC,
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                            const TargetRegisterInfo *TRI) const override;
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  bool expandPostRAPseudo(MachineInstr &MI) const override;
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  bool shouldSink(const MachineInstr &MI) const override;
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  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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                     unsigned DestReg, unsigned SubIdx,
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                     const MachineInstr &Orig,
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                     const TargetRegisterInfo &TRI) const override;
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  MachineInstr &
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  duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
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            const MachineInstr &Orig) const override;
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  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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                                     unsigned SubIdx, unsigned State,
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                                     const TargetRegisterInfo *TRI) const;
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  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
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                        const MachineRegisterInfo *MRI) const override;
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  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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  /// determine if two loads are loading from the same base address. It should
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  /// only return true if the base pointers are the same and the only
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  /// differences between the two addresses is the offset. It also returns the
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  /// offsets by reference.
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  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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                               int64_t &Offset2) const override;
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  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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  /// should be scheduled togther. On some targets if two loads are loading from
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  /// addresses in the same cache line, it's better if they are scheduled
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  /// together. This function takes two integers that represent the load offsets
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  /// from the common base address. It returns true if it decides it's desirable
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  /// to schedule the two loads together. "NumLoads" is the number of loads that
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  /// have already been scheduled after Load1.
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  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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                               int64_t Offset1, int64_t Offset2,
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                               unsigned NumLoads) const override;
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  bool isSchedulingBoundary(const MachineInstr &MI,
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                            const MachineBasicBlock *MBB,
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                            const MachineFunction &MF) const override;
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  bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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                           unsigned NumCycles, unsigned ExtraPredCycles,
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                           BranchProbability Probability) const override;
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  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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                           unsigned ExtraT, MachineBasicBlock &FMBB,
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                           unsigned NumF, unsigned ExtraF,
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                           BranchProbability Probability) const override;
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  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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82.5k
                                 BranchProbability Probability) const override {
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82.5k
    return NumCycles == 1;
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82.5k
  }
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  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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                                 MachineBasicBlock &FMBB) const override;
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  /// analyzeCompare - For a comparison instruction, return the source registers
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  /// in SrcReg and SrcReg2 if having two register operands, and the value it
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  /// compares against in CmpValue. Return true if the comparison instruction
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  /// can be analyzed.
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  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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                      unsigned &SrcReg2, int &CmpMask,
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                      int &CmpValue) const override;
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  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
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  /// that we can remove a "comparison with zero"; Remove a redundant CMP
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  /// instruction if the flags can be updated in the same way by an earlier
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  /// instruction such as SUB.
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  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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                            unsigned SrcReg2, int CmpMask, int CmpValue,
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                            const MachineRegisterInfo *MRI) const override;
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  bool analyzeSelect(const MachineInstr &MI,
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                     SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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                     unsigned &FalseOp, bool &Optimizable) const override;
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  MachineInstr *optimizeSelect(MachineInstr &MI,
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                               SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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                               bool) const override;
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  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
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  /// instruction, try to fold the immediate into the use instruction.
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  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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                     MachineRegisterInfo *MRI) const override;
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  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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                          const MachineInstr &MI) const override;
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  int getOperandLatency(const InstrItineraryData *ItinData,
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                        const MachineInstr &DefMI, unsigned DefIdx,
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                        const MachineInstr &UseMI,
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                        unsigned UseIdx) const override;
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  int getOperandLatency(const InstrItineraryData *ItinData,
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                        SDNode *DefNode, unsigned DefIdx,
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                        SDNode *UseNode, unsigned UseIdx) const override;
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  /// VFP/NEON execution domains.
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  std::pair<uint16_t, uint16_t>
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  getExecutionDomain(const MachineInstr &MI) const override;
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  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
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  unsigned
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  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
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                               const TargetRegisterInfo *) const override;
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  void breakPartialRegDependency(MachineInstr &, unsigned,
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                                 const TargetRegisterInfo *TRI) const override;
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  /// Get the number of addresses by LDM or VLDM or zero for unknown.
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  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
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  std::pair<unsigned, unsigned>
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  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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  ArrayRef<std::pair<unsigned, const char *>>
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  getSerializableDirectMachineOperandTargetFlags() const override;
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  ArrayRef<std::pair<unsigned, const char *>>
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  getSerializableBitmaskMachineOperandTargetFlags() const override;
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private:
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  unsigned getInstBundleLength(const MachineInstr &MI) const;
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  int getVLDMDefCycle(const InstrItineraryData *ItinData,
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                      const MCInstrDesc &DefMCID,
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                      unsigned DefClass,
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                      unsigned DefIdx, unsigned DefAlign) const;
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  int getLDMDefCycle(const InstrItineraryData *ItinData,
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                     const MCInstrDesc &DefMCID,
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                     unsigned DefClass,
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                     unsigned DefIdx, unsigned DefAlign) const;
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  int getVSTMUseCycle(const InstrItineraryData *ItinData,
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                      const MCInstrDesc &UseMCID,
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                      unsigned UseClass,
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                      unsigned UseIdx, unsigned UseAlign) const;
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  int getSTMUseCycle(const InstrItineraryData *ItinData,
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                     const MCInstrDesc &UseMCID,
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                     unsigned UseClass,
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                     unsigned UseIdx, unsigned UseAlign) const;
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  int getOperandLatency(const InstrItineraryData *ItinData,
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                        const MCInstrDesc &DefMCID,
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                        unsigned DefIdx, unsigned DefAlign,
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                        const MCInstrDesc &UseMCID,
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                        unsigned UseIdx, unsigned UseAlign) const;
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  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
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                            const MachineInstr &DefMI, unsigned DefIdx,
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                            const MCInstrDesc &DefMCID, unsigned DefAdj,
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                            const MachineOperand &DefMO, unsigned Reg,
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                            const MachineInstr &UseMI, unsigned UseIdx,
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                            const MCInstrDesc &UseMCID, unsigned UseAdj) const;
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  unsigned getPredicationCost(const MachineInstr &MI) const override;
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  unsigned getInstrLatency(const InstrItineraryData *ItinData,
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                           const MachineInstr &MI,
379
                           unsigned *PredCost = nullptr) const override;
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  int getInstrLatency(const InstrItineraryData *ItinData,
382
                      SDNode *Node) const override;
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  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
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                             const MachineRegisterInfo *MRI,
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                             const MachineInstr &DefMI, unsigned DefIdx,
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                             const MachineInstr &UseMI,
388
                             unsigned UseIdx) const override;
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  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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                        const MachineInstr &DefMI,
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                        unsigned DefIdx) const override;
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  /// verifyInstruction - Perform target specific instruction verification.
394
  bool verifyInstruction(const MachineInstr &MI,
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                         StringRef &ErrInfo) const override;
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  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
398
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  void expandMEMCPY(MachineBasicBlock::iterator) const;
400
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  /// Identify instructions that can be folded into a MOVCC instruction, and
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  /// return the defining instruction.
403
  MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
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                                 const TargetInstrInfo *TII) const;
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private:
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  /// Modeling special VFP / NEON fp MLA / MLS hazards.
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  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
410
  /// MLx table.
411
  DenseMap<unsigned, unsigned> MLxEntryMap;
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  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
414
  /// stalls when scheduled together with fp MLA / MLS opcodes.
415
  SmallSet<unsigned, 16> MLxHazardOpcodes;
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public:
418
  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
419
  /// instruction.
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67.8k
  bool isFpMLxInstruction(unsigned Opcode) const {
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67.8k
    return MLxEntryMap.count(Opcode);
422
67.8k
  }
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  /// isFpMLxInstruction - This version also returns the multiply opcode and the
425
  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
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  /// the MLX instructions with an extra lane operand.
427
  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
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                          unsigned &AddSubOpc, bool &NegAcc,
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                          bool &HasLane) const;
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  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
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  /// will cause stalls when scheduled after (within 4-cycle window) a fp
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  /// MLA / MLS instruction.
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1.24k
  bool canCauseFpMLxStall(unsigned Opcode) const {
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    return MLxHazardOpcodes.count(Opcode);
436
1.24k
  }
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  /// Returns true if the instruction has a shift by immediate that can be
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  /// executed in one cycle less.
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  bool isSwiftFastImmShift(const MachineInstr *MI) const;
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  /// Returns predicate register associated with the given frame instruction.
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182
  unsigned getFramePred(const MachineInstr &MI) const {
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    assert(isFrameInstr(MI));
445
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    // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
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    // - argument declared in the pattern:
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    // 0 - frame size
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    // 1 - arg of CALLSEQ_START/CALLSEQ_END
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    // 2 - predicate code (like ARMCC::AL)
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    // - added by predOps:
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    // 3 - predicate reg
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    return MI.getOperand(3).getReg();
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182
  }
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};
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/// Get the operands corresponding to the given \p Pred value. By default, the
457
/// predicate register is assumed to be 0 (no register), but you can pass in a
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/// \p PredReg if that is not the case.
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static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
460
279k
                                                    unsigned PredReg = 0) {
461
279k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
279k
           MachineOperand::CreateReg(PredReg, false)}};
463
279k
}
A15SDOptimizer.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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Source
460
17
                                                    unsigned PredReg = 0) {
461
17
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
17
           MachineOperand::CreateReg(PredReg, false)}};
463
17
}
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMBaseInstrInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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460
105k
                                                    unsigned PredReg = 0) {
461
105k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
105k
           MachineOperand::CreateReg(PredReg, false)}};
463
105k
}
ARMBaseRegisterInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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460
3
                                                    unsigned PredReg = 0) {
461
3
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
3
           MachineOperand::CreateReg(PredReg, false)}};
463
3
}
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMCallLowering.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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Source
460
1.29k
                                                    unsigned PredReg = 0) {
461
1.29k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
1.29k
           MachineOperand::CreateReg(PredReg, false)}};
463
1.29k
}
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMConstantIslandPass.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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460
100
                                                    unsigned PredReg = 0) {
461
100
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
100
           MachineOperand::CreateReg(PredReg, false)}};
463
100
}
ARMExpandPseudoInsts.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
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460
4.44k
                                                    unsigned PredReg = 0) {
461
4.44k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
4.44k
           MachineOperand::CreateReg(PredReg, false)}};
463
4.44k
}
ARMFastISel.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
6.24k
                                                    unsigned PredReg = 0) {
461
6.24k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
6.24k
           MachineOperand::CreateReg(PredReg, false)}};
463
6.24k
}
ARMFrameLowering.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
32.6k
                                                    unsigned PredReg = 0) {
461
32.6k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
32.6k
           MachineOperand::CreateReg(PredReg, false)}};
463
32.6k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMInstructionSelector.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
816
                                                    unsigned PredReg = 0) {
461
816
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
816
           MachineOperand::CreateReg(PredReg, false)}};
463
816
}
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMISelLowering.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
7.72k
                                                    unsigned PredReg = 0) {
461
7.72k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
7.72k
           MachineOperand::CreateReg(PredReg, false)}};
463
7.72k
}
ARMInstrInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
10
                                                    unsigned PredReg = 0) {
461
10
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
10
           MachineOperand::CreateReg(PredReg, false)}};
463
10
}
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
ARMLoadStoreOptimizer.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
858
                                                    unsigned PredReg = 0) {
461
858
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
858
           MachineOperand::CreateReg(PredReg, false)}};
463
858
}
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Thumb1FrameLowering.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
2.84k
                                                    unsigned PredReg = 0) {
461
2.84k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
2.84k
           MachineOperand::CreateReg(PredReg, false)}};
463
2.84k
}
Thumb1InstrInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
5.87k
                                                    unsigned PredReg = 0) {
461
5.87k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
5.87k
           MachineOperand::CreateReg(PredReg, false)}};
463
5.87k
}
ThumbRegisterInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
1.51k
                                                    unsigned PredReg = 0) {
461
1.51k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
1.51k
           MachineOperand::CreateReg(PredReg, false)}};
463
1.51k
}
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Thumb2InstrInfo.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
97.3k
                                                    unsigned PredReg = 0) {
461
97.3k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
97.3k
           MachineOperand::CreateReg(PredReg, false)}};
463
97.3k
}
Thumb2SizeReduction.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
Line
Count
Source
460
11.9k
                                                    unsigned PredReg = 0) {
461
11.9k
  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
462
11.9k
           MachineOperand::CreateReg(PredReg, false)}};
463
11.9k
}
Unexecuted instantiation: ARMAsmParser.cpp:llvm::predOps(llvm::ARMCC::CondCodes, unsigned int)
464
465
/// Get the operand corresponding to the conditional code result. By default,
466
/// this is 0 (no register).
467
30.0k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
30.0k
  return MachineOperand::CreateReg(CCReg, false);
469
30.0k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::condCodeOp(unsigned int)
ARMBaseInstrInfo.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
9.42k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
9.42k
  return MachineOperand::CreateReg(CCReg, false);
469
9.42k
}
ARMBaseRegisterInfo.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
3
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
3
  return MachineOperand::CreateReg(CCReg, false);
469
3
}
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::condCodeOp(unsigned int)
ARMExpandPseudoInsts.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
5.27k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
5.27k
  return MachineOperand::CreateReg(CCReg, false);
469
5.27k
}
ARMFastISel.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
1.04k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
1.04k
  return MachineOperand::CreateReg(CCReg, false);
469
1.04k
}
ARMFrameLowering.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
404
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
404
  return MachineOperand::CreateReg(CCReg, false);
469
404
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::condCodeOp(unsigned int)
ARMInstructionSelector.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
263
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
263
  return MachineOperand::CreateReg(CCReg, false);
469
263
}
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::condCodeOp(unsigned int)
ARMISelLowering.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
207
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
207
  return MachineOperand::CreateReg(CCReg, false);
469
207
}
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::condCodeOp(unsigned int)
ARMLoadStoreOptimizer.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
499
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
499
  return MachineOperand::CreateReg(CCReg, false);
469
499
}
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::condCodeOp(unsigned int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::condCodeOp(unsigned int)
Thumb2InstrInfo.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
9.15k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
9.15k
  return MachineOperand::CreateReg(CCReg, false);
469
9.15k
}
Thumb2SizeReduction.cpp:llvm::condCodeOp(unsigned int)
Line
Count
Source
467
3.82k
static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
468
3.82k
  return MachineOperand::CreateReg(CCReg, false);
469
3.82k
}
Unexecuted instantiation: ARMAsmParser.cpp:llvm::condCodeOp(unsigned int)
470
471
/// Get the operand corresponding to the conditional code result for Thumb1.
472
/// This operand will always refer to CPSR and it will have the Define flag set.
473
/// You can optionally set the Dead flag by means of \p isDead.
474
60.2k
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475
60.2k
  return MachineOperand::CreateReg(ARM::CPSR,
476
60.2k
                                   /*Define*/ true, /*Implicit*/ false,
477
60.2k
                                   /*Kill*/ false, isDead);
478
60.2k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMFastISel.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::t1CondCodeOp(bool)
ARMISelLowering.cpp:llvm::t1CondCodeOp(bool)
Line
Count
Source
474
1.91k
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475
1.91k
  return MachineOperand::CreateReg(ARM::CPSR,
476
1.91k
                                   /*Define*/ true, /*Implicit*/ false,
477
1.91k
                                   /*Kill*/ false, isDead);
478
1.91k
}
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::t1CondCodeOp(bool)
ARMLoadStoreOptimizer.cpp:llvm::t1CondCodeOp(bool)
Line
Count
Source
474
21
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475
21
  return MachineOperand::CreateReg(ARM::CPSR,
476
21
                                   /*Define*/ true, /*Implicit*/ false,
477
21
                                   /*Kill*/ false, isDead);
478
21
}
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::t1CondCodeOp(bool)
ThumbRegisterInfo.cpp:llvm::t1CondCodeOp(bool)
Line
Count
Source
474
219
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475
219
  return MachineOperand::CreateReg(ARM::CPSR,
476
219
                                   /*Define*/ true, /*Implicit*/ false,
477
219
                                   /*Kill*/ false, isDead);
478
219
}
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::t1CondCodeOp(bool)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::t1CondCodeOp(bool)
Thumb2SizeReduction.cpp:llvm::t1CondCodeOp(bool)
Line
Count
Source
474
58.0k
static inline MachineOperand t1CondCodeOp(bool isDead = false) {
475
58.0k
  return MachineOperand::CreateReg(ARM::CPSR,
476
58.0k
                                   /*Define*/ true, /*Implicit*/ false,
477
58.0k
                                   /*Kill*/ false, isDead);
478
58.0k
}
Unexecuted instantiation: ARMAsmParser.cpp:llvm::t1CondCodeOp(bool)
479
480
static inline
481
4.13M
bool isUncondBranchOpcode(int Opc) {
482
4.13M
  return Opc == ARM::B || 
Opc == ARM::tB4.10M
||
Opc == ARM::t2B4.06M
;
483
4.13M
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isUncondBranchOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isUncondBranchOpcode(int)
Line
Count
Source
481
4.13M
bool isUncondBranchOpcode(int Opc) {
482
4.13M
  return Opc == ARM::B || 
Opc == ARM::tB4.10M
||
Opc == ARM::t2B4.06M
;
483
4.13M
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isUncondBranchOpcode(int)
484
485
0
static inline bool isVPTOpcode(int Opc) {
486
0
  return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
487
0
         Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
488
0
         Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
489
0
         Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
490
0
         Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
491
0
         Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
492
0
         Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
493
0
         Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
494
0
         Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
495
0
         Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
496
0
         Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
497
0
         Opc == ARM::MVE_VPST;
498
0
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isVPTOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isVPTOpcode(int)
499
500
static inline
501
2.87M
bool isCondBranchOpcode(int Opc) {
502
2.87M
  return Opc == ARM::Bcc || 
Opc == ARM::tBcc2.83M
||
Opc == ARM::t2Bcc2.79M
;
503
2.87M
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isCondBranchOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isCondBranchOpcode(int)
Line
Count
Source
501
2.87M
bool isCondBranchOpcode(int Opc) {
502
2.87M
  return Opc == ARM::Bcc || 
Opc == ARM::tBcc2.83M
||
Opc == ARM::t2Bcc2.79M
;
503
2.87M
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isCondBranchOpcode(int)
504
505
3.20M
static inline bool isJumpTableBranchOpcode(int Opc) {
506
3.20M
  return Opc == ARM::BR_JTr || 
Opc == ARM::BR_JTm_i123.20M
||
507
3.20M
         
Opc == ARM::BR_JTm_rs3.20M
||
Opc == ARM::BR_JTadd3.20M
||
Opc == ARM::tBR_JTr3.20M
||
508
3.20M
         
Opc == ARM::t2BR_JT3.20M
;
509
3.20M
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isJumpTableBranchOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Line
Count
Source
505
3.20M
static inline bool isJumpTableBranchOpcode(int Opc) {
506
3.20M
  return Opc == ARM::BR_JTr || 
Opc == ARM::BR_JTm_i123.20M
||
507
3.20M
         
Opc == ARM::BR_JTm_rs3.20M
||
Opc == ARM::BR_JTadd3.20M
||
Opc == ARM::tBR_JTr3.20M
||
508
3.20M
         
Opc == ARM::t2BR_JT3.20M
;
509
3.20M
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isJumpTableBranchOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isJumpTableBranchOpcode(int)
510
511
static inline
512
3.21M
bool isIndirectBranchOpcode(int Opc) {
513
3.21M
  return Opc == ARM::BX || 
Opc == ARM::MOVPCRX3.20M
||
Opc == ARM::tBRIND3.20M
;
514
3.21M
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isIndirectBranchOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isIndirectBranchOpcode(int)
Line
Count
Source
512
3.21M
bool isIndirectBranchOpcode(int Opc) {
513
3.21M
  return Opc == ARM::BX || 
Opc == ARM::MOVPCRX3.20M
||
Opc == ARM::tBRIND3.20M
;
514
3.21M
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isIndirectBranchOpcode(int)
515
516
24.8k
static inline bool isPopOpcode(int Opc) {
517
24.8k
  return Opc == ARM::tPOP_RET || 
Opc == ARM::LDMIA_RET24.6k
||
518
24.8k
         
Opc == ARM::t2LDMIA_RET24.6k
||
Opc == ARM::tPOP24.5k
||
Opc == ARM::LDMIA_UPD24.5k
||
519
24.8k
         
Opc == ARM::t2LDMIA_UPD23.6k
||
Opc == ARM::VLDMDIA_UPD18.9k
;
520
24.8k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isPopOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isPopOpcode(int)
Line
Count
Source
516
682
static inline bool isPopOpcode(int Opc) {
517
682
  return Opc == ARM::tPOP_RET || 
Opc == ARM::LDMIA_RET508
||
518
682
         
Opc == ARM::t2LDMIA_RET507
||
Opc == ARM::tPOP401
||
Opc == ARM::LDMIA_UPD397
||
519
682
         
Opc == ARM::t2LDMIA_UPD397
||
Opc == ARM::VLDMDIA_UPD359
;
520
682
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isPopOpcode(int)
ARMFrameLowering.cpp:llvm::isPopOpcode(int)
Line
Count
Source
516
24.1k
static inline bool isPopOpcode(int Opc) {
517
24.1k
  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
518
24.1k
         Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
519
24.1k
         
Opc == ARM::t2LDMIA_UPD23.2k
||
Opc == ARM::VLDMDIA_UPD18.6k
;
520
24.1k
}
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isPopOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isPopOpcode(int)
521
522
682
static inline bool isPushOpcode(int Opc) {
523
682
  return Opc == ARM::tPUSH || 
Opc == ARM::t2STMDB_UPD508
||
524
682
         
Opc == ARM::STMDB_UPD358
||
Opc == ARM::VSTMDDB_UPD357
;
525
682
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isPushOpcode(int)
ARMBaseInstrInfo.cpp:llvm::isPushOpcode(int)
Line
Count
Source
522
682
static inline bool isPushOpcode(int Opc) {
523
682
  return Opc == ARM::tPUSH || 
Opc == ARM::t2STMDB_UPD508
||
524
682
         
Opc == ARM::STMDB_UPD358
||
Opc == ARM::VSTMDDB_UPD357
;
525
682
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isPushOpcode(int)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::isPushOpcode(int)
526
527
/// isValidCoprocessorNumber - decide whether an explicit coprocessor
528
/// number is legal in generic instructions like CDP. The answer can
529
/// vary with the subtarget.
530
static inline bool isValidCoprocessorNumber(unsigned Num,
531
1.06k
                                            const FeatureBitset& featureBits) {
532
1.06k
  // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
533
1.06k
  if (featureBits[ARM::HasV8Ops] && 
(Num & 0xE) != 0xE564
)
534
59
    return false;
535
1.00k
536
1.00k
  // Armv7 disallows 101x (CP10 and CP11), which clash with VFP/NEON.
537
1.00k
  if (featureBits[ARM::HasV7Ops] && 
(Num & 0xE) == 0xA996
)
538
15
    return false;
539
992
540
992
  // Armv8.1-M also disallows 100x (CP8,CP9) and 111x (CP14,CP15)
541
992
  // which clash with MVE.
542
992
  if (featureBits[ARM::HasV8_1MMainlineOps] &&
543
992
      
(18
(Num & 0xE) == 0x818
||
(Num & 0xE) == 0xE14
))
544
8
    return false;
545
984
546
984
  return true;
547
984
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMFastISel.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
ARMAsmParser.cpp:llvm::isValidCoprocessorNumber(unsigned int, llvm::FeatureBitset const&)
Line
Count
Source
531
1.06k
                                            const FeatureBitset& featureBits) {
532
1.06k
  // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
533
1.06k
  if (featureBits[ARM::HasV8Ops] && 
(Num & 0xE) != 0xE564
)
534
59
    return false;
535
1.00k
536
1.00k
  // Armv7 disallows 101x (CP10 and CP11), which clash with VFP/NEON.
537
1.00k
  if (featureBits[ARM::HasV7Ops] && 
(Num & 0xE) == 0xA996
)
538
15
    return false;
539
992
540
992
  // Armv8.1-M also disallows 100x (CP8,CP9) and 111x (CP14,CP15)
541
992
  // which clash with MVE.
542
992
  if (featureBits[ARM::HasV8_1MMainlineOps] &&
543
992
      
(18
(Num & 0xE) == 0x818
||
(Num & 0xE) == 0xE14
))
544
8
    return false;
545
984
546
984
  return true;
547
984
}
548
549
/// getInstrPredicate - If instruction is predicated, returns its predicate
550
/// condition, otherwise returns AL. It also returns the condition code
551
/// register by reference.
552
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
553
554
unsigned getMatchingCondBranchOpcode(unsigned Opc);
555
556
/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
557
/// the instruction is encoded with an 'S' bit is determined by the optional
558
/// CPSR def operand.
559
unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
560
561
/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
562
/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
563
/// code.
564
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
565
                             MachineBasicBlock::iterator &MBBI,
566
                             const DebugLoc &dl, unsigned DestReg,
567
                             unsigned BaseReg, int NumBytes,
568
                             ARMCC::CondCodes Pred, unsigned PredReg,
569
                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
570
571
void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
572
                            MachineBasicBlock::iterator &MBBI,
573
                            const DebugLoc &dl, unsigned DestReg,
574
                            unsigned BaseReg, int NumBytes,
575
                            ARMCC::CondCodes Pred, unsigned PredReg,
576
                            const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
577
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
578
                               MachineBasicBlock::iterator &MBBI,
579
                               const DebugLoc &dl, unsigned DestReg,
580
                               unsigned BaseReg, int NumBytes,
581
                               const TargetInstrInfo &TII,
582
                               const ARMBaseRegisterInfo &MRI,
583
                               unsigned MIFlags = 0);
584
585
/// Tries to add registers to the reglist of a given base-updating
586
/// push/pop instruction to adjust the stack by an additional
587
/// NumBytes. This can save a few bytes per function in code-size, but
588
/// obviously generates more memory traffic. As such, it only takes
589
/// effect in functions being optimised for size.
590
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
591
                                MachineFunction &MF, MachineInstr *MI,
592
                                unsigned NumBytes);
593
594
/// rewriteARMFrameIndex / rewriteT2FrameIndex -
595
/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
596
/// offset could not be handled directly in MI, and return the left-over
597
/// portion by reference.
598
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
599
                          unsigned FrameReg, int &Offset,
600
                          const ARMBaseInstrInfo &TII);
601
602
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
603
                         unsigned FrameReg, int &Offset,
604
                         const ARMBaseInstrInfo &TII);
605
606
/// Return true if Reg is defd between From and To
607
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From,
608
                            MachineBasicBlock::iterator To,
609
                            const TargetRegisterInfo *TRI);
610
611
/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
612
/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
613
MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
614
                                   const TargetRegisterInfo *TRI);
615
616
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
617
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg);
618
619
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
620
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
621
                              unsigned Inactive);
622
623
} // end namespace llvm
624
625
#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H