Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
Line
Count
Source (jump to first uncovered line)
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//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the base ARM implementation of TargetRegisterInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARMBaseRegisterInfo.h"
14
#include "ARM.h"
15
#include "ARMBaseInstrInfo.h"
16
#include "ARMFrameLowering.h"
17
#include "ARMMachineFunctionInfo.h"
18
#include "ARMSubtarget.h"
19
#include "MCTargetDesc/ARMAddressingModes.h"
20
#include "MCTargetDesc/ARMBaseInfo.h"
21
#include "llvm/ADT/BitVector.h"
22
#include "llvm/ADT/STLExtras.h"
23
#include "llvm/ADT/SmallVector.h"
24
#include "llvm/CodeGen/MachineBasicBlock.h"
25
#include "llvm/CodeGen/MachineConstantPool.h"
26
#include "llvm/CodeGen/MachineFrameInfo.h"
27
#include "llvm/CodeGen/MachineFunction.h"
28
#include "llvm/CodeGen/MachineInstr.h"
29
#include "llvm/CodeGen/MachineInstrBuilder.h"
30
#include "llvm/CodeGen/MachineOperand.h"
31
#include "llvm/CodeGen/MachineRegisterInfo.h"
32
#include "llvm/CodeGen/RegisterScavenging.h"
33
#include "llvm/CodeGen/TargetInstrInfo.h"
34
#include "llvm/CodeGen/TargetRegisterInfo.h"
35
#include "llvm/CodeGen/VirtRegMap.h"
36
#include "llvm/IR/Attributes.h"
37
#include "llvm/IR/Constants.h"
38
#include "llvm/IR/DebugLoc.h"
39
#include "llvm/IR/Function.h"
40
#include "llvm/IR/Type.h"
41
#include "llvm/MC/MCInstrDesc.h"
42
#include "llvm/Support/Debug.h"
43
#include "llvm/Support/ErrorHandling.h"
44
#include "llvm/Support/raw_ostream.h"
45
#include "llvm/Target/TargetMachine.h"
46
#include "llvm/Target/TargetOptions.h"
47
#include <cassert>
48
#include <utility>
49
50
#define DEBUG_TYPE "arm-register-info"
51
52
#define GET_REGINFO_TARGET_DESC
53
#include "ARMGenRegisterInfo.inc"
54
55
using namespace llvm;
56
57
ARMBaseRegisterInfo::ARMBaseRegisterInfo()
58
7.46k
    : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
59
60
153k
static unsigned getFramePointerReg(const ARMSubtarget &STI) {
61
153k
  return STI.useR7AsFramePointer() ? 
ARM::R7146k
:
ARM::R116.84k
;
62
153k
}
63
64
const MCPhysReg*
65
435k
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66
435k
  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
67
435k
  bool UseSplitPush = STI.splitFramePushPop(*MF);
68
435k
  const MCPhysReg *RegList =
69
435k
      STI.isTargetDarwin()
70
435k
          ? 
CSR_iOS_SaveList212k
71
435k
          : 
(UseSplitPush 223k
?
CSR_AAPCS_SplitPush_SaveList26.5k
:
CSR_AAPCS_SaveList196k
);
72
435k
73
435k
  const Function &F = MF->getFunction();
74
435k
  if (F.getCallingConv() == CallingConv::GHC) {
75
20
    // GHC set of callee saved regs is empty as all those regs are
76
20
    // used for passing STG regs around
77
20
    return CSR_NoRegs_SaveList;
78
435k
  } else if (F.hasFnAttribute("interrupt")) {
79
198
    if (STI.isMClass()) {
80
66
      // M-class CPUs have hardware which saves the registers needed to allow a
81
66
      // function conforming to the AAPCS to function as a handler.
82
66
      return UseSplitPush ? 
CSR_AAPCS_SplitPush_SaveList0
: CSR_AAPCS_SaveList;
83
132
    } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
84
22
      // Fast interrupt mode gives the handler a private copy of R8-R14, so less
85
22
      // need to be saved to restore user-mode state.
86
22
      return CSR_FIQ_SaveList;
87
110
    } else {
88
110
      // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
89
110
      // exception handling.
90
110
      return CSR_GenericInt_SaveList;
91
110
    }
92
435k
  }
93
435k
94
435k
  if (STI.getTargetLowering()->supportSwiftError() &&
95
435k
      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
96
1.12k
    if (STI.isTargetDarwin())
97
657
      return CSR_iOS_SwiftError_SaveList;
98
469
99
469
    return UseSplitPush ? 
CSR_AAPCS_SplitPush_SwiftError_SaveList0
:
100
469
      CSR_AAPCS_SwiftError_SaveList;
101
469
  }
102
434k
103
434k
  if (STI.isTargetDarwin() && 
F.getCallingConv() == CallingConv::CXX_FAST_TLS212k
)
104
341
    return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
105
341
               ? 
CSR_iOS_CXX_TLS_PE_SaveList181
106
341
               : 
CSR_iOS_CXX_TLS_SaveList160
;
107
434k
  return RegList;
108
434k
}
109
110
const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
111
23.8k
    const MachineFunction *MF) const {
112
23.8k
  assert(MF && "Invalid MachineFunction pointer.");
113
23.8k
  if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
114
23.8k
      
MF->getInfo<ARMFunctionInfo>()->isSplitCSR()46
)
115
30
    return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
116
23.8k
  return nullptr;
117
23.8k
}
118
119
const uint32_t *
120
ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
121
58.3k
                                          CallingConv::ID CC) const {
122
58.3k
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
123
58.3k
  if (CC == CallingConv::GHC)
124
2
    // This is academic because all GHC calls are (supposed to be) tail calls
125
2
    return CSR_NoRegs_RegMask;
126
58.3k
127
58.3k
  if (STI.getTargetLowering()->supportSwiftError() &&
128
58.3k
      MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
129
39
    return STI.isTargetDarwin() ? 
CSR_iOS_SwiftError_RegMask26
130
39
                                : 
CSR_AAPCS_SwiftError_RegMask13
;
131
58.3k
132
58.3k
  if (STI.isTargetDarwin() && 
CC == CallingConv::CXX_FAST_TLS49.3k
)
133
28
    return CSR_iOS_CXX_TLS_RegMask;
134
58.3k
  return STI.isTargetDarwin() ? 
CSR_iOS_RegMask49.3k
:
CSR_AAPCS_RegMask8.95k
;
135
58.3k
}
136
137
const uint32_t*
138
1
ARMBaseRegisterInfo::getNoPreservedMask() const {
139
1
  return CSR_NoRegs_RegMask;
140
1
}
141
142
const uint32_t *
143
79
ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
144
79
  assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
145
79
         "only know about special TLS call on Darwin");
146
79
  return CSR_iOS_TLSCall_RegMask;
147
79
}
148
149
const uint32_t *
150
32
ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
151
32
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
152
32
  if (!STI.useSoftFloat() && STI.hasVFP2Base() && 
!STI.isThumb1Only()27
)
153
27
    return CSR_NoRegs_RegMask;
154
5
  else
155
5
    return CSR_FPRegs_RegMask;
156
32
}
157
158
const uint32_t *
159
ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
160
987
                                                CallingConv::ID CC) const {
161
987
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
162
987
  // This should return a register mask that is the same as that returned by
163
987
  // getCallPreservedMask but that additionally preserves the register used for
164
987
  // the first i32 argument (which must also be the register used to return a
165
987
  // single i32 return value)
166
987
  //
167
987
  // In case that the calling convention does not use the same register for
168
987
  // both or otherwise does not want to enable this optimization, the function
169
987
  // should return NULL
170
987
  if (CC == CallingConv::GHC)
171
0
    // This is academic because all GHC calls are (supposed to be) tail calls
172
0
    return nullptr;
173
987
  return STI.isTargetDarwin() ? 
CSR_iOS_ThisReturn_RegMask965
174
987
                              : 
CSR_AAPCS_ThisReturn_RegMask22
;
175
987
}
176
177
BitVector ARMBaseRegisterInfo::
178
82.2k
getReservedRegs(const MachineFunction &MF) const {
179
82.2k
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
180
82.2k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
181
82.2k
182
82.2k
  // FIXME: avoid re-calculating this every time.
183
82.2k
  BitVector Reserved(getNumRegs());
184
82.2k
  markSuperRegs(Reserved, ARM::SP);
185
82.2k
  markSuperRegs(Reserved, ARM::PC);
186
82.2k
  markSuperRegs(Reserved, ARM::FPSCR);
187
82.2k
  markSuperRegs(Reserved, ARM::APSR_NZCV);
188
82.2k
  if (TFI->hasFP(MF))
189
32.9k
    markSuperRegs(Reserved, getFramePointerReg(STI));
190
82.2k
  if (hasBasePointer(MF))
191
126
    markSuperRegs(Reserved, BasePtr);
192
82.2k
  // Some targets reserve R9.
193
82.2k
  if (STI.isR9Reserved())
194
1.88k
    markSuperRegs(Reserved, ARM::R9);
195
82.2k
  // Reserve D16-D31 if the subtarget doesn't support them.
196
82.2k
  if (!STI.hasD32()) {
197
24.9k
    static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
198
424k
    for (unsigned R = 0; R < 16; 
++R399k
)
199
399k
      markSuperRegs(Reserved, ARM::D16 + R);
200
24.9k
  }
201
82.2k
  const TargetRegisterClass &RC = ARM::GPRPairRegClass;
202
82.2k
  for (unsigned Reg : RC)
203
1.72M
    
for (MCSubRegIterator SI(Reg, this); 575k
SI.isValid();
++SI1.15M
)
204
1.15M
      if (Reserved.test(*SI))
205
117k
        markSuperRegs(Reserved, Reg);
206
82.2k
  // For v8.1m architecture
207
82.2k
  markSuperRegs(Reserved, ARM::ZR);
208
82.2k
209
82.2k
  assert(checkAllSuperRegsMarked(Reserved));
210
82.2k
  return Reserved;
211
82.2k
}
212
213
bool ARMBaseRegisterInfo::
214
416
isAsmClobberable(const MachineFunction &MF, unsigned PhysReg) const {
215
416
  return !getReservedRegs(MF).test(PhysReg);
216
416
}
217
218
const TargetRegisterClass *
219
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
220
64.6k
                                               const MachineFunction &) const {
221
64.6k
  const TargetRegisterClass *Super = RC;
222
64.6k
  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
223
117k
  do {
224
117k
    switch (Super->getID()) {
225
117k
    case ARM::GPRRegClassID:
226
60.5k
    case ARM::SPRRegClassID:
227
60.5k
    case ARM::DPRRegClassID:
228
60.5k
    case ARM::QPRRegClassID:
229
60.5k
    case ARM::QQPRRegClassID:
230
60.5k
    case ARM::QQQQPRRegClassID:
231
60.5k
    case ARM::GPRPairRegClassID:
232
60.5k
      return Super;
233
56.6k
    }
234
56.6k
    Super = *I++;
235
56.6k
  } while (Super);
236
64.6k
  
return RC4.09k
;
237
64.6k
}
238
239
const TargetRegisterClass *
240
ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
241
235
                                                                         const {
242
235
  return &ARM::GPRRegClass;
243
235
}
244
245
const TargetRegisterClass *
246
14
ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
247
14
  if (RC == &ARM::CCRRegClass)
248
14
    return &ARM::rGPRRegClass;  // Can't copy CCR registers.
249
0
  return RC;
250
0
}
251
252
unsigned
253
ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
254
7.87M
                                         MachineFunction &MF) const {
255
7.87M
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
256
7.87M
  const ARMFrameLowering *TFI = getFrameLowering(MF);
257
7.87M
258
7.87M
  switch (RC->getID()) {
259
7.87M
  default:
260
7.61M
    return 0;
261
7.87M
  case ARM::tGPRRegClassID: {
262
64.5k
    // hasFP ends up calling getMaxCallFrameComputed() which may not be
263
64.5k
    // available when getPressureLimit() is called as part of
264
64.5k
    // ScheduleDAGRRList.
265
64.5k
    bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
266
64.5k
                 ? 
TFI->hasFP(MF)0
: true;
267
64.5k
    return 5 - HasFP;
268
7.87M
  }
269
7.87M
  case ARM::GPRRegClassID: {
270
64.5k
    bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
271
64.5k
                 ? 
TFI->hasFP(MF)0
: true;
272
64.5k
    return 10 - HasFP - (STI.isR9Reserved() ? 
1135
:
064.3k
);
273
7.87M
  }
274
7.87M
  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
275
129k
  case ARM::DPRRegClassID:
276
129k
    return 32 - 10;
277
7.87M
  }
278
7.87M
}
279
280
// Get the other register in a GPRPair.
281
1.20k
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
282
1.20k
  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); 
++Supers0
)
283
1.02k
    if (ARM::GPRPairRegClass.contains(*Supers))
284
1.02k
      return RI->getSubReg(*Supers, Odd ? 
ARM::gsub_1549
:
ARM::gsub_0480
);
285
1.20k
  
return 0171
;
286
1.20k
}
287
288
// Resolve the RegPairEven / RegPairOdd register allocator hints.
289
bool
290
ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
291
                                           ArrayRef<MCPhysReg> Order,
292
                                           SmallVectorImpl<MCPhysReg> &Hints,
293
                                           const MachineFunction &MF,
294
                                           const VirtRegMap *VRM,
295
381k
                                           const LiveRegMatrix *Matrix) const {
296
381k
  const MachineRegisterInfo &MRI = MF.getRegInfo();
297
381k
  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
298
381k
299
381k
  unsigned Odd;
300
381k
  switch (Hint.first) {
301
381k
  case ARMRI::RegPairEven:
302
91
    Odd = 0;
303
91
    break;
304
381k
  case ARMRI::RegPairOdd:
305
95
    Odd = 1;
306
95
    break;
307
381k
  default:
308
381k
    TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
309
381k
    return false;
310
186
  }
311
186
312
186
  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
313
186
  // Check if the other part of the pair has already been assigned, and provide
314
186
  // the paired register as the first hint.
315
186
  unsigned Paired = Hint.second;
316
186
  if (Paired == 0)
317
0
    return false;
318
186
319
186
  unsigned PairedPhys = 0;
320
186
  if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
321
0
    PairedPhys = Paired;
322
186
  } else if (VRM && VRM->hasPhys(Paired)) {
323
70
    PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
324
70
  }
325
186
326
186
  // First prefer the paired physreg.
327
186
  if (PairedPhys && 
is_contained(Order, PairedPhys)70
)
328
70
    Hints.push_back(PairedPhys);
329
186
330
186
  // Then prefer even or odd registers.
331
2.38k
  for (unsigned Reg : Order) {
332
2.38k
    if (Reg == PairedPhys || 
(getEncodingValue(Reg) & 1) != Odd2.31k
)
333
1.25k
      continue;
334
1.13k
    // Don't provide hints that are paired to a reserved register.
335
1.13k
    unsigned Paired = getPairedGPR(Reg, !Odd, this);
336
1.13k
    if (!Paired || 
MRI.isReserved(Paired)959
)
337
262
      continue;
338
868
    Hints.push_back(Reg);
339
868
  }
340
186
  return false;
341
186
}
342
343
void
344
ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
345
137k
                                        MachineFunction &MF) const {
346
137k
  MachineRegisterInfo *MRI = &MF.getRegInfo();
347
137k
  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
348
137k
  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
349
137k
       
Hint.first == (unsigned)ARMRI::RegPairEven136k
) &&
350
137k
      
TargetRegisterInfo::isVirtualRegister(Hint.second)46
) {
351
46
    // If 'Reg' is one of the even / odd register pair and it's now changed
352
46
    // (e.g. coalesced) into a different register. The other register of the
353
46
    // pair allocation hint must be updated to reflect the relationship
354
46
    // change.
355
46
    unsigned OtherReg = Hint.second;
356
46
    Hint = MRI->getRegAllocationHint(OtherReg);
357
46
    // Make sure the pair has not already divorced.
358
46
    if (Hint.second == Reg) {
359
46
      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
360
46
      if (TargetRegisterInfo::isVirtualRegister(NewReg))
361
46
        MRI->setRegAllocationHint(NewReg,
362
46
            Hint.first == (unsigned)ARMRI::RegPairOdd ? 
ARMRI::RegPairEven23
363
46
            : 
ARMRI::RegPairOdd23
, OtherReg);
364
46
    }
365
46
  }
366
137k
}
367
368
177k
bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
369
177k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
370
177k
  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
371
177k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
372
177k
373
177k
  // If we have stack realignment and VLAs, we have no pointer to use to
374
177k
  // access the stack. If we have stack realignment, and a large call frame,
375
177k
  // we have no place to allocate the emergency spill slot.
376
177k
  if (needsStackRealignment(MF) && 
!TFI->hasReservedCallFrame(MF)1.88k
)
377
47
    return true;
378
177k
379
177k
  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
380
177k
  // negative range for ldr/str (255), and thumb1 is positive offsets only.
381
177k
  //
382
177k
  // It's going to be better to use the SP or Base Pointer instead. When there
383
177k
  // are variable sized objects, we can't reference off of the SP, so we
384
177k
  // reserve a Base Pointer.
385
177k
  //
386
177k
  // For Thumb2, estimate whether a negative offset from the frame pointer
387
177k
  // will be sufficient to reach the whole stack frame. If a function has a
388
177k
  // smallish frame, it's less likely to have lots of spills and callee saved
389
177k
  // space, so it's all more likely to be within range of the frame pointer.
390
177k
  // If it's wrong, the scavenger will still enable access to work, it just
391
177k
  // won't be optimal.  (We should always be able to reach the emergency
392
177k
  // spill slot from the frame pointer.)
393
177k
  if (AFI->isThumb2Function() && 
MFI.hasVarSizedObjects()109k
&&
394
177k
      
MFI.getLocalFrameSize() >= 128544
)
395
0
    return true;
396
177k
  // For Thumb1, if sp moves, nothing is in range, so force a base pointer.
397
177k
  // This is necessary for correctness in cases where we need an emergency
398
177k
  // spill slot. (In Thumb1, we can't use a negative offset from the frame
399
177k
  // pointer.)
400
177k
  if (AFI->isThumb1OnlyFunction() && 
!TFI->hasReservedCallFrame(MF)14.3k
)
401
322
    return true;
402
177k
  return false;
403
177k
}
404
405
28.9k
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
406
28.9k
  const MachineRegisterInfo *MRI = &MF.getRegInfo();
407
28.9k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
408
28.9k
  // We can't realign the stack if:
409
28.9k
  // 1. Dynamic stack realignment is explicitly disabled,
410
28.9k
  // 2. There are VLAs in the function and the base pointer is disabled.
411
28.9k
  if (!TargetRegisterInfo::canRealignStack(MF))
412
1
    return false;
413
28.9k
  // Stack realignment requires a frame pointer.  If we already started
414
28.9k
  // register allocation with frame pointer elimination, it is too late now.
415
28.9k
  if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
416
1.04k
    return false;
417
27.9k
  // We may also need a base pointer if there are dynamic allocas or stack
418
27.9k
  // pointer adjustments around calls.
419
27.9k
  if (TFI->hasReservedCallFrame(MF))
420
27.2k
    return true;
421
712
  // A base pointer is required and allowed.  Check that it isn't too late to
422
712
  // reserve it.
423
712
  return MRI->canReserveReg(BasePtr);
424
712
}
425
426
bool ARMBaseRegisterInfo::
427
15.1k
cannotEliminateFrame(const MachineFunction &MF) const {
428
15.1k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
429
15.1k
  if (MF.getTarget().Options.DisableFramePointerElim(MF) && 
MFI.adjustsStack()3.58k
)
430
17
    return true;
431
15.1k
  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
432
15.1k
    || 
needsStackRealignment(MF)15.0k
;
433
15.1k
}
434
435
Register
436
142k
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
437
142k
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
438
142k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
439
142k
440
142k
  if (TFI->hasFP(MF))
441
91.2k
    return getFramePointerReg(STI);
442
51.1k
  return ARM::SP;
443
51.1k
}
444
445
/// emitLoadConstPool - Emits a load from constpool to materialize the
446
/// specified immediate.
447
void ARMBaseRegisterInfo::emitLoadConstPool(
448
    MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
449
    const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
450
0
    ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
451
0
  MachineFunction &MF = *MBB.getParent();
452
0
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
453
0
  MachineConstantPool *ConstantPool = MF.getConstantPool();
454
0
  const Constant *C =
455
0
        ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), Val);
456
0
  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
457
0
458
0
  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
459
0
      .addReg(DestReg, getDefRegState(true), SubIdx)
460
0
      .addConstantPoolIndex(Idx)
461
0
      .addImm(0)
462
0
      .add(predOps(Pred, PredReg))
463
0
      .setMIFlags(MIFlags);
464
0
}
465
466
bool ARMBaseRegisterInfo::
467
76.7k
requiresRegisterScavenging(const MachineFunction &MF) const {
468
76.7k
  return true;
469
76.7k
}
470
471
bool ARMBaseRegisterInfo::
472
57.1k
trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
473
57.1k
  return true;
474
57.1k
}
475
476
bool ARMBaseRegisterInfo::
477
26.5k
requiresFrameIndexScavenging(const MachineFunction &MF) const {
478
26.5k
  return true;
479
26.5k
}
480
481
bool ARMBaseRegisterInfo::
482
26.5k
requiresVirtualBaseRegisters(const MachineFunction &MF) const {
483
26.5k
  return true;
484
26.5k
}
485
486
int64_t ARMBaseRegisterInfo::
487
45.8k
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
488
45.8k
  const MCInstrDesc &Desc = MI->getDesc();
489
45.8k
  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
490
45.8k
  int64_t InstrOffs = 0;
491
45.8k
  int Scale = 1;
492
45.8k
  unsigned ImmIdx = 0;
493
45.8k
  switch (AddrMode) {
494
45.8k
  case ARMII::AddrModeT2_i8:
495
44.1k
  case ARMII::AddrModeT2_i12:
496
44.1k
  case ARMII::AddrMode_i12:
497
44.1k
    InstrOffs = MI->getOperand(Idx+1).getImm();
498
44.1k
    Scale = 1;
499
44.1k
    break;
500
44.1k
  case ARMII::AddrMode5: {
501
598
    // VFP address mode.
502
598
    const MachineOperand &OffOp = MI->getOperand(Idx+1);
503
598
    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
504
598
    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
505
0
      InstrOffs = -InstrOffs;
506
598
    Scale = 4;
507
598
    break;
508
44.1k
  }
509
44.1k
  case ARMII::AddrMode2:
510
0
    ImmIdx = Idx+2;
511
0
    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
512
0
    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
513
0
      InstrOffs = -InstrOffs;
514
0
    break;
515
44.1k
  case ARMII::AddrMode3:
516
61
    ImmIdx = Idx+2;
517
61
    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
518
61
    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
519
0
      InstrOffs = -InstrOffs;
520
61
    break;
521
44.1k
  case ARMII::AddrModeT1_s:
522
995
    ImmIdx = Idx+1;
523
995
    InstrOffs = MI->getOperand(ImmIdx).getImm();
524
995
    Scale = 4;
525
995
    break;
526
44.1k
  default:
527
0
    llvm_unreachable("Unsupported addressing mode!");
528
45.8k
  }
529
45.8k
530
45.8k
  return InstrOffs * Scale;
531
45.8k
}
532
533
/// needsFrameBaseReg - Returns true if the instruction's frame index
534
/// reference would be better served by a base register other than FP
535
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
536
/// references it should create new base registers for.
537
bool ARMBaseRegisterInfo::
538
40.9k
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
539
81.9k
  for (unsigned i = 0; !MI->getOperand(i).isFI(); 
++i40.9k
) {
540
40.9k
    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
541
40.9k
  }
542
40.9k
543
40.9k
  // It's the load/store FI references that cause issues, as it can be difficult
544
40.9k
  // to materialize the offset if it won't fit in the literal field. Estimate
545
40.9k
  // based on the size of the local frame and some conservative assumptions
546
40.9k
  // about the rest of the stack frame (note, this is pre-regalloc, so
547
40.9k
  // we don't know everything for certain yet) whether this offset is likely
548
40.9k
  // to be out of range of the immediate. Return true if so.
549
40.9k
550
40.9k
  // We only generate virtual base registers for loads and stores, so
551
40.9k
  // return false for everything else.
552
40.9k
  unsigned Opc = MI->getOpcode();
553
40.9k
  switch (Opc) {
554
40.9k
  
case ARM::LDRi12: 29.5k
case ARM::LDRH: 29.5k
case ARM::LDRBi12:
555
29.5k
  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
556
29.5k
  case ARM::t2LDRi12: case ARM::t2LDRi8:
557
29.5k
  case ARM::t2STRi12: case ARM::t2STRi8:
558
29.5k
  case ARM::VLDRS: case ARM::VLDRD:
559
29.5k
  case ARM::VSTRS: case ARM::VSTRD:
560
29.5k
  case ARM::tSTRspi: case ARM::tLDRspi:
561
29.5k
    break;
562
29.5k
  default:
563
11.3k
    return false;
564
29.5k
  }
565
29.5k
566
29.5k
  // Without a virtual base register, if the function has variable sized
567
29.5k
  // objects, all fixed-size local references will be via the frame pointer,
568
29.5k
  // Approximate the offset and see if it's legal for the instruction.
569
29.5k
  // Note that the incoming offset is based on the SP value at function entry,
570
29.5k
  // so it'll be negative.
571
29.5k
  MachineFunction &MF = *MI->getParent()->getParent();
572
29.5k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
573
29.5k
  MachineFrameInfo &MFI = MF.getFrameInfo();
574
29.5k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
575
29.5k
576
29.5k
  // Estimate an offset from the frame pointer.
577
29.5k
  // Conservatively assume all callee-saved registers get pushed. R4-R6
578
29.5k
  // will be earlier than the FP, so we ignore those.
579
29.5k
  // R7, LR
580
29.5k
  int64_t FPOffset = Offset - 8;
581
29.5k
  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
582
29.5k
  if (!AFI->isThumbFunction() || 
!AFI->isThumb1OnlyFunction()26.8k
)
583
28.6k
    FPOffset -= 80;
584
29.5k
  // Estimate an offset from the stack pointer.
585
29.5k
  // The incoming offset is relating to the SP at the start of the function,
586
29.5k
  // but when we access the local it'll be relative to the SP after local
587
29.5k
  // allocation, so adjust our SP-relative offset by that allocation size.
588
29.5k
  Offset += MFI.getLocalFrameSize();
589
29.5k
  // Assume that we'll have at least some spill slots allocated.
590
29.5k
  // FIXME: This is a total SWAG number. We should run some statistics
591
29.5k
  //        and pick a real one.
592
29.5k
  Offset += 128; // 128 bytes of spill slots
593
29.5k
594
29.5k
  // If there's a frame pointer and the addressing mode allows it, try using it.
595
29.5k
  // The FP is only available if there is no dynamic realignment. We
596
29.5k
  // don't know for sure yet whether we'll need that, so we guess based
597
29.5k
  // on whether there are any local variables that would trigger it.
598
29.5k
  unsigned StackAlign = TFI->getStackAlignment();
599
29.5k
  if (TFI->hasFP(MF) &&
600
29.5k
      
!(26.5k
(MFI.getLocalFrameMaxAlign() > StackAlign)26.5k
&&
canRealignStack(MF)1.04k
)) {
601
25.4k
    if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
602
9.29k
      return false;
603
20.2k
  }
604
20.2k
  // If we can reference via the stack pointer, try that.
605
20.2k
  // FIXME: This (and the code that resolves the references) can be improved
606
20.2k
  //        to only disallow SP relative references in the live range of
607
20.2k
  //        the VLA(s). In practice, it's unclear how much difference that
608
20.2k
  //        would make, but it may be worth doing.
609
20.2k
  if (!MFI.hasVarSizedObjects() && 
isFrameOffsetLegal(MI, ARM::SP, Offset)20.2k
)
610
20.2k
    return false;
611
76
612
76
  // The offset likely isn't legal, we want to allocate a virtual base register.
613
76
  return true;
614
76
}
615
616
/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
617
/// be a pointer to FrameIdx at the beginning of the basic block.
618
void ARMBaseRegisterInfo::
619
materializeFrameBaseRegister(MachineBasicBlock *MBB,
620
                             unsigned BaseReg, int FrameIdx,
621
8
                             int64_t Offset) const {
622
8
  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
623
8
  unsigned ADDriOpc = !AFI->isThumbFunction() ? 
ARM::ADDri2
:
624
8
    
(AFI->isThumb1OnlyFunction() 6
?
ARM::tADDframe5
:
ARM::t2ADDri1
);
625
8
626
8
  MachineBasicBlock::iterator Ins = MBB->begin();
627
8
  DebugLoc DL;                  // Defaults to "unknown"
628
8
  if (Ins != MBB->end())
629
8
    DL = Ins->getDebugLoc();
630
8
631
8
  const MachineFunction &MF = *MBB->getParent();
632
8
  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
633
8
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
634
8
  const MCInstrDesc &MCID = TII.get(ADDriOpc);
635
8
  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
636
8
637
8
  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
638
8
    .addFrameIndex(FrameIdx).addImm(Offset);
639
8
640
8
  if (!AFI->isThumb1OnlyFunction())
641
3
    MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
642
8
}
643
644
void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
645
32
                                            int64_t Offset) const {
646
32
  MachineBasicBlock &MBB = *MI.getParent();
647
32
  MachineFunction &MF = *MBB.getParent();
648
32
  const ARMBaseInstrInfo &TII =
649
32
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
650
32
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
651
32
  int Off = Offset; // ARM doesn't need the general 64-bit offsets
652
32
  unsigned i = 0;
653
32
654
32
  assert(!AFI->isThumb1OnlyFunction() &&
655
32
         "This resolveFrameIndex does not support Thumb1!");
656
32
657
64
  while (!MI.getOperand(i).isFI()) {
658
32
    ++i;
659
32
    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
660
32
  }
661
32
  bool Done = false;
662
32
  if (!AFI->isThumbFunction())
663
17
    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
664
15
  else {
665
15
    assert(AFI->isThumb2Function());
666
15
    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
667
15
  }
668
32
  assert(Done && "Unable to resolve frame index!");
669
32
  (void)Done;
670
32
}
671
672
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
673
45.8k
                                             int64_t Offset) const {
674
45.8k
  const MCInstrDesc &Desc = MI->getDesc();
675
45.8k
  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
676
45.8k
  unsigned i = 0;
677
91.6k
  for (; !MI->getOperand(i).isFI(); 
++i45.8k
)
678
45.8k
    assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!");
679
45.8k
680
45.8k
  // AddrMode4 and AddrMode6 cannot handle any offset.
681
45.8k
  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
682
0
    return Offset == 0;
683
45.8k
684
45.8k
  unsigned NumBits = 0;
685
45.8k
  unsigned Scale = 1;
686
45.8k
  bool isSigned = true;
687
45.8k
  switch (AddrMode) {
688
45.8k
  case ARMII::AddrModeT2_i8:
689
41.6k
  case ARMII::AddrModeT2_i12:
690
41.6k
    // i8 supports only negative, and i12 supports only positive, so
691
41.6k
    // based on Offset sign, consider the appropriate instruction
692
41.6k
    Scale = 1;
693
41.6k
    if (Offset < 0) {
694
23.9k
      NumBits = 8;
695
23.9k
      Offset = -Offset;
696
23.9k
    } else {
697
17.7k
      NumBits = 12;
698
17.7k
    }
699
41.6k
    break;
700
41.6k
  case ARMII::AddrMode5:
701
593
    // VFP address mode.
702
593
    NumBits = 8;
703
593
    Scale = 4;
704
593
    break;
705
41.6k
  case ARMII::AddrMode_i12:
706
2.51k
  case ARMII::AddrMode2:
707
2.51k
    NumBits = 12;
708
2.51k
    break;
709
2.51k
  case ARMII::AddrMode3:
710
61
    NumBits = 8;
711
61
    break;
712
2.51k
  case ARMII::AddrModeT1_s:
713
969
    NumBits = (BaseReg == ARM::SP ? 
8873
:
596
);
714
969
    Scale = 4;
715
969
    isSigned = false;
716
969
    break;
717
2.51k
  default:
718
0
    llvm_unreachable("Unsupported addressing mode!");
719
45.8k
  }
720
45.8k
721
45.8k
  Offset += getFrameIndexInstrOffset(MI, i);
722
45.8k
  // Make sure the offset is encodable for instructions that scale the
723
45.8k
  // immediate.
724
45.8k
  if ((Offset & (Scale-1)) != 0)
725
3
    return false;
726
45.8k
727
45.8k
  if (isSigned && 
Offset < 044.8k
)
728
1.49k
    Offset = -Offset;
729
45.8k
730
45.8k
  unsigned Mask = (1 << NumBits) - 1;
731
45.8k
  if ((unsigned)Offset <= Mask * Scale)
732
29.5k
    return true;
733
16.2k
734
16.2k
  return false;
735
16.2k
}
736
737
void
738
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
739
                                         int SPAdj, unsigned FIOperandNum,
740
58.5k
                                         RegScavenger *RS) const {
741
58.5k
  MachineInstr &MI = *II;
742
58.5k
  MachineBasicBlock &MBB = *MI.getParent();
743
58.5k
  MachineFunction &MF = *MBB.getParent();
744
58.5k
  const ARMBaseInstrInfo &TII =
745
58.5k
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
746
58.5k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
747
58.5k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
748
58.5k
  assert(!AFI->isThumb1OnlyFunction() &&
749
58.5k
         "This eliminateFrameIndex does not support Thumb1!");
750
58.5k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
751
58.5k
  unsigned FrameReg;
752
58.5k
753
58.5k
  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
754
58.5k
755
58.5k
  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
756
58.5k
  // call frame setup/destroy instructions have already been eliminated.  That
757
58.5k
  // means the stack pointer cannot be used to access the emergency spill slot
758
58.5k
  // when !hasReservedCallFrame().
759
#ifndef NDEBUG
760
  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
761
    assert(TFI->hasReservedCallFrame(MF) &&
762
           "Cannot use SP to access the emergency spill slot in "
763
           "functions without a reserved call frame");
764
    assert(!MF.getFrameInfo().hasVarSizedObjects() &&
765
           "Cannot use SP to access the emergency spill slot in "
766
           "functions with variable sized frame objects");
767
  }
768
#endif // NDEBUG
769
770
58.5k
  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
771
58.5k
772
58.5k
  // Modify MI as necessary to handle as much of 'Offset' as possible
773
58.5k
  bool Done = false;
774
58.5k
  if (!AFI->isThumbFunction())
775
8.01k
    Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
776
50.5k
  else {
777
50.5k
    assert(AFI->isThumb2Function());
778
50.5k
    Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
779
50.5k
  }
780
58.5k
  if (Done)
781
57.0k
    return;
782
1.52k
783
1.52k
  // If we get here, the immediate doesn't fit into the instruction.  We folded
784
1.52k
  // as much as possible above, handle the rest, providing a register that is
785
1.52k
  // SP+LargeImm.
786
1.52k
  assert((Offset ||
787
1.52k
          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
788
1.52k
          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
789
1.52k
         "This code isn't needed if offset already handled!");
790
1.52k
791
1.52k
  unsigned ScratchReg = 0;
792
1.52k
  int PIdx = MI.findFirstPredOperandIdx();
793
1.52k
  ARMCC::CondCodes Pred = (PIdx == -1)
794
1.52k
    ? 
ARMCC::AL0
: (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
795
1.52k
  Register PredReg = (PIdx == -1) ? 
Register()0
: MI.getOperand(PIdx+1).getReg();
796
1.52k
  if (Offset == 0)
797
12
    // Must be addrmode4/6.
798
12
    MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
799
1.51k
  else {
800
1.51k
    ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
801
1.51k
    if (!AFI->isThumbFunction())
802
391
      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
803
391
                              Offset, Pred, PredReg, TII);
804
1.11k
    else {
805
1.11k
      assert(AFI->isThumb2Function());
806
1.11k
      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
807
1.11k
                             Offset, Pred, PredReg, TII);
808
1.11k
    }
809
1.51k
    // Update the original instruction to use the scratch register.
810
1.51k
    MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
811
1.51k
  }
812
1.52k
}
813
814
bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
815
                                  const TargetRegisterClass *SrcRC,
816
                                  unsigned SubReg,
817
                                  const TargetRegisterClass *DstRC,
818
                                  unsigned DstSubReg,
819
                                  const TargetRegisterClass *NewRC,
820
135k
                                  LiveIntervals &LIS) const {
821
135k
  auto MBB = MI->getParent();
822
135k
  auto MF = MBB->getParent();
823
135k
  const MachineRegisterInfo &MRI = MF->getRegInfo();
824
135k
  // If not copying into a sub-register this should be ok because we shouldn't
825
135k
  // need to split the reg.
826
135k
  if (!DstSubReg)
827
131k
    return true;
828
4.67k
  // Small registers don't frequently cause a problem, so we can coalesce them.
829
4.67k
  if (getRegSizeInBits(*NewRC) < 256 && 
getRegSizeInBits(*DstRC) < 2564.23k
&&
830
4.67k
      
getRegSizeInBits(*SrcRC) < 2564.23k
)
831
4.23k
    return true;
832
446
833
446
  auto NewRCWeight =
834
446
              MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
835
446
  auto SrcRCWeight =
836
446
              MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
837
446
  auto DstRCWeight =
838
446
              MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
839
446
  // If the source register class is more expensive than the destination, the
840
446
  // coalescing is probably profitable.
841
446
  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
842
0
    return true;
843
446
  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
844
0
    return true;
845
446
846
446
  // If the register allocator isn't constrained, we can always allow coalescing
847
446
  // unfortunately we don't know yet if we will be constrained.
848
446
  // The goal of this heuristic is to restrict how many expensive registers
849
446
  // we allow to coalesce in a given basic block.
850
446
  auto AFI = MF->getInfo<ARMFunctionInfo>();
851
446
  auto It = AFI->getCoalescedWeight(MBB);
852
446
853
446
  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
854
446
                    << It->second << "\n");
855
446
  LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
856
446
                    << NewRCWeight.RegWeight << "\n");
857
446
858
446
  // This number is the largest round number that which meets the criteria:
859
446
  //  (1) addresses PR18825
860
446
  //  (2) generates better code in some test cases (like vldm-shed-a9.ll)
861
446
  //  (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
862
446
  // In practice the SizeMultiplier will only factor in for straight line code
863
446
  // that uses a lot of NEON vectors, which isn't terribly common.
864
446
  unsigned SizeMultiplier = MBB->size()/100;
865
446
  SizeMultiplier = SizeMultiplier ? 
SizeMultiplier1
:
1445
;
866
446
  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
867
435
    It->second += NewRCWeight.RegWeight;
868
435
    return true;
869
435
  }
870
11
  return false;
871
11
}