Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMCallLowering.cpp
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//===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
7
//===----------------------------------------------------------------------===//
8
//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMCallLowering.h"
16
#include "ARMBaseInstrInfo.h"
17
#include "ARMISelLowering.h"
18
#include "ARMSubtarget.h"
19
#include "Utils/ARMBaseInfo.h"
20
#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/Analysis.h"
22
#include "llvm/CodeGen/CallingConvLower.h"
23
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24
#include "llvm/CodeGen/GlobalISel/Utils.h"
25
#include "llvm/CodeGen/LowLevelType.h"
26
#include "llvm/CodeGen/MachineBasicBlock.h"
27
#include "llvm/CodeGen/MachineFrameInfo.h"
28
#include "llvm/CodeGen/MachineFunction.h"
29
#include "llvm/CodeGen/MachineInstrBuilder.h"
30
#include "llvm/CodeGen/MachineMemOperand.h"
31
#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
33
#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DataLayout.h"
38
#include "llvm/IR/DerivedTypes.h"
39
#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/Casting.h"
43
#include "llvm/Support/LowLevelTypeImpl.h"
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#include "llvm/Support/MachineValueType.h"
45
#include <algorithm>
46
#include <cassert>
47
#include <cstdint>
48
#include <utility>
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using namespace llvm;
51
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ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53
7.46k
    : CallLowering(&TLI) {}
54
55
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56
2.25k
                            Type *T) {
57
2.25k
  if (T->isArrayTy())
58
94
    return isSupportedType(DL, TLI, T->getArrayElementType());
59
2.16k
60
2.16k
  if (T->isStructTy()) {
61
45
    // For now we only allow homogeneous structs that we can manipulate with
62
45
    // G_MERGE_VALUES and G_UNMERGE_VALUES
63
45
    auto StructT = cast<StructType>(T);
64
100
    for (unsigned i = 1, e = StructT->getNumElements(); i != e; 
++i55
)
65
60
      if (StructT->getElementType(i) != StructT->getElementType(0))
66
5
        return false;
67
45
    
return isSupportedType(DL, TLI, StructT->getElementType(0))40
;
68
2.12k
  }
69
2.12k
70
2.12k
  EVT VT = TLI.getValueType(DL, T, true);
71
2.12k
  if (!VT.isSimple() || 
VT.isVector()2.11k
||
72
2.12k
      
!(2.10k
VT.isInteger()2.10k
||
VT.isFloatingPoint()947
))
73
20
    return false;
74
2.10k
75
2.10k
  unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76
2.10k
77
2.10k
  if (VTSize == 64)
78
467
    // FIXME: Support i64 too
79
467
    return VT.isFloatingPoint();
80
1.63k
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1.63k
  return VTSize == 1 || 
VTSize == 81.60k
||
VTSize == 161.47k
||
VTSize == 321.32k
;
82
1.63k
}
83
84
namespace {
85
86
/// Helper class for values going out through an ABI boundary (used for handling
87
/// function return values and call parameters).
88
struct OutgoingValueHandler : public CallLowering::ValueHandler {
89
  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90
                       MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91
729
      : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92
93
  Register getStackAddress(uint64_t Size, int64_t Offset,
94
160
                           MachinePointerInfo &MPO) override {
95
160
    assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
96
160
           "Unsupported size");
97
160
98
160
    LLT p0 = LLT::pointer(0, 32);
99
160
    LLT s32 = LLT::scalar(32);
100
160
    Register SPReg = MRI.createGenericVirtualRegister(p0);
101
160
    MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
102
160
103
160
    Register OffsetReg = MRI.createGenericVirtualRegister(s32);
104
160
    MIRBuilder.buildConstant(OffsetReg, Offset);
105
160
106
160
    Register AddrReg = MRI.createGenericVirtualRegister(p0);
107
160
    MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
108
160
109
160
    MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
110
160
    return AddrReg;
111
160
  }
112
113
  void assignValueToReg(Register ValVReg, Register PhysReg,
114
1.36k
                        CCValAssign &VA) override {
115
1.36k
    assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
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1.36k
    assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
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1.36k
118
1.36k
    assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
119
1.36k
    assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
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1.36k
121
1.36k
    Register ExtReg = extendRegister(ValVReg, VA);
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1.36k
    MIRBuilder.buildCopy(PhysReg, ExtReg);
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1.36k
    MIB.addUse(PhysReg, RegState::Implicit);
124
1.36k
  }
125
126
  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
127
160
                            MachinePointerInfo &MPO, CCValAssign &VA) override {
128
160
    assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
129
160
           "Unsupported size");
130
160
131
160
    Register ExtReg = extendRegister(ValVReg, VA);
132
160
    auto MMO = MIRBuilder.getMF().getMachineMemOperand(
133
160
        MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
134
160
        /* Alignment */ 1);
135
160
    MIRBuilder.buildStore(ExtReg, Addr, *MMO);
136
160
  }
137
138
  unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
139
251
                             ArrayRef<CCValAssign> VAs) override {
140
251
    assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
141
251
142
251
    CCValAssign VA = VAs[0];
143
251
    assert(VA.needsCustom() && "Value doesn't need custom handling");
144
251
    assert(VA.getValVT() == MVT::f64 && "Unsupported type");
145
251
146
251
    CCValAssign NextVA = VAs[1];
147
251
    assert(NextVA.needsCustom() && "Value doesn't need custom handling");
148
251
    assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
149
251
150
251
    assert(VA.getValNo() == NextVA.getValNo() &&
151
251
           "Values belong to different arguments");
152
251
153
251
    assert(VA.isRegLoc() && "Value should be in reg");
154
251
    assert(NextVA.isRegLoc() && "Value should be in reg");
155
251
156
251
    Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
157
251
                          MRI.createGenericVirtualRegister(LLT::scalar(32))};
158
251
    MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
159
251
160
251
    bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
161
251
    if (!IsLittle)
162
7
      std::swap(NewRegs[0], NewRegs[1]);
163
251
164
251
    assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
165
251
    assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
166
251
167
251
    return 1;
168
251
  }
169
170
  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
171
                 CCValAssign::LocInfo LocInfo,
172
1.28k
                 const CallLowering::ArgInfo &Info, CCState &State) override {
173
1.28k
    if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State))
174
5
      return true;
175
1.27k
176
1.27k
    StackSize =
177
1.27k
        std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
178
1.27k
    return false;
179
1.27k
  }
180
181
  MachineInstrBuilder &MIB;
182
  uint64_t StackSize = 0;
183
};
184
185
} // end anonymous namespace
186
187
void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
188
                                        SmallVectorImpl<ArgInfo> &SplitArgs,
189
2.07k
                                        MachineFunction &MF) const {
190
2.07k
  const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
191
2.07k
  LLVMContext &Ctx = OrigArg.Ty->getContext();
192
2.07k
  const DataLayout &DL = MF.getDataLayout();
193
2.07k
  const Function &F = MF.getFunction();
194
2.07k
195
2.07k
  SmallVector<EVT, 4> SplitVTs;
196
2.07k
  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
197
2.07k
  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
198
2.07k
199
2.07k
  if (SplitVTs.size() == 1) {
200
1.95k
    // Even if there is no splitting to do, we still want to replace the
201
1.95k
    // original type (e.g. pointer type -> integer).
202
1.95k
    auto Flags = OrigArg.Flags;
203
1.95k
    unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
204
1.95k
    Flags.setOrigAlign(OriginalAlignment);
205
1.95k
    SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
206
1.95k
                           Flags, OrigArg.IsFixed);
207
1.95k
    return;
208
1.95k
  }
209
118
210
118
  // Create one ArgInfo for each virtual register.
211
727
  
for (unsigned i = 0, e = SplitVTs.size(); 118
i != e;
++i609
) {
212
609
    EVT SplitVT = SplitVTs[i];
213
609
    Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
214
609
    auto Flags = OrigArg.Flags;
215
609
216
609
    unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
217
609
    Flags.setOrigAlign(OriginalAlignment);
218
609
219
609
    bool NeedsConsecutiveRegisters =
220
609
        TLI.functionArgumentNeedsConsecutiveRegisters(
221
609
            SplitTy, F.getCallingConv(), F.isVarArg());
222
609
    if (NeedsConsecutiveRegisters) {
223
84
      Flags.setInConsecutiveRegs();
224
84
      if (i == e - 1)
225
24
        Flags.setInConsecutiveRegsLast();
226
84
    }
227
609
228
609
    // FIXME: We also want to split SplitTy further.
229
609
    Register PartReg = OrigArg.Regs[i];
230
609
    SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
231
609
  }
232
118
}
233
234
/// Lower the return value for the already existing \p Ret. This assumes that
235
/// \p MIRBuilder's insertion point is correct.
236
bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
237
                                     const Value *Val, ArrayRef<Register> VRegs,
238
346
                                     MachineInstrBuilder &Ret) const {
239
346
  if (!Val)
240
22
    // Nothing to do here.
241
22
    return true;
242
324
243
324
  auto &MF = MIRBuilder.getMF();
244
324
  const auto &F = MF.getFunction();
245
324
246
324
  auto DL = MF.getDataLayout();
247
324
  auto &TLI = *getTLI<ARMTargetLowering>();
248
324
  if (!isSupportedType(DL, TLI, Val->getType()))
249
0
    return false;
250
324
251
324
  ArgInfo OrigRetInfo(VRegs, Val->getType());
252
324
  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
253
324
254
324
  SmallVector<ArgInfo, 4> SplitRetInfos;
255
324
  splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
256
324
257
324
  CCAssignFn *AssignFn =
258
324
      TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
259
324
260
324
  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
261
324
  return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
262
324
}
263
264
bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
265
                                  const Value *Val,
266
346
                                  ArrayRef<Register> VRegs) const {
267
346
  assert(!Val == VRegs.empty() && "Return value without a vreg");
268
346
269
346
  auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
270
346
  unsigned Opcode = ST.getReturnOpcode();
271
346
  auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
272
346
273
346
  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
274
5
    return false;
275
341
276
341
  MIRBuilder.insertInstr(Ret);
277
341
  return true;
278
341
}
279
280
namespace {
281
282
/// Helper class for values coming in through an ABI boundary (used for handling
283
/// formal arguments and call return values).
284
struct IncomingValueHandler : public CallLowering::ValueHandler {
285
  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
286
                       CCAssignFn AssignFn)
287
627
      : ValueHandler(MIRBuilder, MRI, AssignFn) {}
288
289
923
  bool isArgumentHandler() const override { return true; }
290
291
  Register getStackAddress(uint64_t Size, int64_t Offset,
292
181
                           MachinePointerInfo &MPO) override {
293
181
    assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
294
181
           "Unsupported size");
295
181
296
181
    auto &MFI = MIRBuilder.getMF().getFrameInfo();
297
181
298
181
    int FI = MFI.CreateFixedObject(Size, Offset, true);
299
181
    MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
300
181
301
181
    unsigned AddrReg =
302
181
        MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
303
181
    MIRBuilder.buildFrameIndex(AddrReg, FI);
304
181
305
181
    return AddrReg;
306
181
  }
307
308
  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
309
181
                            MachinePointerInfo &MPO, CCValAssign &VA) override {
310
181
    assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
311
181
           "Unsupported size");
312
181
313
181
    if (VA.getLocInfo() == CCValAssign::SExt ||
314
181
        
VA.getLocInfo() == CCValAssign::ZExt172
) {
315
14
      // If the value is zero- or sign-extended, its size becomes 4 bytes, so
316
14
      // that's what we should load.
317
14
      Size = 4;
318
14
      assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
319
14
320
14
      auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
321
14
      buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
322
14
      MIRBuilder.buildTrunc(ValVReg, LoadVReg);
323
167
    } else {
324
167
      // If the value is not extended, a simple load will suffice.
325
167
      buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
326
167
    }
327
181
  }
328
329
  void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
330
181
                 MachinePointerInfo &MPO) {
331
181
    auto MMO = MIRBuilder.getMF().getMachineMemOperand(
332
181
        MPO, MachineMemOperand::MOLoad, Size, Alignment);
333
181
    MIRBuilder.buildLoad(Val, Addr, *MMO);
334
181
  }
335
336
  void assignValueToReg(Register ValVReg, Register PhysReg,
337
1.09k
                        CCValAssign &VA) override {
338
1.09k
    assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
339
1.09k
    assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
340
1.09k
341
1.09k
    auto ValSize = VA.getValVT().getSizeInBits();
342
1.09k
    auto LocSize = VA.getLocVT().getSizeInBits();
343
1.09k
344
1.09k
    assert(ValSize <= 64 && "Unsupported value size");
345
1.09k
    assert(LocSize <= 64 && "Unsupported location size");
346
1.09k
347
1.09k
    markPhysRegUsed(PhysReg);
348
1.09k
    if (ValSize == LocSize) {
349
927
      MIRBuilder.buildCopy(ValVReg, PhysReg);
350
927
    } else {
351
168
      assert(ValSize < LocSize && "Extensions not supported");
352
168
353
168
      // We cannot create a truncating copy, nor a trunc of a physical register.
354
168
      // Therefore, we need to copy the content of the physical register into a
355
168
      // virtual one and then truncate that.
356
168
      auto PhysRegToVReg =
357
168
          MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
358
168
      MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
359
168
      MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
360
168
    }
361
1.09k
  }
362
363
  unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
364
96
                             ArrayRef<CCValAssign> VAs) override {
365
96
    assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
366
96
367
96
    CCValAssign VA = VAs[0];
368
96
    assert(VA.needsCustom() && "Value doesn't need custom handling");
369
96
    assert(VA.getValVT() == MVT::f64 && "Unsupported type");
370
96
371
96
    CCValAssign NextVA = VAs[1];
372
96
    assert(NextVA.needsCustom() && "Value doesn't need custom handling");
373
96
    assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
374
96
375
96
    assert(VA.getValNo() == NextVA.getValNo() &&
376
96
           "Values belong to different arguments");
377
96
378
96
    assert(VA.isRegLoc() && "Value should be in reg");
379
96
    assert(NextVA.isRegLoc() && "Value should be in reg");
380
96
381
96
    Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
382
96
                          MRI.createGenericVirtualRegister(LLT::scalar(32))};
383
96
384
96
    assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
385
96
    assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
386
96
387
96
    bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
388
96
    if (!IsLittle)
389
8
      std::swap(NewRegs[0], NewRegs[1]);
390
96
391
96
    MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
392
96
393
96
    return 1;
394
96
  }
395
396
  /// Marking a physical register as used is different between formal
397
  /// parameters, where it's a basic block live-in, and call returns, where it's
398
  /// an implicit-def of the call instruction.
399
  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
400
};
401
402
struct FormalArgHandler : public IncomingValueHandler {
403
  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
404
                   CCAssignFn AssignFn)
405
238
      : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
406
407
621
  void markPhysRegUsed(unsigned PhysReg) override {
408
621
    MIRBuilder.getMBB().addLiveIn(PhysReg);
409
621
  }
410
};
411
412
} // end anonymous namespace
413
414
bool ARMCallLowering::lowerFormalArguments(
415
    MachineIRBuilder &MIRBuilder, const Function &F,
416
417
    ArrayRef<ArrayRef<Register>> VRegs) const {
417
417
  auto &TLI = *getTLI<ARMTargetLowering>();
418
417
  auto Subtarget = TLI.getSubtarget();
419
417
420
417
  if (Subtarget->isThumb1Only())
421
5
    return false;
422
412
423
412
  // Quick exit if there aren't any args
424
412
  if (F.arg_empty())
425
124
    return true;
426
288
427
288
  if (F.isVarArg())
428
5
    return false;
429
283
430
283
  auto &MF = MIRBuilder.getMF();
431
283
  auto &MBB = MIRBuilder.getMBB();
432
283
  auto DL = MF.getDataLayout();
433
283
434
639
  for (auto &Arg : F.args()) {
435
639
    if (!isSupportedType(DL, TLI, Arg.getType()))
436
40
      return false;
437
599
    if (Arg.hasByValOrInAllocaAttr())
438
5
      return false;
439
599
  }
440
283
441
283
  CCAssignFn *AssignFn =
442
238
      TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
443
238
444
238
  FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
445
238
                              AssignFn);
446
238
447
238
  SmallVector<ArgInfo, 8> SplitArgInfos;
448
238
  unsigned Idx = 0;
449
594
  for (auto &Arg : F.args()) {
450
594
    ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
451
594
452
594
    setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
453
594
    splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
454
594
455
594
    Idx++;
456
594
  }
457
238
458
238
  if (!MBB.empty())
459
0
    MIRBuilder.setInstr(*MBB.begin());
460
238
461
238
  if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
462
0
    return false;
463
238
464
238
  // Move back to the end of the basic block.
465
238
  MIRBuilder.setMBB(MBB);
466
238
  return true;
467
238
}
468
469
namespace {
470
471
struct CallReturnHandler : public IncomingValueHandler {
472
  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
473
                    MachineInstrBuilder MIB, CCAssignFn *AssignFn)
474
389
      : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
475
476
474
  void markPhysRegUsed(unsigned PhysReg) override {
477
474
    MIB.addDef(PhysReg, RegState::Implicit);
478
474
  }
479
480
  MachineInstrBuilder MIB;
481
};
482
483
// FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
484
410
unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
485
410
  if (isDirect)
486
404
    return STI.isThumb() ? 
ARM::tBL156
:
ARM::BL248
;
487
6
488
6
  if (STI.isThumb())
489
2
    return ARM::tBLXr;
490
4
491
4
  if (STI.hasV5TOps())
492
2
    return ARM::BLX;
493
2
494
2
  if (STI.hasV4TOps())
495
1
    return ARM::BX_CALL;
496
1
497
1
  return ARM::BMOVPCRX_CALL;
498
1
}
499
} // end anonymous namespace
500
501
bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
502
                                CallingConv::ID CallConv,
503
                                const MachineOperand &Callee,
504
                                const ArgInfo &OrigRet,
505
410
                                ArrayRef<ArgInfo> OrigArgs) const {
506
410
  MachineFunction &MF = MIRBuilder.getMF();
507
410
  const auto &TLI = *getTLI<ARMTargetLowering>();
508
410
  const auto &DL = MF.getDataLayout();
509
410
  const auto &STI = MF.getSubtarget<ARMSubtarget>();
510
410
  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
511
410
  MachineRegisterInfo &MRI = MF.getRegInfo();
512
410
513
410
  if (STI.genLongCalls())
514
0
    return false;
515
410
516
410
  if (STI.isThumb1Only())
517
0
    return false;
518
410
519
410
  auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
520
410
521
410
  // Create the call instruction so we can add the implicit uses of arg
522
410
  // registers, but don't insert it yet.
523
410
  bool IsDirect = !Callee.isReg();
524
410
  auto CallOpcode = getCallOpcode(STI, IsDirect);
525
410
  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
526
410
527
410
  bool IsThumb = STI.isThumb();
528
410
  if (IsThumb)
529
158
    MIB.add(predOps(ARMCC::AL));
530
410
531
410
  MIB.add(Callee);
532
410
  if (!IsDirect) {
533
6
    auto CalleeReg = Callee.getReg();
534
6
    if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) {
535
6
      unsigned CalleeIdx = IsThumb ? 
22
:
04
;
536
6
      MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
537
6
          MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
538
6
          *MIB.getInstr(), MIB->getDesc(), Callee, CalleeIdx));
539
6
    }
540
6
  }
541
410
542
410
  MIB.addRegMask(TRI->getCallPreservedMask(MF, CallConv));
543
410
544
410
  bool IsVarArg = false;
545
410
  SmallVector<ArgInfo, 8> ArgInfos;
546
773
  for (auto Arg : OrigArgs) {
547
773
    if (!isSupportedType(DL, TLI, Arg.Ty))
548
0
      return false;
549
773
550
773
    if (!Arg.IsFixed)
551
14
      IsVarArg = true;
552
773
553
773
    if (Arg.Flags.isByVal())
554
5
      return false;
555
768
556
768
    splitToValueTypes(Arg, ArgInfos, MF);
557
768
  }
558
410
559
410
  auto ArgAssignFn = TLI.CCAssignFnForCall(CallConv, IsVarArg);
560
405
  OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
561
405
  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
562
0
    return false;
563
405
564
405
  // Now we can add the actual call instruction to the correct basic block.
565
405
  MIRBuilder.insertInstr(MIB);
566
405
567
405
  if (!OrigRet.Ty->isVoidTy()) {
568
389
    if (!isSupportedType(DL, TLI, OrigRet.Ty))
569
0
      return false;
570
389
571
389
    ArgInfos.clear();
572
389
    splitToValueTypes(OrigRet, ArgInfos, MF);
573
389
    auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
574
389
    CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
575
389
    if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
576
10
      return false;
577
395
  }
578
395
579
395
  // We now know the size of the stack - update the ADJCALLSTACKDOWN
580
395
  // accordingly.
581
395
  CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
582
395
583
395
  MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
584
395
      .addImm(ArgHandler.StackSize)
585
395
      .addImm(0)
586
395
      .add(predOps(ARMCC::AL));
587
395
588
395
  return true;
589
395
}