Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMFrameLowering.cpp
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Source (jump to first uncovered line)
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//===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the ARM implementation of TargetFrameLowering class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARMFrameLowering.h"
14
#include "ARMBaseInstrInfo.h"
15
#include "ARMBaseRegisterInfo.h"
16
#include "ARMConstantPoolValue.h"
17
#include "ARMMachineFunctionInfo.h"
18
#include "ARMSubtarget.h"
19
#include "MCTargetDesc/ARMAddressingModes.h"
20
#include "MCTargetDesc/ARMBaseInfo.h"
21
#include "Utils/ARMBaseInfo.h"
22
#include "llvm/ADT/BitVector.h"
23
#include "llvm/ADT/STLExtras.h"
24
#include "llvm/ADT/SmallPtrSet.h"
25
#include "llvm/ADT/SmallVector.h"
26
#include "llvm/CodeGen/MachineBasicBlock.h"
27
#include "llvm/CodeGen/MachineConstantPool.h"
28
#include "llvm/CodeGen/MachineFrameInfo.h"
29
#include "llvm/CodeGen/MachineFunction.h"
30
#include "llvm/CodeGen/MachineInstr.h"
31
#include "llvm/CodeGen/MachineInstrBuilder.h"
32
#include "llvm/CodeGen/MachineJumpTableInfo.h"
33
#include "llvm/CodeGen/MachineModuleInfo.h"
34
#include "llvm/CodeGen/MachineOperand.h"
35
#include "llvm/CodeGen/MachineRegisterInfo.h"
36
#include "llvm/CodeGen/RegisterScavenging.h"
37
#include "llvm/CodeGen/TargetInstrInfo.h"
38
#include "llvm/CodeGen/TargetOpcodes.h"
39
#include "llvm/CodeGen/TargetRegisterInfo.h"
40
#include "llvm/CodeGen/TargetSubtargetInfo.h"
41
#include "llvm/IR/Attributes.h"
42
#include "llvm/IR/CallingConv.h"
43
#include "llvm/IR/DebugLoc.h"
44
#include "llvm/IR/Function.h"
45
#include "llvm/MC/MCContext.h"
46
#include "llvm/MC/MCDwarf.h"
47
#include "llvm/MC/MCInstrDesc.h"
48
#include "llvm/MC/MCRegisterInfo.h"
49
#include "llvm/Support/CodeGen.h"
50
#include "llvm/Support/CommandLine.h"
51
#include "llvm/Support/Compiler.h"
52
#include "llvm/Support/Debug.h"
53
#include "llvm/Support/ErrorHandling.h"
54
#include "llvm/Support/MathExtras.h"
55
#include "llvm/Support/raw_ostream.h"
56
#include "llvm/Target/TargetMachine.h"
57
#include "llvm/Target/TargetOptions.h"
58
#include <algorithm>
59
#include <cassert>
60
#include <cstddef>
61
#include <cstdint>
62
#include <iterator>
63
#include <utility>
64
#include <vector>
65
66
#define DEBUG_TYPE "arm-frame-lowering"
67
68
using namespace llvm;
69
70
static cl::opt<bool>
71
SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
72
                     cl::desc("Align ARM NEON spills in prolog and epilog"));
73
74
static MachineBasicBlock::iterator
75
skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
76
                        unsigned NumAlignedDPRCS2Regs);
77
78
ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
79
    : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
80
7.46k
      STI(sti) {}
81
82
1.31M
bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const {
83
1.31M
  // iOS always has a FP for backtracking, force other targets to keep their FP
84
1.31M
  // when doing FastISel. The emitted code is currently superior, and in cases
85
1.31M
  // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
86
1.31M
  return MF.getSubtarget<ARMSubtarget>().useFastISel();
87
1.31M
}
88
89
/// Returns true if the target can safely skip saving callee-saved registers
90
/// for noreturn nounwind functions.
91
36
bool ARMFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const {
92
36
  assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
93
36
         MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
94
36
         !MF.getFunction().hasFnAttribute(Attribute::UWTable));
95
36
96
36
  // Frame pointer and link register are not treated as normal CSR, thus we
97
36
  // can always skip CSR saves for nonreturning functions.
98
36
  return true;
99
36
}
100
101
/// hasFP - Return true if the specified function should have a dedicated frame
102
/// pointer register.  This is true if the function has variable sized allocas
103
/// or if frame pointer elimination is disabled.
104
441k
bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
105
441k
  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
106
441k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
107
441k
108
441k
  // ABI-required frame pointer.
109
441k
  if (MF.getTarget().Options.DisableFramePointerElim(MF))
110
262k
    return true;
111
179k
112
179k
  // Frame pointer required for use within this function.
113
179k
  return (RegInfo->needsStackRealignment(MF) ||
114
179k
          
MFI.hasVarSizedObjects()176k
||
115
179k
          
MFI.isFrameAddressTaken()175k
);
116
179k
}
117
118
/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
119
/// not required, we reserve argument space for call sites in the function
120
/// immediately on entry to the current function.  This eliminates the need for
121
/// add/sub sp brackets around call sites.  Returns true if the call frame is
122
/// included as part of the stack frame.
123
341k
bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
124
341k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
125
341k
  unsigned CFSize = MFI.getMaxCallFrameSize();
126
341k
  // It's not always a good idea to include the call frame as part of the
127
341k
  // stack frame. ARM (especially Thumb) has small immediate offset to
128
341k
  // address the stack frame. So a large call frame can cause poor codegen
129
341k
  // and may even makes it impossible to scavenge a register.
130
341k
  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
131
1.28k
    return false;
132
340k
133
340k
  return !MFI.hasVarSizedObjects();
134
340k
}
135
136
/// canSimplifyCallFramePseudos - If there is a reserved call frame, the
137
/// call frame pseudos can be simplified.  Unlike most targets, having a FP
138
/// is not sufficient here since we still may reference some objects via SP
139
/// even when FP is available in Thumb2 mode.
140
bool
141
126k
ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
142
126k
  return hasReservedCallFrame(MF) || 
MF.getFrameInfo().hasVarSizedObjects()1.70k
;
143
126k
}
144
145
static bool isCSRestore(MachineInstr &MI, const ARMBaseInstrInfo &TII,
146
24.1k
                        const MCPhysReg *CSRegs) {
147
24.1k
  // Integer spill area is handled with "pop".
148
24.1k
  if (isPopOpcode(MI.getOpcode())) {
149
5.97k
    // The first two operands are predicates. The last two are
150
5.97k
    // imp-def and imp-use of SP. Check everything in between.
151
20.2k
    for (int i = 5, e = MI.getNumOperands(); i != e; 
++i14.2k
)
152
14.2k
      if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
153
0
        return false;
154
5.97k
    return true;
155
18.1k
  }
156
18.1k
  if ((MI.getOpcode() == ARM::LDR_POST_IMM ||
157
18.1k
       
MI.getOpcode() == ARM::LDR_POST_REG17.9k
||
158
18.1k
       
MI.getOpcode() == ARM::t2LDR_POST17.9k
) &&
159
18.1k
      
isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs)1.65k
&&
160
18.1k
      
MI.getOperand(1).getReg() == ARM::SP1.65k
)
161
1.65k
    return true;
162
16.5k
163
16.5k
  return false;
164
16.5k
}
165
166
static void emitRegPlusImmediate(
167
    bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
168
    const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
169
    unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
170
20.4k
    ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
171
20.4k
  if (isARM)
172
2.34k
    emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
173
2.34k
                            Pred, PredReg, TII, MIFlags);
174
18.1k
  else
175
18.1k
    emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
176
18.1k
                           Pred, PredReg, TII, MIFlags);
177
20.4k
}
178
179
static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
180
                         MachineBasicBlock::iterator &MBBI, const DebugLoc &dl,
181
                         const ARMBaseInstrInfo &TII, int NumBytes,
182
                         unsigned MIFlags = MachineInstr::NoFlags,
183
                         ARMCC::CondCodes Pred = ARMCC::AL,
184
13.1k
                         unsigned PredReg = 0) {
185
13.1k
  emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
186
13.1k
                       MIFlags, Pred, PredReg);
187
13.1k
}
188
189
7.77k
static int sizeOfSPAdjustment(const MachineInstr &MI) {
190
7.77k
  int RegSize;
191
7.77k
  switch (MI.getOpcode()) {
192
7.77k
  case ARM::VSTMDDB_UPD:
193
424
    RegSize = 8;
194
424
    break;
195
7.77k
  case ARM::STMDB_UPD:
196
7.34k
  case ARM::t2STMDB_UPD:
197
7.34k
    RegSize = 4;
198
7.34k
    break;
199
7.34k
  case ARM::t2STR_PRE:
200
8
  case ARM::STR_PRE_IMM:
201
8
    return 4;
202
8
  default:
203
0
    llvm_unreachable("Unknown push or pop like instruction");
204
7.77k
  }
205
7.77k
206
7.77k
  int count = 0;
207
7.77k
  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
208
7.77k
  // pred) so the list starts at 4.
209
38.7k
  for (int i = MI.getNumOperands() - 1; i >= 4; 
--i30.9k
)
210
30.9k
    count += RegSize;
211
7.77k
  return count;
212
7.77k
}
213
214
static bool WindowsRequiresStackProbe(const MachineFunction &MF,
215
347
                                      size_t StackSizeInBytes) {
216
347
  const MachineFrameInfo &MFI = MF.getFrameInfo();
217
347
  const Function &F = MF.getFunction();
218
347
  unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 
40800
: 4096;
219
347
  if (F.hasFnAttribute("stack-probe-size"))
220
4
    F.getFnAttribute("stack-probe-size")
221
4
        .getValueAsString()
222
4
        .getAsInteger(0, StackProbeSize);
223
347
  return (StackSizeInBytes >= StackProbeSize) &&
224
347
         
!F.hasFnAttribute("no-stack-arg-probe")8
;
225
347
}
226
227
namespace {
228
229
struct StackAdjustingInsts {
230
  struct InstInfo {
231
    MachineBasicBlock::iterator I;
232
    unsigned SPAdjust;
233
    bool BeforeFPSet;
234
  };
235
236
  SmallVector<InstInfo, 4> Insts;
237
238
  void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
239
20.6k
               bool BeforeFPSet = false) {
240
20.6k
    InstInfo Info = {I, SPAdjust, BeforeFPSet};
241
20.6k
    Insts.push_back(Info);
242
20.6k
  }
243
244
117
  void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
245
117
    auto Info =
246
154
        llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
247
117
    assert(Info != Insts.end() && "invalid sp adjusting instruction");
248
117
    Info->SPAdjust += ExtraBytes;
249
117
  }
250
251
  void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
252
24.9k
                         const ARMBaseInstrInfo &TII, bool HasFP) {
253
24.9k
    MachineFunction &MF = *MBB.getParent();
254
24.9k
    unsigned CFAOffset = 0;
255
24.9k
    for (auto &Info : Insts) {
256
17.9k
      if (HasFP && 
!Info.BeforeFPSet13.0k
)
257
5.52k
        return;
258
12.3k
259
12.3k
      CFAOffset -= Info.SPAdjust;
260
12.3k
      unsigned CFIIndex = MF.addFrameInst(
261
12.3k
          MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
262
12.3k
      BuildMI(MBB, std::next(Info.I), dl,
263
12.3k
              TII.get(TargetOpcode::CFI_INSTRUCTION))
264
12.3k
              .addCFIIndex(CFIIndex)
265
12.3k
              .setMIFlags(MachineInstr::FrameSetup);
266
12.3k
    }
267
24.9k
  }
268
};
269
270
} // end anonymous namespace
271
272
/// Emit an instruction sequence that will align the address in
273
/// register Reg by zero-ing out the lower bits.  For versions of the
274
/// architecture that support Neon, this must be done in a single
275
/// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
276
/// single instruction. That function only gets called when optimizing
277
/// spilling of D registers on a core with the Neon instruction set
278
/// present.
279
static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
280
                                     const TargetInstrInfo &TII,
281
                                     MachineBasicBlock &MBB,
282
                                     MachineBasicBlock::iterator MBBI,
283
                                     const DebugLoc &DL, const unsigned Reg,
284
                                     const unsigned Alignment,
285
278
                                     const bool MustBeSingleInstruction) {
286
278
  const ARMSubtarget &AST =
287
278
      static_cast<const ARMSubtarget &>(MF.getSubtarget());
288
278
  const bool CanUseBFC = AST.hasV6T2Ops() || 
AST.hasV7Ops()15
;
289
278
  const unsigned AlignMask = Alignment - 1;
290
278
  const unsigned NrBitsToZero = countTrailingZeros(Alignment);
291
278
  assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
292
278
  if (!AFI->isThumbFunction()) {
293
114
    // if the BFC instruction is available, use that to zero the lower
294
114
    // bits:
295
114
    //   bfc Reg, #0, log2(Alignment)
296
114
    // otherwise use BIC, if the mask to zero the required number of bits
297
114
    // can be encoded in the bic immediate field
298
114
    //   bic Reg, Reg, Alignment-1
299
114
    // otherwise, emit
300
114
    //   lsr Reg, Reg, log2(Alignment)
301
114
    //   lsl Reg, Reg, log2(Alignment)
302
114
    if (CanUseBFC) {
303
99
      BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
304
99
          .addReg(Reg, RegState::Kill)
305
99
          .addImm(~AlignMask)
306
99
          .add(predOps(ARMCC::AL));
307
99
    } else 
if (15
AlignMask <= 25515
) {
308
13
      BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
309
13
          .addReg(Reg, RegState::Kill)
310
13
          .addImm(AlignMask)
311
13
          .add(predOps(ARMCC::AL))
312
13
          .add(condCodeOp());
313
13
    } else {
314
2
      assert(!MustBeSingleInstruction &&
315
2
             "Shouldn't call emitAligningInstructions demanding a single "
316
2
             "instruction to be emitted for large stack alignment for a target "
317
2
             "without BFC.");
318
2
      BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
319
2
          .addReg(Reg, RegState::Kill)
320
2
          .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
321
2
          .add(predOps(ARMCC::AL))
322
2
          .add(condCodeOp());
323
2
      BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
324
2
          .addReg(Reg, RegState::Kill)
325
2
          .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
326
2
          .add(predOps(ARMCC::AL))
327
2
          .add(condCodeOp());
328
2
    }
329
164
  } else {
330
164
    // Since this is only reached for Thumb-2 targets, the BFC instruction
331
164
    // should always be available.
332
164
    assert(CanUseBFC);
333
164
    BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
334
164
        .addReg(Reg, RegState::Kill)
335
164
        .addImm(~AlignMask)
336
164
        .add(predOps(ARMCC::AL));
337
164
  }
338
278
}
339
340
/// We need the offset of the frame pointer relative to other MachineFrameInfo
341
/// offsets which are encoded relative to SP at function begin.
342
/// See also emitPrologue() for how the FP is set up.
343
/// Unfortunately we cannot determine this value in determineCalleeSaves() yet
344
/// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use
345
/// this to produce a conservative estimate that we check in an assert() later.
346
34.2k
static int getMaxFPOffset(const Function &F, const ARMFunctionInfo &AFI) {
347
34.2k
  // For Thumb1, push.w isn't available, so the first push will always push
348
34.2k
  // r7 and lr onto the stack first.
349
34.2k
  if (AFI.isThumb1OnlyFunction())
350
1.55k
    return -AFI.getArgRegsSaveSize() - (2 * 4);
351
32.7k
  // This is a conservative estimation: Assume the frame pointer being r7 and
352
32.7k
  // pc("r15") up to r8 getting spilled before (= 8 registers).
353
32.7k
  return -AFI.getArgRegsSaveSize() - (8 * 4);
354
32.7k
}
355
356
void ARMFrameLowering::emitPrologue(MachineFunction &MF,
357
24.9k
                                    MachineBasicBlock &MBB) const {
358
24.9k
  MachineBasicBlock::iterator MBBI = MBB.begin();
359
24.9k
  MachineFrameInfo  &MFI = MF.getFrameInfo();
360
24.9k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
361
24.9k
  MachineModuleInfo &MMI = MF.getMMI();
362
24.9k
  MCContext &Context = MMI.getContext();
363
24.9k
  const TargetMachine &TM = MF.getTarget();
364
24.9k
  const MCRegisterInfo *MRI = Context.getRegisterInfo();
365
24.9k
  const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
366
24.9k
  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
367
24.9k
  assert(!AFI->isThumb1OnlyFunction() &&
368
24.9k
         "This emitPrologue does not support Thumb1!");
369
24.9k
  bool isARM = !AFI->isThumbFunction();
370
24.9k
  unsigned Align = STI.getFrameLowering()->getStackAlignment();
371
24.9k
  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
372
24.9k
  unsigned NumBytes = MFI.getStackSize();
373
24.9k
  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
374
24.9k
375
24.9k
  // Debug location must be unknown since the first debug location is used
376
24.9k
  // to determine the end of the prologue.
377
24.9k
  DebugLoc dl;
378
24.9k
379
24.9k
  unsigned FramePtr = RegInfo->getFrameRegister(MF);
380
24.9k
381
24.9k
  // Determine the sizes of each callee-save spill areas and record which frame
382
24.9k
  // belongs to which callee-save spill areas.
383
24.9k
  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
384
24.9k
  int FramePtrSpillFI = 0;
385
24.9k
  int D8SpillFI = 0;
386
24.9k
387
24.9k
  // All calls are tail calls in GHC calling conv, and functions have no
388
24.9k
  // prologue/epilogue.
389
24.9k
  if (MF.getFunction().getCallingConv() == CallingConv::GHC)
390
2
    return;
391
24.9k
392
24.9k
  StackAdjustingInsts DefCFAOffsetCandidates;
393
24.9k
  bool HasFP = hasFP(MF);
394
24.9k
395
24.9k
  // Allocate the vararg register save area.
396
24.9k
  if (ArgRegsSaveSize) {
397
107
    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
398
107
                 MachineInstr::FrameSetup);
399
107
    DefCFAOffsetCandidates.addInst(std::prev(MBBI), ArgRegsSaveSize, true);
400
107
  }
401
24.9k
402
24.9k
  if (!AFI->hasStackFrame() &&
403
24.9k
      
(14.1k
!STI.isTargetWindows()14.1k
||
!WindowsRequiresStackProbe(MF, NumBytes)70
)) {
404
14.1k
    if (NumBytes - ArgRegsSaveSize != 0) {
405
324
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
406
324
                   MachineInstr::FrameSetup);
407
324
      DefCFAOffsetCandidates.addInst(std::prev(MBBI),
408
324
                                     NumBytes - ArgRegsSaveSize, true);
409
324
    }
410
14.1k
    DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
411
14.1k
    return;
412
14.1k
  }
413
10.8k
414
10.8k
  // Determine spill area sizes.
415
58.7k
  
for (unsigned i = 0, e = CSI.size(); 10.8k
i != e;
++i47.8k
) {
416
47.8k
    unsigned Reg = CSI[i].getReg();
417
47.8k
    int FI = CSI[i].getFrameIdx();
418
47.8k
    switch (Reg) {
419
47.8k
    case ARM::R8:
420
9.07k
    case ARM::R9:
421
9.07k
    case ARM::R10:
422
9.07k
    case ARM::R11:
423
9.07k
    case ARM::R12:
424
9.07k
      if (STI.splitFramePushPop(MF)) {
425
6.57k
        GPRCS2Size += 4;
426
6.57k
        break;
427
6.57k
      }
428
2.49k
      LLVM_FALLTHROUGH;
429
39.3k
    case ARM::R0:
430
39.3k
    case ARM::R1:
431
39.3k
    case ARM::R2:
432
39.3k
    case ARM::R3:
433
39.3k
    case ARM::R4:
434
39.3k
    case ARM::R5:
435
39.3k
    case ARM::R6:
436
39.3k
    case ARM::R7:
437
39.3k
    case ARM::LR:
438
39.3k
      if (Reg == FramePtr)
439
7.35k
        FramePtrSpillFI = FI;
440
39.3k
      GPRCS1Size += 4;
441
39.3k
      break;
442
39.3k
    default:
443
1.89k
      // This is a DPR. Exclude the aligned DPRCS2 spills.
444
1.89k
      if (Reg == ARM::D8)
445
431
        D8SpillFI = FI;
446
1.89k
      if (Reg < ARM::D8 || 
Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()1.76k
)
447
1.54k
        DPRCSSize += 8;
448
47.8k
    }
449
47.8k
  }
450
10.8k
451
10.8k
  // Move past area 1.
452
10.8k
  MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
453
10.8k
  if (GPRCS1Size > 0) {
454
10.8k
    GPRCS1Push = LastPush = MBBI++;
455
10.8k
    DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
456
10.8k
  }
457
10.8k
458
10.8k
  // Determine starting offsets of spill areas.
459
10.8k
  unsigned GPRCS1Offset = NumBytes - ArgRegsSaveSize - GPRCS1Size;
460
10.8k
  unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
461
10.8k
  unsigned DPRAlign = DPRCSSize ? 
std::min(8U, Align)398
:
4U10.4k
;
462
10.8k
  unsigned DPRGapSize = (GPRCS1Size + GPRCS2Size + ArgRegsSaveSize) % DPRAlign;
463
10.8k
  unsigned DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
464
10.8k
  int FramePtrOffsetInPush = 0;
465
10.8k
  if (HasFP) {
466
7.35k
    int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);
467
7.35k
    assert(getMaxFPOffset(MF.getFunction(), *AFI) <= FPOffset &&
468
7.35k
           "Max FP estimation is wrong");
469
7.35k
    FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize;
470
7.35k
    AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
471
7.35k
                                NumBytes);
472
7.35k
  }
473
10.8k
  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
474
10.8k
  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
475
10.8k
  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
476
10.8k
477
10.8k
  // Move past area 2.
478
10.8k
  if (GPRCS2Size > 0) {
479
3.10k
    GPRCS2Push = LastPush = MBBI++;
480
3.10k
    DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
481
3.10k
  }
482
10.8k
483
10.8k
  // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
484
10.8k
  // .cfi_offset operations will reflect that.
485
10.8k
  if (DPRGapSize) {
486
25
    assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
487
25
    if (LastPush != MBB.end() &&
488
25
        
tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize)24
)
489
6
      DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
490
19
    else {
491
19
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
492
19
                   MachineInstr::FrameSetup);
493
19
      DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
494
19
    }
495
25
  }
496
10.8k
497
10.8k
  // Move past area 3.
498
10.8k
  if (DPRCSSize > 0) {
499
398
    // Since vpush register list cannot have gaps, there may be multiple vpush
500
398
    // instructions in the prologue.
501
822
    while (MBBI != MBB.end() && 
MBBI->getOpcode() == ARM::VSTMDDB_UPD821
) {
502
424
      DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
503
424
      LastPush = MBBI++;
504
424
    }
505
398
  }
506
10.8k
507
10.8k
  // Move past the aligned DPRCS2 area.
508
10.8k
  if (AFI->getNumAlignedDPRCS2Regs() > 0) {
509
50
    MBBI = skipAlignedDPRCS2Spills(MBBI, AFI->getNumAlignedDPRCS2Regs());
510
50
    // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
511
50
    // leaves the stack pointer pointing to the DPRCS2 area.
512
50
    //
513
50
    // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
514
50
    NumBytes += MFI.getObjectOffset(D8SpillFI);
515
50
  } else
516
10.8k
    NumBytes = DPRCSOffset;
517
10.8k
518
10.8k
  if (STI.isTargetWindows() && 
WindowsRequiresStackProbe(MF, NumBytes)103
) {
519
3
    uint32_t NumWords = NumBytes >> 2;
520
3
521
3
    if (NumWords < 65536)
522
3
      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
523
3
          .addImm(NumWords)
524
3
          .setMIFlags(MachineInstr::FrameSetup)
525
3
          .add(predOps(ARMCC::AL));
526
0
    else
527
0
      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
528
0
        .addImm(NumWords)
529
0
        .setMIFlags(MachineInstr::FrameSetup);
530
3
531
3
    switch (TM.getCodeModel()) {
532
3
    case CodeModel::Tiny:
533
0
      llvm_unreachable("Tiny code model not available on ARM.");
534
3
    case CodeModel::Small:
535
1
    case CodeModel::Medium:
536
1
    case CodeModel::Kernel:
537
1
      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
538
1
          .add(predOps(ARMCC::AL))
539
1
          .addExternalSymbol("__chkstk")
540
1
          .addReg(ARM::R4, RegState::Implicit)
541
1
          .setMIFlags(MachineInstr::FrameSetup);
542
1
      break;
543
2
    case CodeModel::Large:
544
2
      BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
545
2
        .addExternalSymbol("__chkstk")
546
2
        .setMIFlags(MachineInstr::FrameSetup);
547
2
548
2
      BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
549
2
          .add(predOps(ARMCC::AL))
550
2
          .addReg(ARM::R12, RegState::Kill)
551
2
          .addReg(ARM::R4, RegState::Implicit)
552
2
          .setMIFlags(MachineInstr::FrameSetup);
553
2
      break;
554
3
    }
555
3
556
3
    BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
557
3
        .addReg(ARM::SP, RegState::Kill)
558
3
        .addReg(ARM::R4, RegState::Kill)
559
3
        .setMIFlags(MachineInstr::FrameSetup)
560
3
        .add(predOps(ARMCC::AL))
561
3
        .add(condCodeOp());
562
3
    NumBytes = 0;
563
3
  }
564
10.8k
565
10.8k
  if (NumBytes) {
566
5.87k
    // Adjust SP after all the callee-save spills.
567
5.87k
    if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
568
5.87k
        
tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes)5.84k
)
569
111
      DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
570
5.76k
    else {
571
5.76k
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
572
5.76k
                   MachineInstr::FrameSetup);
573
5.76k
      DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
574
5.76k
    }
575
5.87k
576
5.87k
    if (HasFP && 
isARM5.05k
)
577
308
      // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
578
308
      // Note it's not safe to do this in Thumb2 mode because it would have
579
308
      // taken two instructions:
580
308
      // mov sp, r7
581
308
      // sub sp, #24
582
308
      // If an interrupt is taken between the two instructions, then sp is in
583
308
      // an inconsistent state (pointing to the middle of callee-saved area).
584
308
      // The interrupt handler can end up clobbering the registers.
585
308
      AFI->setShouldRestoreSPFromFP(true);
586
5.87k
  }
587
10.8k
588
10.8k
  // Set FP to point to the stack slot that contains the previous FP.
589
10.8k
  // For iOS, FP is R7, which has now been stored in spill area 1.
590
10.8k
  // Otherwise, if this is not iOS, all the callee-saved registers go
591
10.8k
  // into spill area 1, including the FP in R11.  In either case, it
592
10.8k
  // is in area one and the adjustment needs to take place just after
593
10.8k
  // that push.
594
10.8k
  if (HasFP) {
595
7.35k
    MachineBasicBlock::iterator AfterPush = std::next(GPRCS1Push);
596
7.35k
    unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
597
7.35k
    emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
598
7.35k
                         dl, TII, FramePtr, ARM::SP,
599
7.35k
                         PushSize + FramePtrOffsetInPush,
600
7.35k
                         MachineInstr::FrameSetup);
601
7.35k
    if (FramePtrOffsetInPush + PushSize != 0) {
602
5.60k
      unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
603
5.60k
          nullptr, MRI->getDwarfRegNum(FramePtr, true),
604
5.60k
          -(ArgRegsSaveSize - FramePtrOffsetInPush)));
605
5.60k
      BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
606
5.60k
          .addCFIIndex(CFIIndex)
607
5.60k
          .setMIFlags(MachineInstr::FrameSetup);
608
5.60k
    } else {
609
1.74k
      unsigned CFIIndex =
610
1.74k
          MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
611
1.74k
              nullptr, MRI->getDwarfRegNum(FramePtr, true)));
612
1.74k
      BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
613
1.74k
          .addCFIIndex(CFIIndex)
614
1.74k
          .setMIFlags(MachineInstr::FrameSetup);
615
1.74k
    }
616
7.35k
  }
617
10.8k
618
10.8k
  // Now that the prologue's actual instructions are finalised, we can insert
619
10.8k
  // the necessary DWARF cf instructions to describe the situation. Start by
620
10.8k
  // recording where each register ended up:
621
10.8k
  if (GPRCS1Size > 0) {
622
10.8k
    MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
623
10.8k
    int CFIIndex;
624
47.7k
    for (const auto &Entry : CSI) {
625
47.7k
      unsigned Reg = Entry.getReg();
626
47.7k
      int FI = Entry.getFrameIdx();
627
47.7k
      switch (Reg) {
628
47.7k
      case ARM::R8:
629
9.07k
      case ARM::R9:
630
9.07k
      case ARM::R10:
631
9.07k
      case ARM::R11:
632
9.07k
      case ARM::R12:
633
9.07k
        if (STI.splitFramePushPop(MF))
634
6.57k
          break;
635
2.49k
        LLVM_FALLTHROUGH;
636
39.3k
      case ARM::R0:
637
39.3k
      case ARM::R1:
638
39.3k
      case ARM::R2:
639
39.3k
      case ARM::R3:
640
39.3k
      case ARM::R4:
641
39.3k
      case ARM::R5:
642
39.3k
      case ARM::R6:
643
39.3k
      case ARM::R7:
644
39.3k
      case ARM::LR:
645
39.3k
        CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
646
39.3k
            nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
647
39.3k
        BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
648
39.3k
            .addCFIIndex(CFIIndex)
649
39.3k
            .setMIFlags(MachineInstr::FrameSetup);
650
39.3k
        break;
651
47.7k
      }
652
47.7k
    }
653
10.8k
  }
654
10.8k
655
10.8k
  if (GPRCS2Size > 0) {
656
3.10k
    MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
657
22.4k
    for (const auto &Entry : CSI) {
658
22.4k
      unsigned Reg = Entry.getReg();
659
22.4k
      int FI = Entry.getFrameIdx();
660
22.4k
      switch (Reg) {
661
22.4k
      case ARM::R8:
662
6.57k
      case ARM::R9:
663
6.57k
      case ARM::R10:
664
6.57k
      case ARM::R11:
665
6.57k
      case ARM::R12:
666
6.57k
        if (STI.splitFramePushPop(MF)) {
667
6.57k
          unsigned DwarfReg =  MRI->getDwarfRegNum(Reg, true);
668
6.57k
          unsigned Offset = MFI.getObjectOffset(FI);
669
6.57k
          unsigned CFIIndex = MF.addFrameInst(
670
6.57k
              MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
671
6.57k
          BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
672
6.57k
              .addCFIIndex(CFIIndex)
673
6.57k
              .setMIFlags(MachineInstr::FrameSetup);
674
6.57k
        }
675
6.57k
        break;
676
22.4k
      }
677
22.4k
    }
678
3.10k
  }
679
10.8k
680
10.8k
  if (DPRCSSize > 0) {
681
398
    // Since vpush register list cannot have gaps, there may be multiple vpush
682
398
    // instructions in the prologue.
683
398
    MachineBasicBlock::iterator Pos = std::next(LastPush);
684
2.79k
    for (const auto &Entry : CSI) {
685
2.79k
      unsigned Reg = Entry.getReg();
686
2.79k
      int FI = Entry.getFrameIdx();
687
2.79k
      if ((Reg >= ARM::D0 && 
Reg <= ARM::D312.41k
) &&
688
2.79k
          
(1.55k
Reg < ARM::D81.55k
||
Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()1.42k
)) {
689
1.54k
        unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
690
1.54k
        unsigned Offset = MFI.getObjectOffset(FI);
691
1.54k
        unsigned CFIIndex = MF.addFrameInst(
692
1.54k
            MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
693
1.54k
        BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
694
1.54k
            .addCFIIndex(CFIIndex)
695
1.54k
            .setMIFlags(MachineInstr::FrameSetup);
696
1.54k
      }
697
2.79k
    }
698
398
  }
699
10.8k
700
10.8k
  // Now we can emit descriptions of where the canonical frame address was
701
10.8k
  // throughout the process. If we have a frame pointer, it takes over the job
702
10.8k
  // half-way through, so only the first few .cfi_def_cfa_offset instructions
703
10.8k
  // actually get emitted.
704
10.8k
  DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
705
10.8k
706
10.8k
  if (STI.isTargetELF() && 
hasFP(MF)3.04k
)
707
391
    MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
708
391
                            AFI->getFramePtrSpillOffset());
709
10.8k
710
10.8k
  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
711
10.8k
  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
712
10.8k
  AFI->setDPRCalleeSavedGapSize(DPRGapSize);
713
10.8k
  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
714
10.8k
715
10.8k
  // If we need dynamic stack realignment, do it here. Be paranoid and make
716
10.8k
  // sure if we also have VLAs, we have a base pointer for frame access.
717
10.8k
  // If aligned NEON registers were spilled, the stack has already been
718
10.8k
  // realigned.
719
10.8k
  if (!AFI->getNumAlignedDPRCS2Regs() && 
RegInfo->needsStackRealignment(MF)10.8k
) {
720
228
    unsigned MaxAlign = MFI.getMaxAlignment();
721
228
    assert(!AFI->isThumb1OnlyFunction());
722
228
    if (!AFI->isThumbFunction()) {
723
98
      emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
724
98
                               false);
725
130
    } else {
726
130
      // We cannot use sp as source/dest register here, thus we're using r4 to
727
130
      // perform the calculations. We're emitting the following sequence:
728
130
      // mov r4, sp
729
130
      // -- use emitAligningInstructions to produce best sequence to zero
730
130
      // -- out lower bits in r4
731
130
      // mov sp, r4
732
130
      // FIXME: It will be better just to find spare register here.
733
130
      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
734
130
          .addReg(ARM::SP, RegState::Kill)
735
130
          .add(predOps(ARMCC::AL));
736
130
      emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
737
130
                               false);
738
130
      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
739
130
          .addReg(ARM::R4, RegState::Kill)
740
130
          .add(predOps(ARMCC::AL));
741
130
    }
742
228
743
228
    AFI->setShouldRestoreSPFromFP(true);
744
228
  }
745
10.8k
746
10.8k
  // If we need a base pointer, set it up here. It's whatever the value
747
10.8k
  // of the stack pointer is at this point. Any variable size objects
748
10.8k
  // will be allocated after this, so we can still use the base pointer
749
10.8k
  // to reference locals.
750
10.8k
  // FIXME: Clarify FrameSetup flags here.
751
10.8k
  if (RegInfo->hasBasePointer(MF)) {
752
7
    if (isARM)
753
3
      BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
754
3
          .addReg(ARM::SP)
755
3
          .add(predOps(ARMCC::AL))
756
3
          .add(condCodeOp());
757
4
    else
758
4
      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
759
4
          .addReg(ARM::SP)
760
4
          .add(predOps(ARMCC::AL));
761
7
  }
762
10.8k
763
10.8k
  // If the frame has variable sized objects then the epilogue must restore
764
10.8k
  // the sp from fp. We can assume there's an FP here since hasFP already
765
10.8k
  // checks for hasVarSizedObjects.
766
10.8k
  if (MFI.hasVarSizedObjects())
767
66
    AFI->setShouldRestoreSPFromFP(true);
768
10.8k
}
769
770
void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
771
26.0k
                                    MachineBasicBlock &MBB) const {
772
26.0k
  MachineFrameInfo &MFI = MF.getFrameInfo();
773
26.0k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
774
26.0k
  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
775
26.0k
  const ARMBaseInstrInfo &TII =
776
26.0k
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
777
26.0k
  assert(!AFI->isThumb1OnlyFunction() &&
778
26.0k
         "This emitEpilogue does not support Thumb1!");
779
26.0k
  bool isARM = !AFI->isThumbFunction();
780
26.0k
781
26.0k
  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
782
26.0k
  int NumBytes = (int)MFI.getStackSize();
783
26.0k
  unsigned FramePtr = RegInfo->getFrameRegister(MF);
784
26.0k
785
26.0k
  // All calls are tail calls in GHC calling conv, and functions have no
786
26.0k
  // prologue/epilogue.
787
26.0k
  if (MF.getFunction().getCallingConv() == CallingConv::GHC)
788
2
    return;
789
26.0k
790
26.0k
  // First put ourselves on the first (from top) terminator instructions.
791
26.0k
  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
792
26.0k
  DebugLoc dl = MBBI != MBB.end() ? 
MBBI->getDebugLoc()25.9k
:
DebugLoc()127
;
793
26.0k
794
26.0k
  if (!AFI->hasStackFrame()) {
795
14.1k
    if (NumBytes - ArgRegsSaveSize != 0)
796
325
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
797
14.1k
  } else {
798
11.8k
    // Unwind MBBI to point to first LDR / VLDRD.
799
11.8k
    const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
800
11.8k
    if (MBBI != MBB.begin()) {
801
16.9k
      do {
802
16.9k
        --MBBI;
803
16.9k
      } while (MBBI != MBB.begin() && 
isCSRestore(*MBBI, TII, CSRegs)13.7k
);
804
10.4k
      if (!isCSRestore(*MBBI, TII, CSRegs))
805
9.32k
        ++MBBI;
806
10.4k
    }
807
11.8k
808
11.8k
    // Move SP to start of FP callee save spill area.
809
11.8k
    NumBytes -= (ArgRegsSaveSize +
810
11.8k
                 AFI->getGPRCalleeSavedArea1Size() +
811
11.8k
                 AFI->getGPRCalleeSavedArea2Size() +
812
11.8k
                 AFI->getDPRCalleeSavedGapSize() +
813
11.8k
                 AFI->getDPRCalleeSavedAreaSize());
814
11.8k
815
11.8k
    // Reset SP based on frame pointer only if the stack frame extends beyond
816
11.8k
    // frame pointer stack slot or target is ELF and the function has FP.
817
11.8k
    if (AFI->shouldRestoreSPFromFP()) {
818
480
      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
819
480
      if (NumBytes) {
820
357
        if (isARM)
821
152
          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
822
152
                                  ARMCC::AL, 0, TII);
823
205
        else {
824
205
          // It's not possible to restore SP from FP in a single instruction.
825
205
          // For iOS, this looks like:
826
205
          // mov sp, r7
827
205
          // sub sp, #24
828
205
          // This is bad, if an interrupt is taken after the mov, sp is in an
829
205
          // inconsistent state.
830
205
          // Use the first callee-saved register as a scratch register.
831
205
          assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
832
205
                 "No scratch register to restore SP from FP!");
833
205
          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
834
205
                                 ARMCC::AL, 0, TII);
835
205
          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
836
205
              .addReg(ARM::R4)
837
205
              .add(predOps(ARMCC::AL));
838
205
        }
839
357
      } else {
840
123
        // Thumb2 or ARM.
841
123
        if (isARM)
842
123
          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
843
123
              .addReg(FramePtr)
844
123
              .add(predOps(ARMCC::AL))
845
123
              .add(condCodeOp());
846
0
        else
847
0
          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
848
0
              .addReg(FramePtr)
849
0
              .add(predOps(ARMCC::AL));
850
123
      }
851
11.3k
    } else if (NumBytes &&
852
11.3k
               
!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes)6.31k
)
853
6.28k
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
854
11.8k
855
11.8k
    // Increment past our save areas.
856
11.8k
    if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
857
424
      MBBI++;
858
424
      // Since vpop register list cannot have gaps, there may be multiple vpop
859
424
      // instructions in the epilogue.
860
448
      while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
861
24
        MBBI++;
862
424
    }
863
11.8k
    if (AFI->getDPRCalleeSavedGapSize()) {
864
23
      assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
865
23
             "unexpected DPR alignment gap");
866
23
      emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
867
23
    }
868
11.8k
869
11.8k
    if (AFI->getGPRCalleeSavedArea2Size()) 
MBBI++4.03k
;
870
11.8k
    if (AFI->getGPRCalleeSavedArea1Size()) 
MBBI++11.8k
;
871
11.8k
  }
872
26.0k
873
26.0k
  if (ArgRegsSaveSize)
874
107
    emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
875
26.0k
}
876
877
/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
878
/// debug info.  It's the same as what we use for resolving the code-gen
879
/// references for now.  FIXME: This can go wrong when references are
880
/// SP-relative and simple call frames aren't used.
881
int
882
ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
883
21
                                         unsigned &FrameReg) const {
884
21
  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
885
21
}
886
887
int
888
ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
889
                                             int FI, unsigned &FrameReg,
890
62.5k
                                             int SPAdj) const {
891
62.5k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
892
62.5k
  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
893
62.5k
      MF.getSubtarget().getRegisterInfo());
894
62.5k
  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
895
62.5k
  int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
896
62.5k
  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
897
62.5k
  bool isFixed = MFI.isFixedObjectIndex(FI);
898
62.5k
899
62.5k
  FrameReg = ARM::SP;
900
62.5k
  Offset += SPAdj;
901
62.5k
902
62.5k
  // SP can move around if there are allocas.  We may also lose track of SP
903
62.5k
  // when emergency spilling inside a non-reserved call frame setup.
904
62.5k
  bool hasMovingSP = !hasReservedCallFrame(MF);
905
62.5k
906
62.5k
  // When dynamically realigning the stack, use the frame pointer for
907
62.5k
  // parameters, and the stack/base pointer for locals.
908
62.5k
  if (RegInfo->needsStackRealignment(MF)) {
909
8.98k
    assert(hasFP(MF) && "dynamic stack realignment without a FP!");
910
8.98k
    if (isFixed) {
911
122
      FrameReg = RegInfo->getFrameRegister(MF);
912
122
      Offset = FPOffset;
913
8.86k
    } else if (hasMovingSP) {
914
470
      assert(RegInfo->hasBasePointer(MF) &&
915
470
             "VLAs and dynamic stack alignment, but missing base pointer!");
916
470
      FrameReg = RegInfo->getBaseRegister();
917
470
      Offset -= SPAdj;
918
470
    }
919
8.98k
    return Offset;
920
8.98k
  }
921
53.5k
922
53.5k
  // If there is a frame pointer, use it when we can.
923
53.5k
  if (hasFP(MF) && 
AFI->hasStackFrame()42.1k
) {
924
41.8k
    // Use frame pointer to reference fixed objects. Use it for locals if
925
41.8k
    // there are VLAs (and thus the SP isn't reliable as a base).
926
41.8k
    if (isFixed || 
(40.2k
hasMovingSP40.2k
&&
!RegInfo->hasBasePointer(MF)305
)) {
927
1.87k
      FrameReg = RegInfo->getFrameRegister(MF);
928
1.87k
      return FPOffset;
929
39.9k
    } else if (hasMovingSP) {
930
52
      assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
931
52
      if (AFI->isThumb2Function()) {
932
0
        // Try to use the frame pointer if we can, else use the base pointer
933
0
        // since it's available. This is handy for the emergency spill slot, in
934
0
        // particular.
935
0
        if (FPOffset >= -255 && FPOffset < 0) {
936
0
          FrameReg = RegInfo->getFrameRegister(MF);
937
0
          return FPOffset;
938
0
        }
939
39.9k
      }
940
39.9k
    } else if (AFI->isThumbFunction()) {
941
39.1k
      // Prefer SP to base pointer, if the offset is suitably aligned and in
942
39.1k
      // range as the effective range of the immediate offset is bigger when
943
39.1k
      // basing off SP.
944
39.1k
      // Use  add <rd>, sp, #<imm8>
945
39.1k
      //      ldr <rd>, [sp, #<imm8>]
946
39.1k
      if (Offset >= 0 && (Offset & 3) == 0 && 
Offset <= 102038.9k
)
947
37.7k
        return Offset;
948
1.32k
      // In Thumb2 mode, the negative offset is very limited. Try to avoid
949
1.32k
      // out of range references. ldr <rt>,[<rn>, #-<imm8>]
950
1.32k
      if (AFI->isThumb2Function() && 
FPOffset >= -2551.31k
&&
FPOffset < 0712
) {
951
712
        FrameReg = RegInfo->getFrameRegister(MF);
952
712
        return FPOffset;
953
712
      }
954
787
    } else if (Offset > (FPOffset < 0 ? -FPOffset : 
FPOffset0
)) {
955
218
      // Otherwise, use SP or FP, whichever is closer to the stack slot.
956
218
      FrameReg = RegInfo->getFrameRegister(MF);
957
218
      return FPOffset;
958
218
    }
959
12.9k
  }
960
12.9k
  // Use the base pointer if we have one.
961
12.9k
  // FIXME: Maybe prefer sp on Thumb1 if it's legal and the offset is cheaper?
962
12.9k
  // That can happen if we forced a base pointer for a large call frame.
963
12.9k
  if (RegInfo->hasBasePointer(MF)) {
964
70
    FrameReg = RegInfo->getBaseRegister();
965
70
    Offset -= SPAdj;
966
70
  }
967
12.9k
  return Offset;
968
12.9k
}
969
970
void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
971
                                    MachineBasicBlock::iterator MI,
972
                                    const std::vector<CalleeSavedInfo> &CSI,
973
                                    unsigned StmOpc, unsigned StrOpc,
974
                                    bool NoGap,
975
                                    bool(*Func)(unsigned, bool),
976
                                    unsigned NumAlignedDPRCS2Regs,
977
32.6k
                                    unsigned MIFlags) const {
978
32.6k
  MachineFunction &MF = *MBB.getParent();
979
32.6k
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
980
32.6k
  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
981
32.6k
982
32.6k
  DebugLoc DL;
983
32.6k
984
32.6k
  using RegAndKill = std::pair<unsigned, bool>;
985
32.6k
986
32.6k
  SmallVector<RegAndKill, 4> Regs;
987
32.6k
  unsigned i = CSI.size();
988
65.2k
  while (i != 0) {
989
32.6k
    unsigned LastReg = 0;
990
176k
    for (; i != 0; 
--i143k
) {
991
143k
      unsigned Reg = CSI[i-1].getReg();
992
143k
      if (!(Func)(Reg, STI.splitFramePushPop(MF))) 
continue95.7k
;
993
47.8k
994
47.8k
      // D-registers in the aligned area DPRCS2 are NOT spilled here.
995
47.8k
      if (Reg >= ARM::D8 && 
Reg < ARM::D8 + NumAlignedDPRCS2Regs36.9k
)
996
346
        continue;
997
47.5k
998
47.5k
      const MachineRegisterInfo &MRI = MF.getRegInfo();
999
47.5k
      bool isLiveIn = MRI.isLiveIn(Reg);
1000
47.5k
      if (!isLiveIn && 
!MRI.isReserved(Reg)46.9k
)
1001
39.6k
        MBB.addLiveIn(Reg);
1002
47.5k
      // If NoGap is true, push consecutive registers and then leave the rest
1003
47.5k
      // for other instructions. e.g.
1004
47.5k
      // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
1005
47.5k
      if (NoGap && 
LastReg1.57k
&&
LastReg != Reg-11.14k
)
1006
26
        break;
1007
47.5k
      LastReg = Reg;
1008
47.5k
      // Do not set a kill flag on values that are also marked as live-in. This
1009
47.5k
      // happens with the @llvm-returnaddress intrinsic and with arguments
1010
47.5k
      // passed in callee saved registers.
1011
47.5k
      // Omitting the kill flags is conservatively correct even if the live-in
1012
47.5k
      // is not used after all.
1013
47.5k
      Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
1014
47.5k
    }
1015
32.6k
1016
32.6k
    if (Regs.empty())
1017
18.2k
      continue;
1018
14.3k
1019
36.2k
    
llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) 14.3k
{
1020
36.2k
      return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
1021
36.2k
    });
1022
14.3k
1023
14.3k
    if (Regs.size() > 1 || 
StrOpc== 01.52k
) {
1024
12.9k
      MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1025
12.9k
                                    .addReg(ARM::SP)
1026
12.9k
                                    .setMIFlags(MIFlags)
1027
12.9k
                                    .add(predOps(ARMCC::AL));
1028
59.0k
      for (unsigned i = 0, e = Regs.size(); i < e; 
++i46.0k
)
1029
46.0k
        MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1030
12.9k
    } else 
if (1.42k
Regs.size() == 11.42k
) {
1031
1.42k
      BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1032
1.42k
          .addReg(Regs[0].first, getKillRegState(Regs[0].second))
1033
1.42k
          .addReg(ARM::SP)
1034
1.42k
          .setMIFlags(MIFlags)
1035
1.42k
          .addImm(-4)
1036
1.42k
          .add(predOps(ARMCC::AL));
1037
1.42k
    }
1038
14.3k
    Regs.clear();
1039
14.3k
1040
14.3k
    // Put any subsequent vpush instructions before this one: they will refer to
1041
14.3k
    // higher register numbers so need to be pushed first in order to preserve
1042
14.3k
    // monotonicity.
1043
14.3k
    if (MI != MBB.begin())
1044
14.3k
      --MI;
1045
14.3k
  }
1046
32.6k
}
1047
1048
void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
1049
                                   MachineBasicBlock::iterator MI,
1050
                                   std::vector<CalleeSavedInfo> &CSI,
1051
                                   unsigned LdmOpc, unsigned LdrOpc,
1052
                                   bool isVarArg, bool NoGap,
1053
                                   bool(*Func)(unsigned, bool),
1054
35.5k
                                   unsigned NumAlignedDPRCS2Regs) const {
1055
35.5k
  MachineFunction &MF = *MBB.getParent();
1056
35.5k
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1057
35.5k
  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1058
35.5k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1059
35.5k
  DebugLoc DL;
1060
35.5k
  bool isTailCall = false;
1061
35.5k
  bool isInterrupt = false;
1062
35.5k
  bool isTrap = false;
1063
35.5k
  if (MBB.end() != MI) {
1064
35.3k
    DL = MI->getDebugLoc();
1065
35.3k
    unsigned RetOpcode = MI->getOpcode();
1066
35.3k
    isTailCall = (RetOpcode == ARM::TCRETURNdi || 
RetOpcode == ARM::TCRETURNri29.7k
);
1067
35.3k
    isInterrupt =
1068
35.3k
        RetOpcode == ARM::SUBS_PC_LR || 
RetOpcode == ARM::t2SUBS_PC_LR35.2k
;
1069
35.3k
    isTrap =
1070
35.3k
        RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
1071
35.3k
        RetOpcode == ARM::tTRAP;
1072
35.3k
  }
1073
35.5k
1074
35.5k
  SmallVector<unsigned, 4> Regs;
1075
35.5k
  unsigned i = CSI.size();
1076
71.1k
  while (i != 0) {
1077
35.6k
    unsigned LastReg = 0;
1078
35.6k
    bool DeleteRet = false;
1079
201k
    for (; i != 0; 
--i165k
) {
1080
165k
      CalleeSavedInfo &Info = CSI[i-1];
1081
165k
      unsigned Reg = Info.getReg();
1082
165k
      if (!(Func)(Reg, STI.splitFramePushPop(MF))) 
continue110k
;
1083
55.3k
1084
55.3k
      // The aligned reloads from area DPRCS2 are not inserted here.
1085
55.3k
      if (Reg >= ARM::D8 && 
Reg < ARM::D8 + NumAlignedDPRCS2Regs43.3k
)
1086
282
        continue;
1087
55.0k
1088
55.0k
      if (Reg == ARM::LR && 
!isTailCall11.8k
&&
!isVarArg9.89k
&&
!isInterrupt9.79k
&&
1089
55.0k
          
!isTrap9.78k
&&
STI.hasV5TOps()9.78k
) {
1090
8.95k
        if (MBB.succ_empty()) {
1091
8.84k
          Reg = ARM::PC;
1092
8.84k
          // Fold the return instruction into the LDM.
1093
8.84k
          DeleteRet = true;
1094
8.84k
          LdmOpc = AFI->isThumbFunction() ? 
ARM::t2LDMIA_RET7.29k
:
ARM::LDMIA_RET1.55k
;
1095
8.84k
          // We 'restore' LR into PC so it is not live out of the return block:
1096
8.84k
          // Clear Restored bit.
1097
8.84k
          Info.setRestored(false);
1098
8.84k
        } else
1099
102
          LdmOpc = AFI->isThumbFunction() ? 
ARM::t2LDMIA_UPD96
:
ARM::LDMIA_UPD6
;
1100
8.95k
      }
1101
55.0k
1102
55.0k
      // If NoGap is true, pop consecutive registers and then leave the rest
1103
55.0k
      // for other instructions. e.g.
1104
55.0k
      // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1105
55.0k
      if (NoGap && 
LastReg1.63k
&&
LastReg != Reg-11.18k
)
1106
24
        break;
1107
55.0k
1108
55.0k
      LastReg = Reg;
1109
55.0k
      Regs.push_back(Reg);
1110
55.0k
    }
1111
35.6k
1112
35.6k
    if (Regs.empty())
1113
19.2k
      continue;
1114
16.3k
1115
38.9k
    
llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) 16.3k
{
1116
38.9k
      return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1117
38.9k
    });
1118
16.3k
1119
16.3k
    if (Regs.size() > 1 || 
LdrOpc == 01.77k
) {
1120
14.6k
      MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1121
14.6k
                                    .addReg(ARM::SP)
1122
14.6k
                                    .add(predOps(ARMCC::AL));
1123
68.0k
      for (unsigned i = 0, e = Regs.size(); i < e; 
++i53.3k
)
1124
53.3k
        MIB.addReg(Regs[i], getDefRegState(true));
1125
14.6k
      if (DeleteRet) {
1126
8.70k
        if (MI != MBB.end()) {
1127
8.70k
          MIB.copyImplicitOps(*MI);
1128
8.70k
          MI->eraseFromParent();
1129
8.70k
        }
1130
8.70k
      }
1131
14.6k
      MI = MIB;
1132
14.6k
    } else 
if (1.65k
Regs.size() == 11.65k
) {
1133
1.65k
      // If we adjusted the reg to PC from LR above, switch it back here. We
1134
1.65k
      // only do that for LDM.
1135
1.65k
      if (Regs[0] == ARM::PC)
1136
147
        Regs[0] = ARM::LR;
1137
1.65k
      MachineInstrBuilder MIB =
1138
1.65k
        BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1139
1.65k
          .addReg(ARM::SP, RegState::Define)
1140
1.65k
          .addReg(ARM::SP);
1141
1.65k
      // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1142
1.65k
      // that refactoring is complete (eventually).
1143
1.65k
      if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1144
215
        MIB.addReg(0);
1145
215
        MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
1146
215
      } else
1147
1.43k
        MIB.addImm(4);
1148
1.65k
      MIB.add(predOps(ARMCC::AL));
1149
1.65k
    }
1150
16.3k
    Regs.clear();
1151
16.3k
1152
16.3k
    // Put any subsequent vpop instructions after this one: they will refer to
1153
16.3k
    // higher register numbers so need to be popped afterwards.
1154
16.3k
    if (MI != MBB.end())
1155
16.3k
      ++MI;
1156
16.3k
  }
1157
35.5k
}
1158
1159
/// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1160
/// starting from d8.  Also insert stack realignment code and leave the stack
1161
/// pointer pointing to the d8 spill slot.
1162
static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1163
                                    MachineBasicBlock::iterator MI,
1164
                                    unsigned NumAlignedDPRCS2Regs,
1165
                                    const std::vector<CalleeSavedInfo> &CSI,
1166
50
                                    const TargetRegisterInfo *TRI) {
1167
50
  MachineFunction &MF = *MBB.getParent();
1168
50
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1169
50
  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : 
DebugLoc()0
;
1170
50
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1171
50
  MachineFrameInfo &MFI = MF.getFrameInfo();
1172
50
1173
50
  // Mark the D-register spill slots as properly aligned.  Since MFI computes
1174
50
  // stack slot layout backwards, this can actually mean that the d-reg stack
1175
50
  // slot offsets can be wrong. The offset for d8 will always be correct.
1176
689
  for (unsigned i = 0, e = CSI.size(); i != e; 
++i639
) {
1177
639
    unsigned DNum = CSI[i].getReg() - ARM::D8;
1178
639
    if (DNum > NumAlignedDPRCS2Regs - 1)
1179
293
      continue;
1180
346
    int FI = CSI[i].getFrameIdx();
1181
346
    // The even-numbered registers will be 16-byte aligned, the odd-numbered
1182
346
    // registers will be 8-byte aligned.
1183
346
    MFI.setObjectAlignment(FI, DNum % 2 ? 
8172
:
16174
);
1184
346
1185
346
    // The stack slot for D8 needs to be maximally aligned because this is
1186
346
    // actually the point where we align the stack pointer.  MachineFrameInfo
1187
346
    // computes all offsets relative to the incoming stack pointer which is a
1188
346
    // bit weird when realigning the stack.  Any extra padding for this
1189
346
    // over-alignment is not realized because the code inserted below adjusts
1190
346
    // the stack pointer by numregs * 8 before aligning the stack pointer.
1191
346
    if (DNum == 0)
1192
50
      MFI.setObjectAlignment(FI, MFI.getMaxAlignment());
1193
346
  }
1194
50
1195
50
  // Move the stack pointer to the d8 spill slot, and align it at the same
1196
50
  // time. Leave the stack slot address in the scratch register r4.
1197
50
  //
1198
50
  //   sub r4, sp, #numregs * 8
1199
50
  //   bic r4, r4, #align - 1
1200
50
  //   mov sp, r4
1201
50
  //
1202
50
  bool isThumb = AFI->isThumbFunction();
1203
50
  assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1204
50
  AFI->setShouldRestoreSPFromFP(true);
1205
50
1206
50
  // sub r4, sp, #numregs * 8
1207
50
  // The immediate is <= 64, so it doesn't need any special encoding.
1208
50
  unsigned Opc = isThumb ? 
ARM::t2SUBri34
:
ARM::SUBri16
;
1209
50
  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1210
50
      .addReg(ARM::SP)
1211
50
      .addImm(8 * NumAlignedDPRCS2Regs)
1212
50
      .add(predOps(ARMCC::AL))
1213
50
      .add(condCodeOp());
1214
50
1215
50
  unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
1216
50
  // We must set parameter MustBeSingleInstruction to true, since
1217
50
  // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1218
50
  // stack alignment.  Luckily, this can always be done since all ARM
1219
50
  // architecture versions that support Neon also support the BFC
1220
50
  // instruction.
1221
50
  emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1222
50
1223
50
  // mov sp, r4
1224
50
  // The stack pointer must be adjusted before spilling anything, otherwise
1225
50
  // the stack slots could be clobbered by an interrupt handler.
1226
50
  // Leave r4 live, it is used below.
1227
50
  Opc = isThumb ? 
ARM::tMOVr34
:
ARM::MOVr16
;
1228
50
  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1229
50
                                .addReg(ARM::R4)
1230
50
                                .add(predOps(ARMCC::AL));
1231
50
  if (!isThumb)
1232
16
    MIB.add(condCodeOp());
1233
50
1234
50
  // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1235
50
  // r4 holds the stack slot address.
1236
50
  unsigned NextReg = ARM::D8;
1237
50
1238
50
  // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1239
50
  // The writeback is only needed when emitting two vst1.64 instructions.
1240
50
  if (NumAlignedDPRCS2Regs >= 6) {
1241
41
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1242
41
                                               &ARM::QQPRRegClass);
1243
41
    MBB.addLiveIn(SupReg);
1244
41
    BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1245
41
        .addReg(ARM::R4, RegState::Kill)
1246
41
        .addImm(16)
1247
41
        .addReg(NextReg)
1248
41
        .addReg(SupReg, RegState::ImplicitKill)
1249
41
        .add(predOps(ARMCC::AL));
1250
41
    NextReg += 4;
1251
41
    NumAlignedDPRCS2Regs -= 4;
1252
41
  }
1253
50
1254
50
  // We won't modify r4 beyond this point.  It currently points to the next
1255
50
  // register to be spilled.
1256
50
  unsigned R4BaseReg = NextReg;
1257
50
1258
50
  // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1259
50
  if (NumAlignedDPRCS2Regs >= 4) {
1260
40
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1261
40
                                               &ARM::QQPRRegClass);
1262
40
    MBB.addLiveIn(SupReg);
1263
40
    BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1264
40
        .addReg(ARM::R4)
1265
40
        .addImm(16)
1266
40
        .addReg(NextReg)
1267
40
        .addReg(SupReg, RegState::ImplicitKill)
1268
40
        .add(predOps(ARMCC::AL));
1269
40
    NextReg += 4;
1270
40
    NumAlignedDPRCS2Regs -= 4;
1271
40
  }
1272
50
1273
50
  // 16-byte aligned vst1.64 with 2 d-regs.
1274
50
  if (NumAlignedDPRCS2Regs >= 2) {
1275
10
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1276
10
                                               &ARM::QPRRegClass);
1277
10
    MBB.addLiveIn(SupReg);
1278
10
    BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1279
10
        .addReg(ARM::R4)
1280
10
        .addImm(16)
1281
10
        .addReg(SupReg)
1282
10
        .add(predOps(ARMCC::AL));
1283
10
    NextReg += 2;
1284
10
    NumAlignedDPRCS2Regs -= 2;
1285
10
  }
1286
50
1287
50
  // Finally, use a vanilla vstr.64 for the odd last register.
1288
50
  if (NumAlignedDPRCS2Regs) {
1289
2
    MBB.addLiveIn(NextReg);
1290
2
    // vstr.64 uses addrmode5 which has an offset scale of 4.
1291
2
    BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1292
2
        .addReg(NextReg)
1293
2
        .addReg(ARM::R4)
1294
2
        .addImm((NextReg - R4BaseReg) * 2)
1295
2
        .add(predOps(ARMCC::AL));
1296
2
  }
1297
50
1298
50
  // The last spill instruction inserted should kill the scratch register r4.
1299
50
  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1300
50
}
1301
1302
/// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1303
/// iterator to the following instruction.
1304
static MachineBasicBlock::iterator
1305
skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1306
50
                        unsigned NumAlignedDPRCS2Regs) {
1307
50
  //   sub r4, sp, #numregs * 8
1308
50
  //   bic r4, r4, #align - 1
1309
50
  //   mov sp, r4
1310
50
  ++MI; ++MI; ++MI;
1311
50
  assert(MI->mayStore() && "Expecting spill instruction");
1312
50
1313
50
  // These switches all fall through.
1314
50
  switch(NumAlignedDPRCS2Regs) {
1315
50
  case 7:
1316
1
    ++MI;
1317
1
    assert(MI->mayStore() && "Expecting spill instruction");
1318
1
    LLVM_FALLTHROUGH;
1319
42
  default:
1320
42
    ++MI;
1321
42
    assert(MI->mayStore() && "Expecting spill instruction");
1322
42
    LLVM_FALLTHROUGH;
1323
50
  case 1:
1324
50
  case 2:
1325
50
  case 4:
1326
50
    assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1327
50
    ++MI;
1328
50
  }
1329
50
  return MI;
1330
50
}
1331
1332
/// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1333
/// starting from d8.  These instructions are assumed to execute while the
1334
/// stack is still aligned, unlike the code inserted by emitPopInst.
1335
static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1336
                                      MachineBasicBlock::iterator MI,
1337
                                      unsigned NumAlignedDPRCS2Regs,
1338
                                      const std::vector<CalleeSavedInfo> &CSI,
1339
42
                                      const TargetRegisterInfo *TRI) {
1340
42
  MachineFunction &MF = *MBB.getParent();
1341
42
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1342
42
  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : 
DebugLoc()0
;
1343
42
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1344
42
1345
42
  // Find the frame index assigned to d8.
1346
42
  int D8SpillFI = 0;
1347
511
  for (unsigned i = 0, e = CSI.size(); i != e; 
++i469
)
1348
511
    if (CSI[i].getReg() == ARM::D8) {
1349
42
      D8SpillFI = CSI[i].getFrameIdx();
1350
42
      break;
1351
42
    }
1352
42
1353
42
  // Materialize the address of the d8 spill slot into the scratch register r4.
1354
42
  // This can be fairly complicated if the stack frame is large, so just use
1355
42
  // the normal frame index elimination mechanism to do it.  This code runs as
1356
42
  // the initial part of the epilog where the stack and base pointers haven't
1357
42
  // been changed yet.
1358
42
  bool isThumb = AFI->isThumbFunction();
1359
42
  assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1360
42
1361
42
  unsigned Opc = isThumb ? 
ARM::t2ADDri31
:
ARM::ADDri11
;
1362
42
  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1363
42
      .addFrameIndex(D8SpillFI)
1364
42
      .addImm(0)
1365
42
      .add(predOps(ARMCC::AL))
1366
42
      .add(condCodeOp());
1367
42
1368
42
  // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1369
42
  unsigned NextReg = ARM::D8;
1370
42
1371
42
  // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1372
42
  if (NumAlignedDPRCS2Regs >= 6) {
1373
33
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1374
33
                                               &ARM::QQPRRegClass);
1375
33
    BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1376
33
        .addReg(ARM::R4, RegState::Define)
1377
33
        .addReg(ARM::R4, RegState::Kill)
1378
33
        .addImm(16)
1379
33
        .addReg(SupReg, RegState::ImplicitDefine)
1380
33
        .add(predOps(ARMCC::AL));
1381
33
    NextReg += 4;
1382
33
    NumAlignedDPRCS2Regs -= 4;
1383
33
  }
1384
42
1385
42
  // We won't modify r4 beyond this point.  It currently points to the next
1386
42
  // register to be spilled.
1387
42
  unsigned R4BaseReg = NextReg;
1388
42
1389
42
  // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1390
42
  if (NumAlignedDPRCS2Regs >= 4) {
1391
32
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1392
32
                                               &ARM::QQPRRegClass);
1393
32
    BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1394
32
        .addReg(ARM::R4)
1395
32
        .addImm(16)
1396
32
        .addReg(SupReg, RegState::ImplicitDefine)
1397
32
        .add(predOps(ARMCC::AL));
1398
32
    NextReg += 4;
1399
32
    NumAlignedDPRCS2Regs -= 4;
1400
32
  }
1401
42
1402
42
  // 16-byte aligned vld1.64 with 2 d-regs.
1403
42
  if (NumAlignedDPRCS2Regs >= 2) {
1404
10
    unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1405
10
                                               &ARM::QPRRegClass);
1406
10
    BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1407
10
        .addReg(ARM::R4)
1408
10
        .addImm(16)
1409
10
        .add(predOps(ARMCC::AL));
1410
10
    NextReg += 2;
1411
10
    NumAlignedDPRCS2Regs -= 2;
1412
10
  }
1413
42
1414
42
  // Finally, use a vanilla vldr.64 for the remaining odd register.
1415
42
  if (NumAlignedDPRCS2Regs)
1416
2
    BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1417
2
        .addReg(ARM::R4)
1418
2
        .addImm(2 * (NextReg - R4BaseReg))
1419
2
        .add(predOps(ARMCC::AL));
1420
42
1421
42
  // Last store kills r4.
1422
42
  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1423
42
}
1424
1425
bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1426
                                        MachineBasicBlock::iterator MI,
1427
                                        const std::vector<CalleeSavedInfo> &CSI,
1428
10.8k
                                        const TargetRegisterInfo *TRI) const {
1429
10.8k
  if (CSI.empty())
1430
0
    return false;
1431
10.8k
1432
10.8k
  MachineFunction &MF = *MBB.getParent();
1433
10.8k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1434
10.8k
1435
10.8k
  unsigned PushOpc = AFI->isThumbFunction() ? 
ARM::t2STMDB_UPD8.32k
:
ARM::STMDB_UPD2.54k
;
1436
10.8k
  unsigned PushOneOpc = AFI->isThumbFunction() ?
1437
8.32k
    ARM::t2STR_PRE : 
ARM::STR_PRE_IMM2.54k
;
1438
10.8k
  unsigned FltOpc = ARM::VSTMDDB_UPD;
1439
10.8k
  unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1440
10.8k
  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1441
10.8k
               MachineInstr::FrameSetup);
1442
10.8k
  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1443
10.8k
               MachineInstr::FrameSetup);
1444
10.8k
  emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1445
10.8k
               NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1446
10.8k
1447
10.8k
  // The code above does not insert spill code for the aligned DPRCS2 registers.
1448
10.8k
  // The stack realignment code will be inserted between the push instructions
1449
10.8k
  // and these spills.
1450
10.8k
  if (NumAlignedDPRCS2Regs)
1451
50
    emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1452
10.8k
1453
10.8k
  return true;
1454
10.8k
}
1455
1456
bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1457
                                        MachineBasicBlock::iterator MI,
1458
                                        std::vector<CalleeSavedInfo> &CSI,
1459
11.8k
                                        const TargetRegisterInfo *TRI) const {
1460
11.8k
  if (CSI.empty())
1461
0
    return false;
1462
11.8k
1463
11.8k
  MachineFunction &MF = *MBB.getParent();
1464
11.8k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1465
11.8k
  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
1466
11.8k
  unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1467
11.8k
1468
11.8k
  // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
1469
11.8k
  // registers. Do that here instead.
1470
11.8k
  if (NumAlignedDPRCS2Regs)
1471
42
    emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1472
11.8k
1473
11.8k
  unsigned PopOpc = AFI->isThumbFunction() ? 
ARM::t2LDMIA_UPD9.35k
:
ARM::LDMIA_UPD2.50k
;
1474
11.8k
  unsigned LdrOpc = AFI->isThumbFunction() ? 
ARM::t2LDR_POST9.35k
:
ARM::LDR_POST_IMM2.50k
;
1475
11.8k
  unsigned FltOpc = ARM::VLDMDIA_UPD;
1476
11.8k
  emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1477
11.8k
              NumAlignedDPRCS2Regs);
1478
11.8k
  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1479
11.8k
              &isARMArea2Register, 0);
1480
11.8k
  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1481
11.8k
              &isARMArea1Register, 0);
1482
11.8k
1483
11.8k
  return true;
1484
11.8k
}
1485
1486
// FIXME: Make generic?
1487
static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF,
1488
887
                                            const ARMBaseInstrInfo &TII) {
1489
887
  unsigned FnSize = 0;
1490
2.09k
  for (auto &MBB : MF) {
1491
2.09k
    for (auto &MI : MBB)
1492
9.49k
      FnSize += TII.getInstSizeInBytes(MI);
1493
2.09k
  }
1494
887
  if (MF.getJumpTableInfo())
1495
12
    for (auto &Table: MF.getJumpTableInfo()->getJumpTables())
1496
12
      FnSize += Table.MBBs.size() * 4;
1497
887
  FnSize += MF.getConstantPool()->getConstants().size() * 4;
1498
887
  return FnSize;
1499
887
}
1500
1501
/// estimateRSStackSizeLimit - Look at each instruction that references stack
1502
/// frames and return the stack size limit beyond which some of these
1503
/// instructions will require a scratch register during their expansion later.
1504
// FIXME: Move to TII?
1505
static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
1506
32.7k
                                         const TargetFrameLowering *TFI) {
1507
32.7k
  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1508
32.7k
  unsigned Limit = (1 << 12) - 1;
1509
180k
  for (auto &MBB : MF) {
1510
1.20M
    for (auto &MI : MBB) {
1511
6.56M
      for (unsigned i = 0, e = MI.getNumOperands(); i != e; 
++i5.36M
) {
1512
5.41M
        if (!MI.getOperand(i).isFI())
1513
5.36M
          continue;
1514
57.2k
1515
57.2k
        // When using ADDri to get the address of a stack object, 255 is the
1516
57.2k
        // largest offset guaranteed to fit in the immediate offset.
1517
57.2k
        if (MI.getOpcode() == ARM::ADDri) {
1518
1.30k
          Limit = std::min(Limit, (1U << 8) - 1);
1519
1.30k
          break;
1520
1.30k
        }
1521
55.9k
1522
55.9k
        // Otherwise check the addressing mode.
1523
55.9k
        switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
1524
55.9k
        case ARMII::AddrMode3:
1525
100
        case ARMII::AddrModeT2_i8:
1526
100
          Limit = std::min(Limit, (1U << 8) - 1);
1527
100
          break;
1528
1.63k
        case ARMII::AddrMode5:
1529
1.63k
        case ARMII::AddrModeT2_i8s4:
1530
1.63k
        case ARMII::AddrModeT2_ldrex:
1531
1.63k
          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
1532
1.63k
          break;
1533
38.7k
        case ARMII::AddrModeT2_i12:
1534
38.7k
          // i12 supports only positive offset so these will be converted to
1535
38.7k
          // i8 opcodes. See llvm::rewriteT2FrameIndex.
1536
38.7k
          if (TFI->hasFP(MF) && 
AFI->hasStackFrame()35.3k
)
1537
0
            Limit = std::min(Limit, (1U << 8) - 1);
1538
38.7k
          break;
1539
1.63k
        case ARMII::AddrMode4:
1540
9
        case ARMII::AddrMode6:
1541
9
          // Addressing modes 4 & 6 (load/store) instructions can't encode an
1542
9
          // immediate offset for stack references.
1543
9
          return 0;
1544
15.4k
        default:
1545
15.4k
          break;
1546
55.8k
        }
1547
55.8k
        break; // At most one FI per instruction
1548
55.8k
      }
1549
1.20M
    }
1550
180k
  }
1551
32.7k
1552
32.7k
  
return Limit32.7k
;
1553
32.7k
}
1554
1555
// In functions that realign the stack, it can be an advantage to spill the
1556
// callee-saved vector registers after realigning the stack. The vst1 and vld1
1557
// instructions take alignment hints that can improve performance.
1558
static void
1559
34.2k
checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
1560
34.2k
  MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
1561
34.2k
  if (!SpillAlignedNEONRegs)
1562
3
    return;
1563
34.2k
1564
34.2k
  // Naked functions don't spill callee-saved registers.
1565
34.2k
  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1566
1
    return;
1567
34.2k
1568
34.2k
  // We are planning to use NEON instructions vst1 / vld1.
1569
34.2k
  if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1570
8.90k
    return;
1571
25.3k
1572
25.3k
  // Don't bother if the default stack alignment is sufficiently high.
1573
25.3k
  if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
1574
12.7k
    return;
1575
12.6k
1576
12.6k
  // Aligned spills require stack realignment.
1577
12.6k
  if (!static_cast<const ARMBaseRegisterInfo *>(
1578
12.6k
           MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
1579
1.03k
    return;
1580
11.5k
1581
11.5k
  // We always spill contiguous d-registers starting from d8. Count how many
1582
11.5k
  // needs spilling.  The register allocator will almost always use the
1583
11.5k
  // callee-saved registers in order, but it can happen that there are holes in
1584
11.5k
  // the range.  Registers above the hole will be spilled to the standard DPRCS
1585
11.5k
  // area.
1586
11.5k
  unsigned NumSpills = 0;
1587
11.9k
  for (; NumSpills < 8; 
++NumSpills352
)
1588
11.8k
    if (!SavedRegs.test(ARM::D8 + NumSpills))
1589
11.5k
      break;
1590
11.5k
1591
11.5k
  // Don't do this for just one d-register. It's not worth it.
1592
11.5k
  if (NumSpills < 2)
1593
11.5k
    return;
1594
50
1595
50
  // Spill the first NumSpills D-registers after realigning the stack.
1596
50
  MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
1597
50
1598
50
  // A scratch register is required for the vst1 / vld1 instructions.
1599
50
  SavedRegs.set(ARM::R4);
1600
50
}
1601
1602
void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
1603
                                            BitVector &SavedRegs,
1604
34.2k
                                            RegScavenger *RS) const {
1605
34.2k
  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1606
34.2k
  // This tells PEI to spill the FP as if it is any other callee-save register
1607
34.2k
  // to take advantage the eliminateFrameIndex machinery. This also ensures it
1608
34.2k
  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1609
34.2k
  // to combine multiple loads / stores.
1610
34.2k
  bool CanEliminateFrame = true;
1611
34.2k
  bool CS1Spilled = false;
1612
34.2k
  bool LRSpilled = false;
1613
34.2k
  unsigned NumGPRSpills = 0;
1614
34.2k
  unsigned NumFPRSpills = 0;
1615
34.2k
  SmallVector<unsigned, 4> UnspilledCS1GPRs;
1616
34.2k
  SmallVector<unsigned, 4> UnspilledCS2GPRs;
1617
34.2k
  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1618
34.2k
      MF.getSubtarget().getRegisterInfo());
1619
34.2k
  const ARMBaseInstrInfo &TII =
1620
34.2k
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1621
34.2k
  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1622
34.2k
  MachineFrameInfo &MFI = MF.getFrameInfo();
1623
34.2k
  MachineRegisterInfo &MRI = MF.getRegInfo();
1624
34.2k
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1625
34.2k
  (void)TRI;  // Silence unused warning in non-assert builds.
1626
34.2k
  unsigned FramePtr = RegInfo->getFrameRegister(MF);
1627
34.2k
1628
34.2k
  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1629
34.2k
  // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1630
34.2k
  // since it's not always possible to restore sp from fp in a single
1631
34.2k
  // instruction.
1632
34.2k
  // FIXME: It will be better just to find spare register here.
1633
34.2k
  if (AFI->isThumb2Function() &&
1634
34.2k
      
(23.6k
MFI.hasVarSizedObjects()23.6k
||
RegInfo->needsStackRealignment(MF)23.6k
))
1635
237
    SavedRegs.set(ARM::R4);
1636
34.2k
1637
34.2k
  // If a stack probe will be emitted, spill R4 and LR, since they are
1638
34.2k
  // clobbered by the stack probe call.
1639
34.2k
  // This estimate should be a safe, conservative estimate. The actual
1640
34.2k
  // stack probe is enabled based on the size of the local objects;
1641
34.2k
  // this estimate also includes the varargs store size.
1642
34.2k
  if (STI.isTargetWindows() &&
1643
34.2k
      
WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))174
) {
1644
3
    SavedRegs.set(ARM::R4);
1645
3
    SavedRegs.set(ARM::LR);
1646
3
  }
1647
34.2k
1648
34.2k
  if (AFI->isThumb1OnlyFunction()) {
1649
1.55k
    // Spill LR if Thumb1 function uses variable length argument lists.
1650
1.55k
    if (AFI->getArgRegsSaveSize() > 0)
1651
20
      SavedRegs.set(ARM::LR);
1652
1.55k
1653
1.55k
    // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function
1654
1.55k
    // requires stack alignment.  We don't know for sure what the stack size
1655
1.55k
    // will be, but for this, an estimate is good enough. If there anything
1656
1.55k
    // changes it, it'll be a spill, which implies we've used all the registers
1657
1.55k
    // and so R4 is already used, so not marking it here will be OK.
1658
1.55k
    // FIXME: It will be better just to find spare register here.
1659
1.55k
    if (MFI.hasVarSizedObjects() || 
RegInfo->needsStackRealignment(MF)1.54k
||
1660
1.55k
        
MFI.estimateStackSize(MF) > 5081.50k
)
1661
161
      SavedRegs.set(ARM::R4);
1662
1.55k
  }
1663
34.2k
1664
34.2k
  // See if we can spill vector registers to aligned stack.
1665
34.2k
  checkNumAlignedDPRCS2Regs(MF, SavedRegs);
1666
34.2k
1667
34.2k
  // Spill the BasePtr if it's used.
1668
34.2k
  if (RegInfo->hasBasePointer(MF))
1669
32
    SavedRegs.set(RegInfo->getBaseRegister());
1670
34.2k
1671
34.2k
  // Don't spill FP if the frame can be eliminated. This is determined
1672
34.2k
  // by scanning the callee-save registers to see if any is modified.
1673
34.2k
  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1674
598k
  for (unsigned i = 0; CSRegs[i]; 
++i564k
) {
1675
564k
    unsigned Reg = CSRegs[i];
1676
564k
    bool Spilled = false;
1677
564k
    if (SavedRegs.test(Reg)) {
1678
90.9k
      Spilled = true;
1679
90.9k
      CanEliminateFrame = false;
1680
90.9k
    }
1681
564k
1682
564k
    if (!ARM::GPRRegClass.contains(Reg)) {
1683
274k
      if (Spilled) {
1684
2.15k
        if (ARM::SPRRegClass.contains(Reg))
1685
0
          NumFPRSpills++;
1686
2.15k
        else if (ARM::DPRRegClass.contains(Reg))
1687
2.15k
          NumFPRSpills += 2;
1688
0
        else if (ARM::QPRRegClass.contains(Reg))
1689
0
          NumFPRSpills += 4;
1690
2.15k
      }
1691
274k
      continue;
1692
274k
    }
1693
289k
1694
289k
    if (Spilled) {
1695
88.7k
      NumGPRSpills++;
1696
88.7k
1697
88.7k
      if (!STI.splitFramePushPop(MF)) {
1698
8.91k
        if (Reg == ARM::LR)
1699
3.73k
          LRSpilled = true;
1700
8.91k
        CS1Spilled = true;
1701
8.91k
        continue;
1702
8.91k
      }
1703
79.8k
1704
79.8k
      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1705
79.8k
      switch (Reg) {
1706
79.8k
      case ARM::LR:
1707
14.9k
        LRSpilled = true;
1708
14.9k
        LLVM_FALLTHROUGH;
1709
57.5k
      case ARM::R0: case ARM::R1:
1710
57.5k
      case ARM::R2: case ARM::R3:
1711
57.5k
      case ARM::R4: case ARM::R5:
1712
57.5k
      case ARM::R6: case ARM::R7:
1713
57.5k
        CS1Spilled = true;
1714
57.5k
        break;
1715
57.5k
      default:
1716
22.3k
        break;
1717
200k
      }
1718
200k
    } else {
1719
200k
      if (!STI.splitFramePushPop(MF)) {
1720
125k
        UnspilledCS1GPRs.push_back(Reg);
1721
125k
        continue;
1722
125k
      }
1723
75.2k
1724
75.2k
      switch (Reg) {
1725
75.2k
      
case ARM::R0: 38.4k
case ARM::R1:
1726
38.4k
      case ARM::R2: case ARM::R3:
1727
38.4k
      case ARM::R4: case ARM::R5:
1728
38.4k
      case ARM::R6: case ARM::R7:
1729
38.4k
      case ARM::LR:
1730
38.4k
        UnspilledCS1GPRs.push_back(Reg);
1731
38.4k
        break;
1732
38.4k
      default:
1733
36.8k
        UnspilledCS2GPRs.push_back(Reg);
1734
36.8k
        break;
1735
75.2k
      }
1736
75.2k
    }
1737
289k
  }
1738
34.2k
1739
34.2k
  bool ForceLRSpill = false;
1740
34.2k
  if (!LRSpilled && 
AFI->isThumb1OnlyFunction()15.6k
) {
1741
887
    unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII);
1742
887
    // Force LR to be spilled if the Thumb function size is > 2048. This enables
1743
887
    // use of BL to implement far jump. If it turns out that it's not needed
1744
887
    // then the branch fix up path will undo it.
1745
887
    if (FnSize >= (1 << 11)) {
1746
4
      CanEliminateFrame = false;
1747
4
      ForceLRSpill = true;
1748
4
    }
1749
887
  }
1750
34.2k
1751
34.2k
  // If any of the stack slot references may be out of range of an immediate
1752
34.2k
  // offset, make sure a register (or a spill slot) is available for the
1753
34.2k
  // register scavenger. Note that if we're indexing off the frame pointer, the
1754
34.2k
  // effective stack size is 4 bytes larger since the FP points to the stack
1755
34.2k
  // slot of the previous FP. Also, if we have variable sized objects in the
1756
34.2k
  // function, stack slot references will often be negative, and some of
1757
34.2k
  // our instructions are positive-offset only, so conservatively consider
1758
34.2k
  // that case to want a spill slot (or register) as well. Similarly, if
1759
34.2k
  // the function adjusts the stack pointer during execution and the
1760
34.2k
  // adjustments aren't already part of our stack size estimate, our offset
1761
34.2k
  // calculations may be off, so be conservative.
1762
34.2k
  // FIXME: We could add logic to be more precise about negative offsets
1763
34.2k
  //        and which instructions will need a scratch register for them. Is it
1764
34.2k
  //        worth the effort and added fragility?
1765
34.2k
  unsigned EstimatedStackSize =
1766
34.2k
      MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
1767
34.2k
1768
34.2k
  // Determine biggest (positive) SP offset in MachineFrameInfo.
1769
34.2k
  int MaxFixedOffset = 0;
1770
38.7k
  for (int I = MFI.getObjectIndexBegin(); I < 0; 
++I4.42k
) {
1771
4.42k
    int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I);
1772
4.42k
    MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);
1773
4.42k
  }
1774
34.2k
1775
34.2k
  bool HasFP = hasFP(MF);
1776
34.2k
  if (HasFP) {
1777
18.5k
    if (AFI->hasStackFrame())
1778
5.73k
      EstimatedStackSize += 4;
1779
18.5k
  } else {
1780
15.7k
    // If FP is not used, SP will be used to access arguments, so count the
1781
15.7k
    // size of arguments into the estimation.
1782
15.7k
    EstimatedStackSize += MaxFixedOffset;
1783
15.7k
  }
1784
34.2k
  EstimatedStackSize += 16; // For possible paddings.
1785
34.2k
1786
34.2k
  unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit;
1787
34.2k
  if (AFI->isThumb1OnlyFunction()) {
1788
1.55k
    // For Thumb1, don't bother to iterate over the function. The only
1789
1.55k
    // instruction that requires an emergency spill slot is a store to a
1790
1.55k
    // frame index.
1791
1.55k
    //
1792
1.55k
    // tSTRspi, which is used for sp-relative accesses, has an 8-bit unsigned
1793
1.55k
    // immediate. tSTRi, which is used for bp- and fp-relative accesses, has
1794
1.55k
    // a 5-bit unsigned immediate.
1795
1.55k
    //
1796
1.55k
    // We could try to check if the function actually contains a tSTRspi
1797
1.55k
    // that might need the spill slot, but it's not really important.
1798
1.55k
    // Functions with VLAs or extremely large call frames are rare, and
1799
1.55k
    // if a function is allocating more than 1KB of stack, an extra 4-byte
1800
1.55k
    // slot probably isn't relevant.
1801
1.55k
    if (RegInfo->hasBasePointer(MF))
1802
25
      EstimatedRSStackSizeLimit = (1U << 5) * 4;
1803
1.53k
    else
1804
1.53k
      EstimatedRSStackSizeLimit = (1U << 8) * 4;
1805
1.55k
    EstimatedRSFixedSizeLimit = (1U << 5) * 4;
1806
32.7k
  } else {
1807
32.7k
    EstimatedRSStackSizeLimit = estimateRSStackSizeLimit(MF, this);
1808
32.7k
    EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit;
1809
32.7k
  }
1810
34.2k
  // Final estimate of whether sp or bp-relative accesses might require
1811
34.2k
  // scavenging.
1812
34.2k
  bool HasLargeStack = EstimatedStackSize > EstimatedRSStackSizeLimit;
1813
34.2k
1814
34.2k
  // If the stack pointer moves and we don't have a base pointer, the
1815
34.2k
  // estimate logic doesn't work. The actual offsets might be larger when
1816
34.2k
  // we're constructing a call frame, or we might need to use negative
1817
34.2k
  // offsets from fp.
1818
34.2k
  bool HasMovingSP = MFI.hasVarSizedObjects() ||
1819
34.2k
    
(34.2k
MFI.adjustsStack()34.2k
&&
!canSimplifyCallFramePseudos(MF)16.0k
);
1820
34.2k
  bool HasBPOrFixedSP = RegInfo->hasBasePointer(MF) || 
!HasMovingSP34.2k
;
1821
34.2k
1822
34.2k
  // If we have a frame pointer, we assume arguments will be accessed
1823
34.2k
  // relative to the frame pointer. Check whether fp-relative accesses to
1824
34.2k
  // arguments require scavenging.
1825
34.2k
  //
1826
34.2k
  // We could do slightly better on Thumb1; in some cases, an sp-relative
1827
34.2k
  // offset would be legal even though an fp-relative offset is not.
1828
34.2k
  int MaxFPOffset = getMaxFPOffset(MF.getFunction(), *AFI);
1829
34.2k
  bool HasLargeArgumentList =
1830
34.2k
      HasFP && 
(MaxFixedOffset - MaxFPOffset) > (int)EstimatedRSFixedSizeLimit18.5k
;
1831
34.2k
1832
34.2k
  bool BigFrameOffsets = HasLargeStack || 
!HasBPOrFixedSP34.0k
||
1833
34.2k
                         
HasLargeArgumentList34.0k
;
1834
34.2k
  LLVM_DEBUG(dbgs() << "EstimatedLimit: " << EstimatedRSStackSizeLimit
1835
34.2k
                    << "; EstimatedStack" << EstimatedStackSize
1836
34.2k
                    << "; EstimatedFPStack" << MaxFixedOffset - MaxFPOffset
1837
34.2k
                    << "; BigFrameOffsets: " << BigFrameOffsets
1838
34.2k
                    << "\n");
1839
34.2k
  if (BigFrameOffsets ||
1840
34.2k
      
!CanEliminateFrame34.0k
||
RegInfo->cannotEliminateFrame(MF)15.1k
) {
1841
19.2k
    AFI->setHasStackFrame(true);
1842
19.2k
1843
19.2k
    if (HasFP) {
1844
15.0k
      SavedRegs.set(FramePtr);
1845
15.0k
      // If the frame pointer is required by the ABI, also spill LR so that we
1846
15.0k
      // emit a complete frame record.
1847
15.0k
      if (MF.getTarget().Options.DisableFramePointerElim(MF) && 
!LRSpilled14.7k
) {
1848
171
        SavedRegs.set(ARM::LR);
1849
171
        LRSpilled = true;
1850
171
        NumGPRSpills++;
1851
171
        auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
1852
171
        if (LRPos != UnspilledCS1GPRs.end())
1853
171
          UnspilledCS1GPRs.erase(LRPos);
1854
171
      }
1855
15.0k
      auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);
1856
15.0k
      if (FPPos != UnspilledCS1GPRs.end())
1857
7.46k
        UnspilledCS1GPRs.erase(FPPos);
1858
15.0k
      NumGPRSpills++;
1859
15.0k
      if (FramePtr == ARM::R7)
1860
14.6k
        CS1Spilled = true;
1861
15.0k
    }
1862
19.2k
1863
19.2k
    // This is true when we inserted a spill for a callee-save GPR which is
1864
19.2k
    // not otherwise used by the function. This guaranteees it is possible
1865
19.2k
    // to scavenge a register to hold the address of a stack slot. On Thumb1,
1866
19.2k
    // the register must be a valid operand to tSTRi, i.e. r4-r7. For other
1867
19.2k
    // subtargets, this is any GPR, i.e. r4-r11 or lr.
1868
19.2k
    //
1869
19.2k
    // If we don't insert a spill, we instead allocate an emergency spill
1870
19.2k
    // slot, which can be used by scavenging to spill an arbitrary register.
1871
19.2k
    //
1872
19.2k
    // We currently don't try to figure out whether any specific instruction
1873
19.2k
    // requires scavening an additional register.
1874
19.2k
    bool ExtraCSSpill = false;
1875
19.2k
1876
19.2k
    if (AFI->isThumb1OnlyFunction()) {
1877
863
      // For Thumb1-only targets, we need some low registers when we save and
1878
863
      // restore the high registers (which aren't allocatable, but could be
1879
863
      // used by inline assembly) because the push/pop instructions can not
1880
863
      // access high registers. If necessary, we might need to push more low
1881
863
      // registers to ensure that there is at least one free that can be used
1882
863
      // for the saving & restoring, and preferably we should ensure that as
1883
863
      // many as are needed are available so that fewer push/pop instructions
1884
863
      // are required.
1885
863
1886
863
      // Low registers which are not currently pushed, but could be (r4-r7).
1887
863
      SmallVector<unsigned, 4> AvailableRegs;
1888
863
1889
863
      // Unused argument registers (r0-r3) can be clobbered in the prologue for
1890
863
      // free.
1891
863
      int EntryRegDeficit = 0;
1892
3.45k
      for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
1893
3.45k
        if (!MF.getRegInfo().isLiveIn(Reg)) {
1894
2.22k
          --EntryRegDeficit;
1895
2.22k
          LLVM_DEBUG(dbgs()
1896
2.22k
                     << printReg(Reg, TRI)
1897
2.22k
                     << " is unused argument register, EntryRegDeficit = "
1898
2.22k
                     << EntryRegDeficit << "\n");
1899
2.22k
        }
1900
3.45k
      }
1901
863
1902
863
      // Unused return registers can be clobbered in the epilogue for free.
1903
863
      int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
1904
863
      LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount()
1905
863
                        << " return regs used, ExitRegDeficit = "
1906
863
                        << ExitRegDeficit << "\n");
1907
863
1908
863
      int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
1909
863
      LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
1910
863
1911
863
      // r4-r6 can be used in the prologue if they are pushed by the first push
1912
863
      // instruction.
1913
2.58k
      for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
1914
2.58k
        if (SavedRegs.test(Reg)) {
1915
1.04k
          --RegDeficit;
1916
1.04k
          LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1917
1.04k
                            << " is saved low register, RegDeficit = "
1918
1.04k
                            << RegDeficit << "\n");
1919
1.54k
        } else {
1920
1.54k
          AvailableRegs.push_back(Reg);
1921
1.54k
          LLVM_DEBUG(
1922
1.54k
              dbgs()
1923
1.54k
              << printReg(Reg, TRI)
1924
1.54k
              << " is non-saved low register, adding to AvailableRegs\n");
1925
1.54k
        }
1926
2.58k
      }
1927
863
1928
863
      // r7 can be used if it is not being used as the frame pointer.
1929
863
      if (!HasFP) {
1930
691
        if (SavedRegs.test(ARM::R7)) {
1931
110
          --RegDeficit;
1932
110
          LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
1933
110
                            << RegDeficit << "\n");
1934
581
        } else {
1935
581
          AvailableRegs.push_back(ARM::R7);
1936
581
          LLVM_DEBUG(
1937
581
              dbgs()
1938
581
              << "%r7 is non-saved low register, adding to AvailableRegs\n");
1939
581
        }
1940
691
      }
1941
863
1942
863
      // Each of r8-r11 needs to be copied to a low register, then pushed.
1943
3.45k
      for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
1944
3.45k
        if (SavedRegs.test(Reg)) {
1945
55
          ++RegDeficit;
1946
55
          LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1947
55
                            << " is saved high register, RegDeficit = "
1948
55
                            << RegDeficit << "\n");
1949
55
        }
1950
3.45k
      }
1951
863
1952
863
      // LR can only be used by PUSH, not POP, and can't be used at all if the
1953
863
      // llvm.returnaddress intrinsic is used. This is only worth doing if we
1954
863
      // are more limited at function entry than exit.
1955
863
      if ((EntryRegDeficit > ExitRegDeficit) &&
1956
863
          
!(365
MF.getRegInfo().isLiveIn(ARM::LR)365
&&
1957
365
            
MF.getFrameInfo().isReturnAddressTaken()0
)) {
1958
365
        if (SavedRegs.test(ARM::LR)) {
1959
275
          --RegDeficit;
1960
275
          LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = "
1961
275
                            << RegDeficit << "\n");
1962
275
        } else {
1963
90
          AvailableRegs.push_back(ARM::LR);
1964
90
          LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");
1965
90
        }
1966
365
      }
1967
863
1968
863
      // If there are more high registers that need pushing than low registers
1969
863
      // available, push some more low registers so that we can use fewer push
1970
863
      // instructions. This might not reduce RegDeficit all the way to zero,
1971
863
      // because we can only guarantee that r4-r6 are available, but r8-r11 may
1972
863
      // need saving.
1973
863
      LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
1974
871
      for (; RegDeficit > 0 && 
!AvailableRegs.empty()9
;
--RegDeficit8
) {
1975
8
        unsigned Reg = AvailableRegs.pop_back_val();
1976
8
        LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
1977
8
                          << " to make up reg deficit\n");
1978
8
        SavedRegs.set(Reg);
1979
8
        NumGPRSpills++;
1980
8
        CS1Spilled = true;
1981
8
        assert(!MRI.isReserved(Reg) && "Should not be reserved");
1982
8
        if (Reg != ARM::LR && 
!MRI.isPhysRegUsed(Reg)7
)
1983
7
          ExtraCSSpill = true;
1984
8
        UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
1985
8
        if (Reg == ARM::LR)
1986
1
          LRSpilled = true;
1987
8
      }
1988
863
      LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit
1989
863
                        << "\n");
1990
863
    }
1991
19.2k
1992
19.2k
    // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to
1993
19.2k
    // restore LR in that case.
1994
19.2k
    bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && 
MFI.hasTailCall()863
;
1995
19.2k
1996
19.2k
    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1997
19.2k
    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1998
19.2k
    if (!LRSpilled && 
CS1Spilled381
&&
!ExpensiveLRRestore332
) {
1999
331
      SavedRegs.set(ARM::LR);
2000
331
      NumGPRSpills++;
2001
331
      SmallVectorImpl<unsigned>::iterator LRPos;
2002
331
      LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
2003
331
      if (LRPos != UnspilledCS1GPRs.end())
2004
331
        UnspilledCS1GPRs.erase(LRPos);
2005
331
2006
331
      ForceLRSpill = false;
2007
331
      if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) &&
2008
331
          
!AFI->isThumb1OnlyFunction()328
)
2009
167
        ExtraCSSpill = true;
2010
331
    }
2011
19.2k
2012
19.2k
    // If stack and double are 8-byte aligned and we are spilling an odd number
2013
19.2k
    // of GPRs, spill one extra callee save GPR so we won't have to pad between
2014
19.2k
    // the integer and double callee save areas.
2015
19.2k
    LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");
2016
19.2k
    unsigned TargetAlign = getStackAlignment();
2017
19.2k
    if (TargetAlign >= 8 && 
(NumGPRSpills & 1)9.12k
) {
2018
5.62k
      if (CS1Spilled && 
!UnspilledCS1GPRs.empty()5.60k
) {
2019
6.58k
        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; 
++i3.59k
) {
2020
6.49k
          unsigned Reg = UnspilledCS1GPRs[i];
2021
6.49k
          // Don't spill high register if the function is thumb.  In the case of
2022
6.49k
          // Windows on ARM, accept R11 (frame pointer)
2023
6.49k
          if (!AFI->isThumbFunction() ||
2024
6.49k
              
(5.22k
STI.isTargetWindows()5.22k
&&
Reg == ARM::R11100
) ||
2025
6.49k
              
isARMLowRegister(Reg)5.15k
||
2026
6.49k
              
(3.59k
Reg == ARM::LR3.59k
&&
!ExpensiveLRRestore1
)) {
2027
2.90k
            SavedRegs.set(Reg);
2028
2.90k
            LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2029
2.90k
                              << " to make up alignment\n");
2030
2.90k
            if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg) &&
2031
2.90k
                !(Reg == ARM::LR && 
AFI->isThumb1OnlyFunction()0
))
2032
2.90k
              ExtraCSSpill = true;
2033
2.90k
            break;
2034
2.90k
          }
2035
6.49k
        }
2036
2.99k
      } else 
if (2.62k
!UnspilledCS2GPRs.empty()2.62k
&&
!AFI->isThumb1OnlyFunction()714
) {
2037
598
        unsigned Reg = UnspilledCS2GPRs.front();
2038
598
        SavedRegs.set(Reg);
2039
598
        LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2040
598
                          << " to make up alignment\n");
2041
598
        if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
2042
598
          ExtraCSSpill = true;
2043
598
      }
2044
5.62k
    }
2045
19.2k
2046
19.2k
    // Estimate if we might need to scavenge a register at some point in order
2047
19.2k
    // to materialize a stack offset. If so, either spill one additional
2048
19.2k
    // callee-saved register or reserve a special spill slot to facilitate
2049
19.2k
    // register scavenging. Thumb1 needs a spill slot for stack pointer
2050
19.2k
    // adjustments also, even when the frame itself is small.
2051
19.2k
    if (BigFrameOffsets && 
!ExtraCSSpill278
) {
2052
184
      // If any non-reserved CS register isn't spilled, just spill one or two
2053
184
      // extra. That should take care of it!
2054
184
      unsigned NumExtras = TargetAlign / 4;
2055
184
      SmallVector<unsigned, 2> Extras;
2056
369
      while (NumExtras && 
!UnspilledCS1GPRs.empty()252
) {
2057
185
        unsigned Reg = UnspilledCS1GPRs.back();
2058
185
        UnspilledCS1GPRs.pop_back();
2059
185
        if (!MRI.isReserved(Reg) &&
2060
185
            (!AFI->isThumb1OnlyFunction() || 
isARMLowRegister(Reg)67
)) {
2061
185
          Extras.push_back(Reg);
2062
185
          NumExtras--;
2063
185
        }
2064
185
      }
2065
184
      // For non-Thumb1 functions, also check for hi-reg CS registers
2066
184
      if (!AFI->isThumb1OnlyFunction()) {
2067
133
        while (NumExtras && 
!UnspilledCS2GPRs.empty()57
) {
2068
4
          unsigned Reg = UnspilledCS2GPRs.back();
2069
4
          UnspilledCS2GPRs.pop_back();
2070
4
          if (!MRI.isReserved(Reg)) {
2071
4
            Extras.push_back(Reg);
2072
4
            NumExtras--;
2073
4
          }
2074
4
        }
2075
129
      }
2076
184
      if (NumExtras == 0) {
2077
180
        for (unsigned Reg : Extras) {
2078
180
          SavedRegs.set(Reg);
2079
180
          if (!MRI.isPhysRegUsed(Reg))
2080
180
            ExtraCSSpill = true;
2081
180
        }
2082
119
      }
2083
184
      if (!ExtraCSSpill) {
2084
65
        // Reserve a slot closest to SP or frame pointer.
2085
65
        assert(RS && "Register scavenging not provided");
2086
65
        LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n");
2087
65
        const TargetRegisterClass &RC = ARM::GPRRegClass;
2088
65
        unsigned Size = TRI->getSpillSize(RC);
2089
65
        unsigned Align = TRI->getSpillAlignment(RC);
2090
65
        RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
2091
65
      }
2092
184
    }
2093
19.2k
  }
2094
34.2k
2095
34.2k
  if (ForceLRSpill) {
2096
4
    SavedRegs.set(ARM::LR);
2097
4
    AFI->setLRIsSpilledForFarJump(true);
2098
4
  }
2099
34.2k
  AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
2100
34.2k
2101
34.2k
  // If we have the "returned" parameter attribute which guarantees that we
2102
34.2k
  // return the value which was passed in r0 unmodified (e.g. C++ 'structors),
2103
34.2k
  // record that fact for IPRA.
2104
34.2k
  if (AFI->getPreservesR0())
2105
963
    SavedRegs.set(ARM::R0);
2106
34.2k
}
2107
2108
MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
2109
    MachineFunction &MF, MachineBasicBlock &MBB,
2110
107k
    MachineBasicBlock::iterator I) const {
2111
107k
  const ARMBaseInstrInfo &TII =
2112
107k
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2113
107k
  if (!hasReservedCallFrame(MF)) {
2114
1.55k
    // If we have alloca, convert as follows:
2115
1.55k
    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
2116
1.55k
    // ADJCALLSTACKUP   -> add, sp, sp, amount
2117
1.55k
    MachineInstr &Old = *I;
2118
1.55k
    DebugLoc dl = Old.getDebugLoc();
2119
1.55k
    unsigned Amount = TII.getFrameSize(Old);
2120
1.55k
    if (Amount != 0) {
2121
182
      // We need to keep the stack aligned properly.  To do this, we round the
2122
182
      // amount of space needed for the outgoing arguments up to the next
2123
182
      // alignment boundary.
2124
182
      Amount = alignSPAdjust(Amount);
2125
182
2126
182
      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2127
182
      assert(!AFI->isThumb1OnlyFunction() &&
2128
182
             "This eliminateCallFramePseudoInstr does not support Thumb1!");
2129
182
      bool isARM = !AFI->isThumbFunction();
2130
182
2131
182
      // Replace the pseudo instruction with a new instruction...
2132
182
      unsigned Opc = Old.getOpcode();
2133
182
      int PIdx = Old.findFirstPredOperandIdx();
2134
182
      ARMCC::CondCodes Pred =
2135
182
          (PIdx == -1) ? 
ARMCC::AL0
2136
182
                       : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
2137
182
      unsigned PredReg = TII.getFramePred(Old);
2138
182
      if (Opc == ARM::ADJCALLSTACKDOWN || 
Opc == ARM::tADJCALLSTACKDOWN91
) {
2139
91
        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
2140
91
                     Pred, PredReg);
2141
91
      } else {
2142
91
        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
2143
91
        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
2144
91
                     Pred, PredReg);
2145
91
      }
2146
182
    }
2147
1.55k
  }
2148
107k
  return MBB.erase(I);
2149
107k
}
2150
2151
/// Get the minimum constant for ARM that is greater than or equal to the
2152
/// argument. In ARM, constants can have any value that can be produced by
2153
/// rotating an 8-bit value to the right by an even number of bits within a
2154
/// 32-bit word.
2155
112
static uint32_t alignToARMConstant(uint32_t Value) {
2156
112
  unsigned Shifted = 0;
2157
112
2158
112
  if (Value == 0)
2159
60
      return 0;
2160
52
2161
648
  
while (52
!(Value & 0xC0000000)) {
2162
596
      Value = Value << 2;
2163
596
      Shifted += 2;
2164
596
  }
2165
52
2166
52
  bool Carry = (Value & 0x00FFFFFF);
2167
52
  Value = ((Value & 0xFF000000) >> 24) + Carry;
2168
52
2169
52
  if (Value & 0x0000100)
2170
0
      Value = Value & 0x000001FC;
2171
52
2172
52
  if (Shifted > 24)
2173
36
      Value = Value >> (Shifted - 24);
2174
16
  else
2175
16
      Value = Value << (24 - Shifted);
2176
52
2177
52
  return Value;
2178
52
}
2179
2180
// The stack limit in the TCB is set to this many bytes above the actual
2181
// stack limit.
2182
static const uint64_t kSplitStackAvailable = 256;
2183
2184
// Adjust the function prologue to enable split stacks. This currently only
2185
// supports android and linux.
2186
//
2187
// The ABI of the segmented stack prologue is a little arbitrarily chosen, but
2188
// must be well defined in order to allow for consistent implementations of the
2189
// __morestack helper function. The ABI is also not a normal ABI in that it
2190
// doesn't follow the normal calling conventions because this allows the
2191
// prologue of each function to be optimized further.
2192
//
2193
// Currently, the ABI looks like (when calling __morestack)
2194
//
2195
//  * r4 holds the minimum stack size requested for this function call
2196
//  * r5 holds the stack size of the arguments to the function
2197
//  * the beginning of the function is 3 instructions after the call to
2198
//    __morestack
2199
//
2200
// Implementations of __morestack should use r4 to allocate a new stack, r5 to
2201
// place the arguments on to the new stack, and the 3-instruction knowledge to
2202
// jump directly to the body of the function when working on the new stack.
2203
//
2204
// An old (and possibly no longer compatible) implementation of __morestack for
2205
// ARM can be found at [1].
2206
//
2207
// [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
2208
void ARMFrameLowering::adjustForSegmentedStacks(
2209
64
    MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2210
64
  unsigned Opcode;
2211
64
  unsigned CFIIndex;
2212
64
  const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
2213
64
  bool Thumb = ST->isThumb();
2214
64
2215
64
  // Sadly, this currently doesn't support varargs, platforms other than
2216
64
  // android/linux. Note that thumb1/thumb2 are support for android/linux.
2217
64
  if (MF.getFunction().isVarArg())
2218
0
    report_fatal_error("Segmented stacks do not support vararg functions.");
2219
64
  if (!ST->isTargetAndroid() && 
!ST->isTargetLinux()32
)
2220
0
    report_fatal_error("Segmented stacks not supported on this platform.");
2221
64
2222
64
  MachineFrameInfo &MFI = MF.getFrameInfo();
2223
64
  MachineModuleInfo &MMI = MF.getMMI();
2224
64
  MCContext &Context = MMI.getContext();
2225
64
  const MCRegisterInfo *MRI = Context.getRegisterInfo();
2226
64
  const ARMBaseInstrInfo &TII =
2227
64
      *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2228
64
  ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
2229
64
  DebugLoc DL;
2230
64
2231
64
  uint64_t StackSize = MFI.getStackSize();
2232
64
2233
64
  // Do not generate a prologue for leaf functions with a stack of size zero.
2234
64
  // For non-leaf functions we have to allow for the possibility that the
2235
64
  // callis to a non-split function, as in PR37807. This function could also
2236
64
  // take the address of a non-split function. When the linker tries to adjust
2237
64
  // its non-existent prologue, it would fail with an error. Mark the object
2238
64
  // file so that such failures are not errors. See this Go language bug-report
2239
64
  // https://go-review.googlesource.com/c/go/+/148819/
2240
64
  if (StackSize == 0 && 
!MFI.hasTailCall()12
) {
2241
8
    MF.getMMI().setHasNosplitStack(true);
2242
8
    return;
2243
8
  }
2244
56
2245
56
  // Use R4 and R5 as scratch registers.
2246
56
  // We save R4 and R5 before use and restore them before leaving the function.
2247
56
  unsigned ScratchReg0 = ARM::R4;
2248
56
  unsigned ScratchReg1 = ARM::R5;
2249
56
  uint64_t AlignedStackSize;
2250
56
2251
56
  MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
2252
56
  MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
2253
56
  MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
2254
56
  MachineBasicBlock *GetMBB = MF.CreateMachineBasicBlock();
2255
56
  MachineBasicBlock *McrMBB = MF.CreateMachineBasicBlock();
2256
56
2257
56
  // Grab everything that reaches PrologueMBB to update there liveness as well.
2258
56
  SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
2259
56
  SmallVector<MachineBasicBlock *, 2> WalkList;
2260
56
  WalkList.push_back(&PrologueMBB);
2261
56
2262
56
  do {
2263
56
    MachineBasicBlock *CurMBB = WalkList.pop_back_val();
2264
56
    for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
2265
0
      if (BeforePrologueRegion.insert(PredBB).second)
2266
0
        WalkList.push_back(PredBB);
2267
0
    }
2268
56
  } while (!WalkList.empty());
2269
56
2270
56
  // The order in that list is important.
2271
56
  // The blocks will all be inserted before PrologueMBB using that order.
2272
56
  // Therefore the block that should appear first in the CFG should appear
2273
56
  // first in the list.
2274
56
  MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
2275
56
                                      PostStackMBB};
2276
56
2277
56
  for (MachineBasicBlock *B : AddedBlocks)
2278
280
    BeforePrologueRegion.insert(B);
2279
56
2280
168
  for (const auto &LI : PrologueMBB.liveins()) {
2281
168
    for (MachineBasicBlock *PredBB : BeforePrologueRegion)
2282
840
      PredBB->addLiveIn(LI);
2283
168
  }
2284
56
2285
56
  // Remove the newly added blocks from the list, since we know
2286
56
  // we do not have to do the following updates for them.
2287
280
  for (MachineBasicBlock *B : AddedBlocks) {
2288
280
    BeforePrologueRegion.erase(B);
2289
280
    MF.insert(PrologueMBB.getIterator(), B);
2290
280
  }
2291
56
2292
56
  for (MachineBasicBlock *MBB : BeforePrologueRegion) {
2293
0
    // Make sure the LiveIns are still sorted and unique.
2294
0
    MBB->sortUniqueLiveIns();
2295
0
    // Replace the edges to PrologueMBB by edges to the sequences
2296
0
    // we are about to add.
2297
0
    MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2298
0
  }
2299
56
2300
56
  // The required stack size that is aligned to ARM constant criterion.
2301
56
  AlignedStackSize = alignToARMConstant(StackSize);
2302
56
2303
56
  // When the frame size is less than 256 we just compare the stack
2304
56
  // boundary directly to the value of the stack pointer, per gcc.
2305
56
  bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
2306
56
2307
56
  // We will use two of the callee save registers as scratch registers so we
2308
56
  // need to save those registers onto the stack.
2309
56
  // We will use SR0 to hold stack limit and SR1 to hold the stack size
2310
56
  // requested and arguments for __morestack().
2311
56
  // SR0: Scratch Register #0
2312
56
  // SR1: Scratch Register #1
2313
56
  // push {SR0, SR1}
2314
56
  if (Thumb) {
2315
26
    BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
2316
26
        .add(predOps(ARMCC::AL))
2317
26
        .addReg(ScratchReg0)
2318
26
        .addReg(ScratchReg1);
2319
30
  } else {
2320
30
    BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2321
30
        .addReg(ARM::SP, RegState::Define)
2322
30
        .addReg(ARM::SP)
2323
30
        .add(predOps(ARMCC::AL))
2324
30
        .addReg(ScratchReg0)
2325
30
        .addReg(ScratchReg1);
2326
30
  }
2327
56
2328
56
  // Emit the relevant DWARF information about the change in stack pointer as
2329
56
  // well as where to find both r4 and r5 (the callee-save registers)
2330
56
  CFIIndex =
2331
56
      MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
2332
56
  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2333
56
      .addCFIIndex(CFIIndex);
2334
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2335
56
      nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
2336
56
  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2337
56
      .addCFIIndex(CFIIndex);
2338
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2339
56
      nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
2340
56
  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2341
56
      .addCFIIndex(CFIIndex);
2342
56
2343
56
  // mov SR1, sp
2344
56
  if (Thumb) {
2345
26
    BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
2346
26
        .addReg(ARM::SP)
2347
26
        .add(predOps(ARMCC::AL));
2348
30
  } else if (CompareStackPointer) {
2349
22
    BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
2350
22
        .addReg(ARM::SP)
2351
22
        .add(predOps(ARMCC::AL))
2352
22
        .add(condCodeOp());
2353
22
  }
2354
56
2355
56
  // sub SR1, sp, #StackSize
2356
56
  if (!CompareStackPointer && 
Thumb16
) {
2357
8
    BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
2358
8
        .add(condCodeOp())
2359
8
        .addReg(ScratchReg1)
2360
8
        .addImm(AlignedStackSize)
2361
8
        .add(predOps(ARMCC::AL));
2362
48
  } else if (!CompareStackPointer) {
2363
8
    BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
2364
8
        .addReg(ARM::SP)
2365
8
        .addImm(AlignedStackSize)
2366
8
        .add(predOps(ARMCC::AL))
2367
8
        .add(condCodeOp());
2368
8
  }
2369
56
2370
56
  if (Thumb && 
ST->isThumb1Only()26
) {
2371
24
    unsigned PCLabelId = ARMFI->createPICLabelUId();
2372
24
    ARMConstantPoolValue *NewCPV = ARMConstantPoolSymbol::Create(
2373
24
        MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);
2374
24
    MachineConstantPool *MCP = MF.getConstantPool();
2375
24
    unsigned CPI = MCP->getConstantPoolIndex(NewCPV, 4);
2376
24
2377
24
    // ldr SR0, [pc, offset(STACK_LIMIT)]
2378
24
    BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
2379
24
        .addConstantPoolIndex(CPI)
2380
24
        .add(predOps(ARMCC::AL));
2381
24
2382
24
    // ldr SR0, [SR0]
2383
24
    BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
2384
24
        .addReg(ScratchReg0)
2385
24
        .addImm(0)
2386
24
        .add(predOps(ARMCC::AL));
2387
32
  } else {
2388
32
    // Get TLS base address from the coprocessor
2389
32
    // mrc p15, #0, SR0, c13, c0, #3
2390
32
    BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
2391
32
        .addImm(15)
2392
32
        .addImm(0)
2393
32
        .addImm(13)
2394
32
        .addImm(0)
2395
32
        .addImm(3)
2396
32
        .add(predOps(ARMCC::AL));
2397
32
2398
32
    // Use the last tls slot on android and a private field of the TCP on linux.
2399
32
    assert(ST->isTargetAndroid() || ST->isTargetLinux());
2400
32
    unsigned TlsOffset = ST->isTargetAndroid() ? 
6316
:
116
;
2401
32
2402
32
    // Get the stack limit from the right offset
2403
32
    // ldr SR0, [sr0, #4 * TlsOffset]
2404
32
    BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2405
32
        .addReg(ScratchReg0)
2406
32
        .addImm(4 * TlsOffset)
2407
32
        .add(predOps(ARMCC::AL));
2408
32
  }
2409
56
2410
56
  // Compare stack limit with stack size requested.
2411
56
  // cmp SR0, SR1
2412
56
  Opcode = Thumb ? 
ARM::tCMPr26
:
ARM::CMPrr30
;
2413
56
  BuildMI(GetMBB, DL, TII.get(Opcode))
2414
56
      .addReg(ScratchReg0)
2415
56
      .addReg(ScratchReg1)
2416
56
      .add(predOps(ARMCC::AL));
2417
56
2418
56
  // This jump is taken if StackLimit < SP - stack required.
2419
56
  Opcode = Thumb ? 
ARM::tBcc26
:
ARM::Bcc30
;
2420
56
  BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2421
56
       .addImm(ARMCC::LO)
2422
56
       .addReg(ARM::CPSR);
2423
56
2424
56
2425
56
  // Calling __morestack(StackSize, Size of stack arguments).
2426
56
  // __morestack knows that the stack size requested is in SR0(r4)
2427
56
  // and amount size of stack arguments is in SR1(r5).
2428
56
2429
56
  // Pass first argument for the __morestack by Scratch Register #0.
2430
56
  //   The amount size of stack required
2431
56
  if (Thumb) {
2432
26
    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
2433
26
        .add(condCodeOp())
2434
26
        .addImm(AlignedStackSize)
2435
26
        .add(predOps(ARMCC::AL));
2436
30
  } else {
2437
30
    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2438
30
        .addImm(AlignedStackSize)
2439
30
        .add(predOps(ARMCC::AL))
2440
30
        .add(condCodeOp());
2441
30
  }
2442
56
  // Pass second argument for the __morestack by Scratch Register #1.
2443
56
  //   The amount size of stack consumed to save function arguments.
2444
56
  if (Thumb) {
2445
26
    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
2446
26
        .add(condCodeOp())
2447
26
        .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2448
26
        .add(predOps(ARMCC::AL));
2449
30
  } else {
2450
30
    BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2451
30
        .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
2452
30
        .add(predOps(ARMCC::AL))
2453
30
        .add(condCodeOp());
2454
30
  }
2455
56
2456
56
  // push {lr} - Save return address of this function.
2457
56
  if (Thumb) {
2458
26
    BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
2459
26
        .add(predOps(ARMCC::AL))
2460
26
        .addReg(ARM::LR);
2461
30
  } else {
2462
30
    BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2463
30
        .addReg(ARM::SP, RegState::Define)
2464
30
        .addReg(ARM::SP)
2465
30
        .add(predOps(ARMCC::AL))
2466
30
        .addReg(ARM::LR);
2467
30
  }
2468
56
2469
56
  // Emit the DWARF info about the change in stack as well as where to find the
2470
56
  // previous link register
2471
56
  CFIIndex =
2472
56
      MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2473
56
  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2474
56
      .addCFIIndex(CFIIndex);
2475
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
2476
56
        nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2477
56
  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2478
56
      .addCFIIndex(CFIIndex);
2479
56
2480
56
  // Call __morestack().
2481
56
  if (Thumb) {
2482
26
    BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
2483
26
        .add(predOps(ARMCC::AL))
2484
26
        .addExternalSymbol("__morestack");
2485
30
  } else {
2486
30
    BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2487
30
        .addExternalSymbol("__morestack");
2488
30
  }
2489
56
2490
56
  // pop {lr} - Restore return address of this original function.
2491
56
  if (Thumb) {
2492
26
    if (ST->isThumb1Only()) {
2493
24
      BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2494
24
          .add(predOps(ARMCC::AL))
2495
24
          .addReg(ScratchReg0);
2496
24
      BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2497
24
          .addReg(ScratchReg0)
2498
24
          .add(predOps(ARMCC::AL));
2499
24
    } else {
2500
2
      BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2501
2
          .addReg(ARM::LR, RegState::Define)
2502
2
          .addReg(ARM::SP, RegState::Define)
2503
2
          .addReg(ARM::SP)
2504
2
          .addImm(4)
2505
2
          .add(predOps(ARMCC::AL));
2506
2
    }
2507
30
  } else {
2508
30
    BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2509
30
        .addReg(ARM::SP, RegState::Define)
2510
30
        .addReg(ARM::SP)
2511
30
        .add(predOps(ARMCC::AL))
2512
30
        .addReg(ARM::LR);
2513
30
  }
2514
56
2515
56
  // Restore SR0 and SR1 in case of __morestack() was called.
2516
56
  // __morestack() will skip PostStackMBB block so we need to restore
2517
56
  // scratch registers from here.
2518
56
  // pop {SR0, SR1}
2519
56
  if (Thumb) {
2520
26
    BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2521
26
        .add(predOps(ARMCC::AL))
2522
26
        .addReg(ScratchReg0)
2523
26
        .addReg(ScratchReg1);
2524
30
  } else {
2525
30
    BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2526
30
        .addReg(ARM::SP, RegState::Define)
2527
30
        .addReg(ARM::SP)
2528
30
        .add(predOps(ARMCC::AL))
2529
30
        .addReg(ScratchReg0)
2530
30
        .addReg(ScratchReg1);
2531
30
  }
2532
56
2533
56
  // Update the CFA offset now that we've popped
2534
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2535
56
  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2536
56
      .addCFIIndex(CFIIndex);
2537
56
2538
56
  // Return from this function.
2539
56
  BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
2540
56
2541
56
  // Restore SR0 and SR1 in case of __morestack() was not called.
2542
56
  // pop {SR0, SR1}
2543
56
  if (Thumb) {
2544
26
    BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
2545
26
        .add(predOps(ARMCC::AL))
2546
26
        .addReg(ScratchReg0)
2547
26
        .addReg(ScratchReg1);
2548
30
  } else {
2549
30
    BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2550
30
        .addReg(ARM::SP, RegState::Define)
2551
30
        .addReg(ARM::SP)
2552
30
        .add(predOps(ARMCC::AL))
2553
30
        .addReg(ScratchReg0)
2554
30
        .addReg(ScratchReg1);
2555
30
  }
2556
56
2557
56
  // Update the CFA offset now that we've popped
2558
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2559
56
  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2560
56
      .addCFIIndex(CFIIndex);
2561
56
2562
56
  // Tell debuggers that r4 and r5 are now the same as they were in the
2563
56
  // previous function, that they're the "Same Value".
2564
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2565
56
      nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
2566
56
  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2567
56
      .addCFIIndex(CFIIndex);
2568
56
  CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
2569
56
      nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
2570
56
  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2571
56
      .addCFIIndex(CFIIndex);
2572
56
2573
56
  // Organizing MBB lists
2574
56
  PostStackMBB->addSuccessor(&PrologueMBB);
2575
56
2576
56
  AllocMBB->addSuccessor(PostStackMBB);
2577
56
2578
56
  GetMBB->addSuccessor(PostStackMBB);
2579
56
  GetMBB->addSuccessor(AllocMBB);
2580
56
2581
56
  McrMBB->addSuccessor(GetMBB);
2582
56
2583
56
  PrevStackMBB->addSuccessor(McrMBB);
2584
56
2585
#ifdef EXPENSIVE_CHECKS
2586
  MF.verify();
2587
#endif
2588
}