Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "ARMHazardRecognizer.h"
10
#include "ARMBaseInstrInfo.h"
11
#include "ARMBaseRegisterInfo.h"
12
#include "ARMSubtarget.h"
13
#include "llvm/CodeGen/MachineInstr.h"
14
#include "llvm/CodeGen/ScheduleDAG.h"
15
#include "llvm/CodeGen/TargetRegisterInfo.h"
16
using namespace llvm;
17
18
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
19
1.04k
                         const TargetRegisterInfo &TRI) {
20
1.04k
  // FIXME: Detect integer instructions properly.
21
1.04k
  const MCInstrDesc &MCID = MI->getDesc();
22
1.04k
  unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
23
1.04k
  if (MI->mayStore())
24
3
    return false;
25
1.04k
  unsigned Opcode = MCID.getOpcode();
26
1.04k
  if (Opcode == ARM::VMOVRS || 
Opcode == ARM::VMOVRRD873
)
27
180
    return false;
28
862
  if ((Domain & ARMII::DomainVFP) || 
(Domain & ARMII::DomainNEON)16
)
29
862
    return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
30
0
  return false;
31
0
}
32
33
ScheduleHazardRecognizer::HazardType
34
402k
ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
35
402k
  assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
36
402k
37
402k
  MachineInstr *MI = SU->getInstr();
38
402k
39
402k
  if (!MI->isDebugInstr()) {
40
402k
    // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
41
402k
    // a VMLA / VMLS will cause 4 cycle stall.
42
402k
    const MCInstrDesc &MCID = MI->getDesc();
43
402k
    if (LastMI && 
(MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral311k
) {
44
67.4k
      MachineInstr *DefMI = LastMI;
45
67.4k
      const MCInstrDesc &LastMCID = LastMI->getDesc();
46
67.4k
      const MachineFunction *MF = MI->getParent()->getParent();
47
67.4k
      const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
48
67.4k
                                        MF->getSubtarget().getInstrInfo());
49
67.4k
50
67.4k
      // Skip over one non-VFP / NEON instruction.
51
67.4k
      if (!LastMI->isBarrier() &&
52
67.4k
          !(TII.getSubtarget().hasMuxedUnits() && 
LastMI->mayLoadOrStore()1.14k
) &&
53
67.4k
          
(LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral67.1k
) {
54
7.62k
        MachineBasicBlock::iterator I = LastMI;
55
7.62k
        if (I != LastMI->getParent()->begin()) {
56
7.01k
          I = std::prev(I);
57
7.01k
          DefMI = &*I;
58
7.01k
        }
59
7.62k
      }
60
67.4k
61
67.4k
      if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
62
67.4k
          
(1.23k
TII.canCauseFpMLxStall(MI->getOpcode())1.23k
||
63
1.23k
           
hasRAWHazard(DefMI, MI, TII.getRegisterInfo())1.04k
)) {
64
442
        // Try to schedule another instruction for the next 4 cycles.
65
442
        if (FpMLxStalls == 0)
66
107
          FpMLxStalls = 4;
67
442
        return Hazard;
68
442
      }
69
402k
    }
70
402k
  }
71
402k
72
402k
  return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
73
402k
}
74
75
286k
void ARMHazardRecognizer::Reset() {
76
286k
  LastMI = nullptr;
77
286k
  FpMLxStalls = 0;
78
286k
  ScoreboardHazardRecognizer::Reset();
79
286k
}
80
81
344k
void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
82
344k
  MachineInstr *MI = SU->getInstr();
83
344k
  if (!MI->isDebugInstr()) {
84
344k
    LastMI = MI;
85
344k
    FpMLxStalls = 0;
86
344k
  }
87
344k
88
344k
  ScoreboardHazardRecognizer::EmitInstruction(SU);
89
344k
}
90
91
266k
void ARMHazardRecognizer::AdvanceCycle() {
92
266k
  if (FpMLxStalls && 
--FpMLxStalls == 0407
)
93
101
    // Stalled for 4 cycles but still can't schedule any other instructions.
94
101
    LastMI = nullptr;
95
266k
  ScoreboardHazardRecognizer::AdvanceCycle();
96
266k
}
97
98
0
void ARMHazardRecognizer::RecedeCycle() {
99
0
  llvm_unreachable("reverse ARM hazard checking unsupported");
100
0
}