Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMISelLowering.h
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//===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/MachineValueType.h"
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#include <utility>
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namespace llvm {
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class ARMSubtarget;
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class DataLayout;
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class FastISel;
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class FunctionLoweringInfo;
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class GlobalValue;
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class InstrItineraryData;
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class Instruction;
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class MachineBasicBlock;
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class MachineInstr;
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class SelectionDAG;
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class TargetLibraryInfo;
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class TargetMachine;
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class TargetRegisterInfo;
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class VectorType;
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  namespace ARMISD {
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    // ARM Specific DAG Nodes
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    enum NodeType : unsigned {
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      // Start the numbering where the builtin ops and target ops leave off.
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      FIRST_NUMBER = ISD::BUILTIN_OP_END,
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      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
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                    // TargetExternalSymbol, and TargetGlobalAddress.
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      WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
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                    // PIC mode.
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      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
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      // Add pseudo op to model memcpy for struct byval.
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      COPY_STRUCT_BYVAL,
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      CALL,         // Function call.
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      CALL_PRED,    // Function call that's predicable.
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      CALL_NOLINK,  // Function call with branch not branch-and-link.
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      BRCOND,       // Conditional branch.
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      BR_JT,        // Jumptable branch.
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      BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
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      RET_FLAG,     // Return with a flag operand.
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      INTRET_FLAG,  // Interrupt return with an LR-offset and a flag operand.
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77
      PIC_ADD,      // Add with a PC operand and a PIC label.
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      ASRL,         // MVE long arithmetic shift right.
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      LSRL,         // MVE long shift right.
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      LSLL,         // MVE long shift left.
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      CMP,          // ARM compare instructions.
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      CMN,          // ARM CMN instructions.
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      CMPZ,         // ARM compare that sets only Z flag.
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      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
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      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
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      FMSTAT,       // ARM fmstat instruction.
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90
      CMOV,         // ARM conditional move instructions.
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      SUBS,         // Flag-setting subtraction.
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      SSAT,         // Signed saturation
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      USAT,         // Unsigned saturation
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      BCC_i64,
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      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
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102
      ADDC,         // Add with carry
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      ADDE,         // Add using carry
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      SUBC,         // Sub with carry
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      SUBE,         // Sub using carry
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      VMOVRRD,      // double to two gprs.
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      VMOVDRR,      // Two gprs to double.
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      VMOVSR,       // move gpr to single, used for f32 literal constructed in a gpr
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111
      EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
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      EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
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      EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
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      TC_RETURN,    // Tail call return pseudo.
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      THREAD_POINTER,
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      DYN_ALLOC,    // Dynamic allocation on the stack.
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      MEMBARRIER_MCR, // Memory barrier (MCR)
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      PRELOAD,      // Preload
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      WIN__CHKSTK,  // Windows' __chkstk call to do stack probing.
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      WIN__DBZCHK,  // Windows' divide by zero check
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      WLS,          // Low-overhead loops, While Loop Start
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      LOOP_DEC,     // Really a part of LE, performs the sub
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      LE,           // Low-overhead loops, Loop End
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      VCEQ,         // Vector compare equal.
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      VCEQZ,        // Vector compare equal to zero.
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      VCGE,         // Vector compare greater than or equal.
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      VCGEZ,        // Vector compare greater than or equal to zero.
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      VCLEZ,        // Vector compare less than or equal to zero.
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      VCGEU,        // Vector compare unsigned greater than or equal.
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      VCGT,         // Vector compare greater than.
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      VCGTZ,        // Vector compare greater than zero.
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      VCLTZ,        // Vector compare less than zero.
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      VCGTU,        // Vector compare unsigned greater than.
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      VTST,         // Vector test bits.
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      // Vector shift by vector
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      VSHLs,        // ...left/right by signed
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      VSHLu,        // ...left/right by unsigned
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      // Vector shift by immediate:
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      VSHLIMM,      // ...left
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      VSHRsIMM,     // ...right (signed)
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      VSHRuIMM,     // ...right (unsigned)
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      // Vector rounding shift by immediate:
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      VRSHRsIMM,    // ...right (signed)
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      VRSHRuIMM,    // ...right (unsigned)
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      VRSHRNIMM,    // ...right narrow
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      // Vector saturating shift by immediate:
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      VQSHLsIMM,    // ...left (signed)
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      VQSHLuIMM,    // ...left (unsigned)
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      VQSHLsuIMM,   // ...left (signed to unsigned)
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      VQSHRNsIMM,   // ...right narrow (signed)
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      VQSHRNuIMM,   // ...right narrow (unsigned)
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      VQSHRNsuIMM,  // ...right narrow (signed to unsigned)
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      // Vector saturating rounding shift by immediate:
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      VQRSHRNsIMM,  // ...right narrow (signed)
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      VQRSHRNuIMM,  // ...right narrow (unsigned)
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      VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
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      // Vector shift and insert:
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      VSLIIMM,      // ...left
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      VSRIIMM,      // ...right
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      // Vector get lane (VMOV scalar to ARM core register)
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      // (These are used for 8- and 16-bit element types only.)
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      VGETLANEu,    // zero-extend vector extract element
178
      VGETLANEs,    // sign-extend vector extract element
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180
      // Vector move immediate and move negated immediate:
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      VMOVIMM,
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      VMVNIMM,
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      // Vector move f32 immediate:
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      VMOVFPIMM,
186
187
      // Move H <-> R, clearing top 16 bits
188
      VMOVrh,
189
      VMOVhr,
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191
      // Vector duplicate:
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      VDUP,
193
      VDUPLANE,
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      // Vector shuffles:
196
      VEXT,         // extract
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      VREV64,       // reverse elements within 64-bit doublewords
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      VREV32,       // reverse elements within 32-bit words
199
      VREV16,       // reverse elements within 16-bit halfwords
200
      VZIP,         // zip (interleave)
201
      VUZP,         // unzip (deinterleave)
202
      VTRN,         // transpose
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      VTBL1,        // 1-register shuffle with mask
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      VTBL2,        // 2-register shuffle with mask
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      // Vector multiply long:
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      VMULLs,       // ...signed
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      VMULLu,       // ...unsigned
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      SMULWB,       // Signed multiply word by half word, bottom
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      SMULWT,       // Signed multiply word by half word, top
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      UMLAL,        // 64bit Unsigned Accumulate Multiply
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      SMLAL,        // 64bit Signed Accumulate Multiply
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      UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply
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      SMLALBB,      // 64-bit signed accumulate multiply bottom, bottom 16
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      SMLALBT,      // 64-bit signed accumulate multiply bottom, top 16
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      SMLALTB,      // 64-bit signed accumulate multiply top, bottom 16
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      SMLALTT,      // 64-bit signed accumulate multiply top, top 16
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      SMLALD,       // Signed multiply accumulate long dual
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      SMLALDX,      // Signed multiply accumulate long dual exchange
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      SMLSLD,       // Signed multiply subtract long dual
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      SMLSLDX,      // Signed multiply subtract long dual exchange
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      SMMLAR,       // Signed multiply long, round and add
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      SMMLSR,       // Signed multiply long, subtract and round
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      // Operands of the standard BUILD_VECTOR node are not legalized, which
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      // is fine if BUILD_VECTORs are always lowered to shuffles or other
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      // operations, but for ARM some BUILD_VECTORs are legal as-is and their
229
      // operands need to be legalized.  Define an ARM-specific version of
230
      // BUILD_VECTOR for this purpose.
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      BUILD_VECTOR,
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      // Bit-field insert
234
      BFI,
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      // Vector OR with immediate
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      VORRIMM,
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      // Vector AND with NOT of immediate
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      VBICIMM,
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      // Vector bitwise select
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      VBSL,
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      // Pseudo-instruction representing a memory copy using ldm/stm
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      // instructions.
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      MEMCPY,
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      // Vector load N-element structure to all lanes:
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      VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
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      VLD2DUP,
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      VLD3DUP,
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      VLD4DUP,
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      // NEON loads with post-increment base updates:
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      VLD1_UPD,
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      VLD2_UPD,
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      VLD3_UPD,
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      VLD4_UPD,
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      VLD2LN_UPD,
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      VLD3LN_UPD,
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      VLD4LN_UPD,
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      VLD1DUP_UPD,
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      VLD2DUP_UPD,
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      VLD3DUP_UPD,
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      VLD4DUP_UPD,
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      // NEON stores with post-increment base updates:
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      VST1_UPD,
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      VST2_UPD,
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      VST3_UPD,
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      VST4_UPD,
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      VST2LN_UPD,
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      VST3LN_UPD,
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      VST4LN_UPD
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    };
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  } // end namespace ARMISD
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  /// Define some predicates that are used for node matching.
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  namespace ARM {
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    bool isBitFieldInvertedMask(unsigned v);
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  } // end namespace ARM
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  //===--------------------------------------------------------------------===//
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  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
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  class ARMTargetLowering : public TargetLowering {
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  public:
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    explicit ARMTargetLowering(const TargetMachine &TM,
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                               const ARMSubtarget &STI);
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    unsigned getJumpTableEncoding() const override;
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    bool useSoftFloat() const override;
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297
    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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    /// ReplaceNodeResults - Replace the results of node with an illegal result
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    /// type with new values built out of custom code.
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    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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                            SelectionDAG &DAG) const override;
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    const char *getTargetNodeName(unsigned Opcode) const override;
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7.04k
    bool isSelectSupported(SelectSupportKind Kind) const override {
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7.04k
      // ARM does not support scalar condition selects on vectors.
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7.04k
      return (Kind != ScalarCondVectorVal);
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7.04k
    }
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    bool isReadOnly(const GlobalValue *GV) const;
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    /// getSetCCResultType - Return the value type to use for ISD::SETCC.
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    EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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                           EVT VT) const override;
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    MachineBasicBlock *
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    EmitInstrWithCustomInserter(MachineInstr &MI,
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                                MachineBasicBlock *MBB) const override;
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    void AdjustInstrPostInstrSelection(MachineInstr &MI,
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                                       SDNode *Node) const override;
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    SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
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    SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
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    SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
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    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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    bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
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331
    /// allowsMisalignedMemoryAccesses - Returns true if the target allows
332
    /// unaligned memory accesses of the specified type. Returns whether it
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    /// is "fast" by reference in the second argument.
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    bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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                                        unsigned Align,
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                                        MachineMemOperand::Flags Flags,
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                                        bool *Fast) const override;
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    EVT getOptimalMemOpType(uint64_t Size,
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                            unsigned DstAlign, unsigned SrcAlign,
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                            bool IsMemset, bool ZeroMemset,
342
                            bool MemcpyStrSrc,
343
                            const AttributeList &FuncAttributes) const override;
344
345
    bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
346
    bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
347
    bool isZExtFree(SDValue Val, EVT VT2) const override;
348
    bool shouldSinkOperands(Instruction *I,
349
                            SmallVectorImpl<Use *> &Ops) const override;
350
351
    bool isFNegFree(EVT VT) const override;
352
353
    bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
354
355
    bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
356
357
358
    /// isLegalAddressingMode - Return true if the addressing mode represented
359
    /// by AM is legal for this target, for a load/store of the specified type.
360
    bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
361
                               Type *Ty, unsigned AS,
362
                               Instruction *I = nullptr) const override;
363
364
    /// getScalingFactorCost - Return the cost of the scaling used in
365
    /// addressing mode represented by AM.
366
    /// If the AM is supported, the return value must be >= 0.
367
    /// If the AM is not supported, the return value must be negative.
368
    int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
369
                             unsigned AS) const override;
370
371
    bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
372
373
    /// Returns true if the addresing mode representing by AM is legal
374
    /// for the Thumb1 target, for a load/store of the specified type.
375
    bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
376
377
    /// isLegalICmpImmediate - Return true if the specified immediate is legal
378
    /// icmp immediate, that is the target has icmp instructions which can
379
    /// compare a register against the immediate without having to materialize
380
    /// the immediate into a register.
381
    bool isLegalICmpImmediate(int64_t Imm) const override;
382
383
    /// isLegalAddImmediate - Return true if the specified immediate is legal
384
    /// add immediate, that is the target has add instructions which can
385
    /// add a register and the immediate without having to materialize
386
    /// the immediate into a register.
387
    bool isLegalAddImmediate(int64_t Imm) const override;
388
389
    /// getPreIndexedAddressParts - returns true by value, base pointer and
390
    /// offset pointer and addressing mode by reference if the node's address
391
    /// can be legally represented as pre-indexed load / store address.
392
    bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
393
                                   ISD::MemIndexedMode &AM,
394
                                   SelectionDAG &DAG) const override;
395
396
    /// getPostIndexedAddressParts - returns true by value, base pointer and
397
    /// offset pointer and addressing mode by reference if this node can be
398
    /// combined with a load / store to form a post-indexed load / store.
399
    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
400
                                    SDValue &Offset, ISD::MemIndexedMode &AM,
401
                                    SelectionDAG &DAG) const override;
402
403
    void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
404
                                       const APInt &DemandedElts,
405
                                       const SelectionDAG &DAG,
406
                                       unsigned Depth) const override;
407
408
    bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
409
                                      TargetLoweringOpt &TLO) const override;
410
411
412
    bool ExpandInlineAsm(CallInst *CI) const override;
413
414
    ConstraintType getConstraintType(StringRef Constraint) const override;
415
416
    /// Examine constraint string and operand type and determine a weight value.
417
    /// The operand object must already have been set up with the operand type.
418
    ConstraintWeight getSingleConstraintMatchWeight(
419
      AsmOperandInfo &info, const char *constraint) const override;
420
421
    std::pair<unsigned, const TargetRegisterClass *>
422
    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
423
                                 StringRef Constraint, MVT VT) const override;
424
425
    const char *LowerXConstraint(EVT ConstraintVT) const override;
426
427
    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
428
    /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
429
    /// true it means one of the asm constraint of the inline asm instruction
430
    /// being processed is 'm'.
431
    void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
432
                                      std::vector<SDValue> &Ops,
433
                                      SelectionDAG &DAG) const override;
434
435
    unsigned
436
25
    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
437
25
      if (ConstraintCode == "Q")
438
7
        return InlineAsm::Constraint_Q;
439
18
      else if (ConstraintCode == "o")
440
1
        return InlineAsm::Constraint_o;
441
17
      else if (ConstraintCode.size() == 2) {
442
2
        if (ConstraintCode[0] == 'U') {
443
2
          switch(ConstraintCode[1]) {
444
2
          default:
445
0
            break;
446
2
          case 'm':
447
0
            return InlineAsm::Constraint_Um;
448
2
          case 'n':
449
0
            return InlineAsm::Constraint_Un;
450
2
          case 'q':
451
0
            return InlineAsm::Constraint_Uq;
452
2
          case 's':
453
0
            return InlineAsm::Constraint_Us;
454
2
          case 't':
455
0
            return InlineAsm::Constraint_Ut;
456
2
          case 'v':
457
2
            return InlineAsm::Constraint_Uv;
458
2
          case 'y':
459
0
            return InlineAsm::Constraint_Uy;
460
15
          }
461
15
        }
462
2
      }
463
15
      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
464
15
    }
465
466
582
    const ARMSubtarget* getSubtarget() const {
467
582
      return Subtarget;
468
582
    }
469
470
    /// getRegClassFor - Return the register class that should be used for the
471
    /// specified value type.
472
    const TargetRegisterClass *
473
    getRegClassFor(MVT VT, bool isDivergent = false) const override;
474
475
    /// Returns true if a cast between SrcAS and DestAS is a noop.
476
2
    bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
477
2
      // Addrspacecasts are always noops.
478
2
      return true;
479
2
    }
480
481
    bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
482
                                unsigned &PrefAlign) const override;
483
484
    /// createFastISel - This method returns a target specific FastISel object,
485
    /// or null if the target does not support "fast" ISel.
486
    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
487
                             const TargetLibraryInfo *libInfo) const override;
488
489
    Sched::Preference getSchedulingPreference(SDNode *N) const override;
490
491
    bool
492
    isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
493
    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
494
495
    /// isFPImmLegal - Returns true if the target can instruction select the
496
    /// specified FP immediate natively. If false, the legalizer will
497
    /// materialize the FP immediate as a load from a constant pool.
498
    bool isFPImmLegal(const APFloat &Imm, EVT VT,
499
                      bool ForCodeSize = false) const override;
500
501
    bool getTgtMemIntrinsic(IntrinsicInfo &Info,
502
                            const CallInst &I,
503
                            MachineFunction &MF,
504
                            unsigned Intrinsic) const override;
505
506
    /// Returns true if it is beneficial to convert a load of a constant
507
    /// to just the constant itself.
508
    bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
509
                                           Type *Ty) const override;
510
511
    /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
512
    /// with this index.
513
    bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
514
                                 unsigned Index) const override;
515
516
    /// Returns true if an argument of type Ty needs to be passed in a
517
    /// contiguous block of registers in calling convention CallConv.
518
    bool functionArgumentNeedsConsecutiveRegisters(
519
        Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
520
521
    /// If a physical register, this returns the register that receives the
522
    /// exception address on entry to an EH pad.
523
    unsigned
524
    getExceptionPointerRegister(const Constant *PersonalityFn) const override;
525
526
    /// If a physical register, this returns the register that receives the
527
    /// exception typeid on entry to a landing pad.
528
    unsigned
529
    getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
530
531
    Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
532
    Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
533
                          AtomicOrdering Ord) const override;
534
    Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
535
                                Value *Addr, AtomicOrdering Ord) const override;
536
537
    void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
538
539
    Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
540
                                  AtomicOrdering Ord) const override;
541
    Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
542
                                   AtomicOrdering Ord) const override;
543
544
25.4k
    unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
545
546
    bool lowerInterleavedLoad(LoadInst *LI,
547
                              ArrayRef<ShuffleVectorInst *> Shuffles,
548
                              ArrayRef<unsigned> Indices,
549
                              unsigned Factor) const override;
550
    bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
551
                               unsigned Factor) const override;
552
553
    bool shouldInsertFencesForAtomic(const Instruction *I) const override;
554
    TargetLoweringBase::AtomicExpansionKind
555
    shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
556
    bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
557
    TargetLoweringBase::AtomicExpansionKind
558
    shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
559
    TargetLoweringBase::AtomicExpansionKind
560
    shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
561
562
    bool useLoadStackGuardNode() const override;
563
564
    void insertSSPDeclarations(Module &M) const override;
565
    Value *getSDagStackGuard(const Module &M) const override;
566
    Function *getSSPStackGuardCheck(const Module &M) const override;
567
568
    bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
569
                                   unsigned &Cost) const override;
570
571
    bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
572
203k
                          const SelectionDAG &DAG) const override {
573
203k
      // Do not merge to larger than i32.
574
203k
      return (MemVT.getSizeInBits() <= 32);
575
203k
    }
576
577
    bool isCheapToSpeculateCttz() const override;
578
    bool isCheapToSpeculateCtlz() const override;
579
580
309
    bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
581
309
      return VT.isScalarInteger();
582
309
    }
583
584
894k
    bool supportSwiftError() const override {
585
894k
      return true;
586
894k
    }
587
588
32
    bool hasStandaloneRem(EVT VT) const override {
589
32
      return HasStandaloneRem;
590
32
    }
591
592
    bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
593
594
    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
595
    CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
596
597
    /// Returns true if \p VecTy is a legal interleaved access type. This
598
    /// function checks the vector element type and the overall width of the
599
    /// vector.
600
    bool isLegalInterleavedAccessType(VectorType *VecTy,
601
                                      const DataLayout &DL) const;
602
603
    bool alignLoopsWithOptSize() const override;
604
605
    /// Returns the number of interleaved accesses that will be generated when
606
    /// lowering accesses of the given type.
607
    unsigned getNumInterleavedAccesses(VectorType *VecTy,
608
                                       const DataLayout &DL) const;
609
610
    void finalizeLowering(MachineFunction &MF) const override;
611
612
    /// Return the correct alignment for the current calling convention.
613
    unsigned getABIAlignmentForCallingConv(Type *ArgTy,
614
                                           DataLayout DL) const override;
615
616
    bool isDesirableToCommuteWithShift(const SDNode *N,
617
                                       CombineLevel Level) const override;
618
619
    bool shouldFoldConstantShiftPairToMask(const SDNode *N,
620
                                           CombineLevel Level) const override;
621
622
    bool preferIncOfAddToSubOfNot(EVT VT) const override;
623
624
  protected:
625
    std::pair<const TargetRegisterClass *, uint8_t>
626
    findRepresentativeClass(const TargetRegisterInfo *TRI,
627
                            MVT VT) const override;
628
629
  private:
630
    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
631
    /// make the right decision when generating code for different targets.
632
    const ARMSubtarget *Subtarget;
633
634
    const TargetRegisterInfo *RegInfo;
635
636
    const InstrItineraryData *Itins;
637
638
    /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
639
    unsigned ARMPCLabelIndex;
640
641
    // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
642
    // check.
643
    bool InsertFencesForAtomic;
644
645
    bool HasStandaloneRem = true;
646
647
    void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
648
    void addDRTypeForNEON(MVT VT);
649
    void addQRTypeForNEON(MVT VT);
650
    std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
651
652
    using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
653
654
    void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
655
                          SDValue &Arg, RegsToPassVector &RegsToPass,
656
                          CCValAssign &VA, CCValAssign &NextVA,
657
                          SDValue &StackPtr,
658
                          SmallVectorImpl<SDValue> &MemOpChains,
659
                          ISD::ArgFlagsTy Flags) const;
660
    SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
661
                                 SDValue &Root, SelectionDAG &DAG,
662
                                 const SDLoc &dl) const;
663
664
    CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
665
                                            bool isVarArg) const;
666
    CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
667
                                  bool isVarArg) const;
668
    SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
669
                             const SDLoc &dl, SelectionDAG &DAG,
670
                             const CCValAssign &VA,
671
                             ISD::ArgFlagsTy Flags) const;
672
    SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
673
    SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
674
    SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
675
    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
676
                                    const ARMSubtarget *Subtarget) const;
677
    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
678
    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
679
    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
680
    SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
681
    SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
682
    SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
683
    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
684
    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
685
                                            SelectionDAG &DAG) const;
686
    SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
687
                                 SelectionDAG &DAG,
688
                                 TLSModel::Model model) const;
689
    SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
690
    SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
691
    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
692
    SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
693
    SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
694
    SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
695
    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
696
    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
697
    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
698
    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
699
    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
700
    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
701
    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
702
    SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
703
    SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
704
    SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
705
    SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
706
                            const ARMSubtarget *ST) const;
707
    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
708
                              const ARMSubtarget *ST) const;
709
    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
710
    SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
711
    SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
712
    SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
713
    void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
714
                           SmallVectorImpl<SDValue> &Results) const;
715
    SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
716
                                   SDValue &Chain) const;
717
    SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
718
    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
719
    SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
720
    SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
721
    SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
722
    SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
723
    void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
724
                  SelectionDAG &DAG) const;
725
726
    unsigned getRegisterByName(const char* RegName, EVT VT,
727
                               SelectionDAG &DAG) const override;
728
729
    SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
730
                          SmallVectorImpl<SDNode *> &Created) const override;
731
732
    /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
733
    /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
734
    /// expanded to FMAs when this method returns true, otherwise fmuladd is
735
    /// expanded to fmul + fadd.
736
    ///
737
    /// ARM supports both fused and unfused multiply-add operations; we already
738
    /// lower a pair of fmul and fadd to the latter so it's not clear that there
739
    /// would be a gain or that the gain would be worthwhile enough to risk
740
    /// correctness bugs.
741
5.39k
    bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
742
743
    SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
744
745
    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
746
                            CallingConv::ID CallConv, bool isVarArg,
747
                            const SmallVectorImpl<ISD::InputArg> &Ins,
748
                            const SDLoc &dl, SelectionDAG &DAG,
749
                            SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
750
                            SDValue ThisVal) const;
751
752
25.9k
    bool supportSplitCSR(MachineFunction *MF) const override {
753
25.9k
      return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
754
25.9k
          
MF->getFunction().hasFnAttribute(Attribute::NoUnwind)35
;
755
25.9k
    }
756
757
    void initializeSplitCSR(MachineBasicBlock *Entry) const override;
758
    void insertCopiesSplitCSR(
759
      MachineBasicBlock *Entry,
760
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
761
762
    SDValue
763
    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
764
                         const SmallVectorImpl<ISD::InputArg> &Ins,
765
                         const SDLoc &dl, SelectionDAG &DAG,
766
                         SmallVectorImpl<SDValue> &InVals) const override;
767
768
    int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
769
                       SDValue &Chain, const Value *OrigArg,
770
                       unsigned InRegsParamRecordIdx, int ArgOffset,
771
                       unsigned ArgSize) const;
772
773
    void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
774
                              const SDLoc &dl, SDValue &Chain,
775
                              unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
776
                              bool ForceMutable = false) const;
777
778
    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
779
                      SmallVectorImpl<SDValue> &InVals) const override;
780
781
    /// HandleByVal - Target-specific cleanup for ByVal support.
782
    void HandleByVal(CCState *, unsigned &, unsigned) const override;
783
784
    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
785
    /// for tail call optimization. Targets which want to do tail call
786
    /// optimization should implement this function.
787
    bool IsEligibleForTailCallOptimization(
788
        SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
789
        bool isCalleeStructRet, bool isCallerStructRet,
790
        const SmallVectorImpl<ISD::OutputArg> &Outs,
791
        const SmallVectorImpl<SDValue> &OutVals,
792
        const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
793
        const bool isIndirect) const;
794
795
    bool CanLowerReturn(CallingConv::ID CallConv,
796
                        MachineFunction &MF, bool isVarArg,
797
                        const SmallVectorImpl<ISD::OutputArg> &Outs,
798
                        LLVMContext &Context) const override;
799
800
    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
801
                        const SmallVectorImpl<ISD::OutputArg> &Outs,
802
                        const SmallVectorImpl<SDValue> &OutVals,
803
                        const SDLoc &dl, SelectionDAG &DAG) const override;
804
805
    bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
806
807
    bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
808
809
5.36k
    bool shouldConsiderGEPOffsetSplit() const override { return true; }
810
811
    bool isUnsupportedFloatingType(EVT VT) const;
812
813
    SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
814
                    SDValue ARMcc, SDValue CCR, SDValue Cmp,
815
                    SelectionDAG &DAG) const;
816
    SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
817
                      SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
818
    SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
819
                      const SDLoc &dl, bool InvalidOnQNaN) const;
820
    SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
821
822
    SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
823
824
    void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
825
                                MachineBasicBlock *DispatchBB, int FI) const;
826
827
    void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
828
829
    bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
830
831
    MachineBasicBlock *EmitStructByval(MachineInstr &MI,
832
                                       MachineBasicBlock *MBB) const;
833
834
    MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
835
                                           MachineBasicBlock *MBB) const;
836
    MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
837
                                           MachineBasicBlock *MBB) const;
838
    void addMVEVectorTypes(bool HasMVEFP);
839
    void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
840
    void setAllExpand(MVT VT);
841
  };
842
843
  enum VMOVModImmType {
844
    VMOVModImm,
845
    VMVNModImm,
846
    MVEVMVNModImm,
847
    OtherModImm
848
  };
849
850
  namespace ARM {
851
852
    FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
853
                             const TargetLibraryInfo *libInfo);
854
855
  } // end namespace ARM
856
857
} // end namespace llvm
858
859
#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H