Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
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1
//===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
/// \file
9
/// This file implements the targeting of the RegisterBankInfo class for ARM.
10
/// \todo This should be generated by TableGen.
11
//===----------------------------------------------------------------------===//
12
13
#include "ARMRegisterBankInfo.h"
14
#include "ARMInstrInfo.h" // For the register classes
15
#include "ARMSubtarget.h"
16
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
17
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
18
#include "llvm/CodeGen/MachineRegisterInfo.h"
19
#include "llvm/CodeGen/TargetRegisterInfo.h"
20
21
#define GET_TARGET_REGBANK_IMPL
22
#include "ARMGenRegisterBank.inc"
23
24
using namespace llvm;
25
26
// FIXME: TableGen this.
27
// If it grows too much and TableGen still isn't ready to do the job, extract it
28
// into an ARMGenRegisterBankInfo.def (similar to AArch64).
29
namespace llvm {
30
namespace ARM {
31
enum PartialMappingIdx {
32
  PMI_GPR,
33
  PMI_SPR,
34
  PMI_DPR,
35
  PMI_Min = PMI_GPR,
36
};
37
38
RegisterBankInfo::PartialMapping PartMappings[]{
39
    // GPR Partial Mapping
40
    {0, 32, GPRRegBank},
41
    // SPR Partial Mapping
42
    {0, 32, FPRRegBank},
43
    // DPR Partial Mapping
44
    {0, 64, FPRRegBank},
45
};
46
47
#ifndef NDEBUG
48
static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM,
49
                             unsigned Start, unsigned Length,
50
                             unsigned RegBankID) {
51
  return PM.StartIdx == Start && PM.Length == Length &&
52
         PM.RegBank->getID() == RegBankID;
53
}
54
55
static void checkPartialMappings() {
56
  assert(
57
      checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
58
      "Wrong mapping for GPR");
59
  assert(
60
      checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) &&
61
      "Wrong mapping for SPR");
62
  assert(
63
      checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) &&
64
      "Wrong mapping for DPR");
65
}
66
#endif
67
68
enum ValueMappingIdx {
69
  InvalidIdx = 0,
70
  GPR3OpsIdx = 1,
71
  SPR3OpsIdx = 4,
72
  DPR3OpsIdx = 7,
73
};
74
75
RegisterBankInfo::ValueMapping ValueMappings[] = {
76
    // invalid
77
    {nullptr, 0},
78
    // 3 ops in GPRs
79
    {&PartMappings[PMI_GPR - PMI_Min], 1},
80
    {&PartMappings[PMI_GPR - PMI_Min], 1},
81
    {&PartMappings[PMI_GPR - PMI_Min], 1},
82
    // 3 ops in SPRs
83
    {&PartMappings[PMI_SPR - PMI_Min], 1},
84
    {&PartMappings[PMI_SPR - PMI_Min], 1},
85
    {&PartMappings[PMI_SPR - PMI_Min], 1},
86
    // 3 ops in DPRs
87
    {&PartMappings[PMI_DPR - PMI_Min], 1},
88
    {&PartMappings[PMI_DPR - PMI_Min], 1},
89
    {&PartMappings[PMI_DPR - PMI_Min], 1}};
90
91
#ifndef NDEBUG
92
static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
93
                              RegisterBankInfo::PartialMapping *BreakDown) {
94
  return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
95
}
96
97
static void checkValueMappings() {
98
  assert(checkValueMapping(ValueMappings[GPR3OpsIdx],
99
                           &PartMappings[PMI_GPR - PMI_Min]) &&
100
         "Wrong value mapping for 3 GPR ops instruction");
101
  assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1],
102
                           &PartMappings[PMI_GPR - PMI_Min]) &&
103
         "Wrong value mapping for 3 GPR ops instruction");
104
  assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2],
105
                           &PartMappings[PMI_GPR - PMI_Min]) &&
106
         "Wrong value mapping for 3 GPR ops instruction");
107
108
  assert(checkValueMapping(ValueMappings[SPR3OpsIdx],
109
                           &PartMappings[PMI_SPR - PMI_Min]) &&
110
         "Wrong value mapping for 3 SPR ops instruction");
111
  assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1],
112
                           &PartMappings[PMI_SPR - PMI_Min]) &&
113
         "Wrong value mapping for 3 SPR ops instruction");
114
  assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2],
115
                           &PartMappings[PMI_SPR - PMI_Min]) &&
116
         "Wrong value mapping for 3 SPR ops instruction");
117
118
  assert(checkValueMapping(ValueMappings[DPR3OpsIdx],
119
                           &PartMappings[PMI_DPR - PMI_Min]) &&
120
         "Wrong value mapping for 3 DPR ops instruction");
121
  assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1],
122
                           &PartMappings[PMI_DPR - PMI_Min]) &&
123
         "Wrong value mapping for 3 DPR ops instruction");
124
  assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2],
125
                           &PartMappings[PMI_DPR - PMI_Min]) &&
126
         "Wrong value mapping for 3 DPR ops instruction");
127
}
128
#endif
129
} // end namespace arm
130
} // end namespace llvm
131
132
ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
133
7.46k
    : ARMGenRegisterBankInfo() {
134
7.46k
  static bool AlreadyInit = false;
135
7.46k
  // We have only one set of register banks, whatever the subtarget
136
7.46k
  // is. Therefore, the initialization of the RegBanks table should be
137
7.46k
  // done only once. Indeed the table of all register banks
138
7.46k
  // (ARM::RegBanks) is unique in the compiler. At some point, it
139
7.46k
  // will get tablegen'ed and the whole constructor becomes empty.
140
7.46k
  if (AlreadyInit)
141
2.29k
    return;
142
5.17k
  AlreadyInit = true;
143
5.17k
144
5.17k
  const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
145
5.17k
  (void)RBGPR;
146
5.17k
  assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147
5.17k
148
5.17k
  // Initialize the GPR bank.
149
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
150
5.17k
         "Subclass not added?");
151
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
152
5.17k
         "Subclass not added?");
153
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
154
5.17k
         "Subclass not added?");
155
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
156
5.17k
         "Subclass not added?");
157
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
158
5.17k
         "Subclass not added?");
159
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
160
5.17k
         "Subclass not added?");
161
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
162
5.17k
         "Subclass not added?");
163
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
164
5.17k
         "Subclass not added?");
165
5.17k
  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&
166
5.17k
         "Subclass not added?");
167
5.17k
  assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
168
5.17k
169
#ifndef NDEBUG
170
  ARM::checkPartialMappings();
171
  ARM::checkValueMappings();
172
#endif
173
}
174
175
const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
176
5.05k
    const TargetRegisterClass &RC) const {
177
5.05k
  using namespace ARM;
178
5.05k
179
5.05k
  switch (RC.getID()) {
180
5.05k
  case GPRRegClassID:
181
4.31k
  case GPRwithAPSRRegClassID:
182
4.31k
  case GPRnopcRegClassID:
183
4.31k
  case rGPRRegClassID:
184
4.31k
  case GPRspRegClassID:
185
4.31k
  case tGPR_and_tcGPRRegClassID:
186
4.31k
  case tcGPRRegClassID:
187
4.31k
  case tGPRRegClassID:
188
4.31k
  case tGPREvenRegClassID:
189
4.31k
  case tGPROddRegClassID:
190
4.31k
  case tGPR_and_tGPREvenRegClassID:
191
4.31k
  case tGPR_and_tGPROddRegClassID:
192
4.31k
  case tGPREven_and_tcGPRRegClassID:
193
4.31k
  case tGPREven_and_tGPR_and_tcGPRRegClassID:
194
4.31k
  case tGPROdd_and_tcGPRRegClassID:
195
4.31k
    return getRegBank(ARM::GPRRegBankID);
196
4.31k
  case HPRRegClassID:
197
740
  case SPR_8RegClassID:
198
740
  case SPRRegClassID:
199
740
  case DPR_8RegClassID:
200
740
  case DPRRegClassID:
201
740
  case QPRRegClassID:
202
740
    return getRegBank(ARM::FPRRegBankID);
203
740
  default:
204
0
    llvm_unreachable("Unsupported register kind");
205
0
  }
206
0
207
0
  llvm_unreachable("Switch should handle all register classes");
208
0
}
209
210
const RegisterBankInfo::InstructionMapping &
211
1.84k
ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
212
1.84k
  auto Opc = MI.getOpcode();
213
1.84k
214
1.84k
  // Try the default logic for non-generic instructions that are either copies
215
1.84k
  // or already have some operands assigned to banks.
216
1.84k
  if (!isPreISelGenericOpcode(Opc) || 
Opc == TargetOpcode::G_PHI690
) {
217
1.15k
    const InstructionMapping &Mapping = getInstrMappingImpl(MI);
218
1.15k
    if (Mapping.isValid())
219
1.15k
      return Mapping;
220
692
  }
221
692
222
692
  using namespace TargetOpcode;
223
692
224
692
  const MachineFunction &MF = *MI.getParent()->getParent();
225
692
  const MachineRegisterInfo &MRI = MF.getRegInfo();
226
692
  unsigned NumOperands = MI.getNumOperands();
227
692
  const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
228
692
229
692
  switch (Opc) {
230
692
  case G_ADD:
231
29
  case G_SUB: {
232
29
    // Integer operations where the source and destination are in the
233
29
    // same register class.
234
29
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
235
29
    OperandsMapping = Ty.getSizeInBits() == 64
236
29
                          ? 
&ARM::ValueMappings[ARM::DPR3OpsIdx]0
237
29
                          : &ARM::ValueMappings[ARM::GPR3OpsIdx];
238
29
    break;
239
29
  }
240
211
  case G_MUL:
241
211
  case G_AND:
242
211
  case G_OR:
243
211
  case G_XOR:
244
211
  case G_LSHR:
245
211
  case G_ASHR:
246
211
  case G_SHL:
247
211
  case G_SDIV:
248
211
  case G_UDIV:
249
211
  case G_SEXT:
250
211
  case G_ZEXT:
251
211
  case G_ANYEXT:
252
211
  case G_GEP:
253
211
  case G_INTTOPTR:
254
211
  case G_PTRTOINT:
255
211
  case G_CTLZ:
256
211
    // FIXME: We're abusing the fact that everything lives in a GPR for now; in
257
211
    // the real world we would use different mappings.
258
211
    OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
259
211
    break;
260
211
  case G_TRUNC: {
261
26
    // In some cases we may end up with a G_TRUNC from a 64-bit value to a
262
26
    // 32-bit value. This isn't a real floating point trunc (that would be a
263
26
    // G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear
264
26
    // because the legalizer doesn't distinguish between integer and floating
265
26
    // point values so it may leave some 64-bit integers un-narrowed. Until we
266
26
    // have a more principled solution that doesn't let such things sneak all
267
26
    // the way to this point, just map the source to a DPR and the destination
268
26
    // to a GPR.
269
26
    LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
270
26
    OperandsMapping =
271
26
        LargeTy.getSizeInBits() <= 32
272
26
            ? 
&ARM::ValueMappings[ARM::GPR3OpsIdx]24
273
26
            : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
274
2
                                  &ARM::ValueMappings[ARM::DPR3OpsIdx]});
275
26
    break;
276
211
  }
277
211
  case G_LOAD:
278
144
  case G_STORE: {
279
144
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
280
144
    OperandsMapping =
281
144
        Ty.getSizeInBits() == 64
282
144
            ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
283
4
                                  &ARM::ValueMappings[ARM::GPR3OpsIdx]})
284
144
            : 
&ARM::ValueMappings[ARM::GPR3OpsIdx]140
;
285
144
    break;
286
144
  }
287
144
  case G_FADD:
288
32
  case G_FSUB:
289
32
  case G_FMUL:
290
32
  case G_FDIV:
291
32
  case G_FNEG: {
292
32
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
293
32
    OperandsMapping =Ty.getSizeInBits() == 64
294
32
                          ? 
&ARM::ValueMappings[ARM::DPR3OpsIdx]16
295
32
                          : 
&ARM::ValueMappings[ARM::SPR3OpsIdx]16
;
296
32
    break;
297
32
  }
298
32
  case G_FMA: {
299
4
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
300
4
    OperandsMapping =
301
4
        Ty.getSizeInBits() == 64
302
4
            ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
303
2
                                  &ARM::ValueMappings[ARM::DPR3OpsIdx],
304
2
                                  &ARM::ValueMappings[ARM::DPR3OpsIdx],
305
2
                                  &ARM::ValueMappings[ARM::DPR3OpsIdx]})
306
4
            : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
307
2
                                  &ARM::ValueMappings[ARM::SPR3OpsIdx],
308
2
                                  &ARM::ValueMappings[ARM::SPR3OpsIdx],
309
2
                                  &ARM::ValueMappings[ARM::SPR3OpsIdx]});
310
4
    break;
311
32
  }
312
32
  case G_FPEXT: {
313
2
    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
314
2
    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
315
2
    if (ToTy.getSizeInBits() == 64 && FromTy.getSizeInBits() == 32)
316
2
      OperandsMapping =
317
2
          getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
318
2
                              &ARM::ValueMappings[ARM::SPR3OpsIdx]});
319
2
    break;
320
32
  }
321
32
  case G_FPTRUNC: {
322
2
    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
323
2
    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
324
2
    if (ToTy.getSizeInBits() == 32 && FromTy.getSizeInBits() == 64)
325
2
      OperandsMapping =
326
2
          getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
327
2
                              &ARM::ValueMappings[ARM::DPR3OpsIdx]});
328
2
    break;
329
32
  }
330
32
  case G_FPTOSI:
331
8
  case G_FPTOUI: {
332
8
    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
333
8
    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
334
8
    if ((FromTy.getSizeInBits() == 32 || 
FromTy.getSizeInBits() == 644
) &&
335
8
        ToTy.getSizeInBits() == 32)
336
8
      OperandsMapping =
337
8
          FromTy.getSizeInBits() == 64
338
8
              ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
339
4
                                    &ARM::ValueMappings[ARM::DPR3OpsIdx]})
340
8
              : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
341
4
                                    &ARM::ValueMappings[ARM::SPR3OpsIdx]});
342
8
    break;
343
8
  }
344
8
  case G_SITOFP:
345
8
  case G_UITOFP: {
346
8
    LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
347
8
    LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
348
8
    if (FromTy.getSizeInBits() == 32 &&
349
8
        (ToTy.getSizeInBits() == 32 || 
ToTy.getSizeInBits() == 644
))
350
8
      OperandsMapping =
351
8
          ToTy.getSizeInBits() == 64
352
8
              ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
353
4
                                    &ARM::ValueMappings[ARM::GPR3OpsIdx]})
354
8
              : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
355
4
                                    &ARM::ValueMappings[ARM::GPR3OpsIdx]});
356
8
    break;
357
8
  }
358
8
  case G_FCONSTANT: {
359
4
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
360
4
    OperandsMapping = getOperandsMapping(
361
4
        {Ty.getSizeInBits() == 64 ? 
&ARM::ValueMappings[ARM::DPR3OpsIdx]2
362
4
                                  : 
&ARM::ValueMappings[ARM::SPR3OpsIdx]2
,
363
4
         nullptr});
364
4
    break;
365
8
  }
366
162
  case G_CONSTANT:
367
162
  case G_FRAME_INDEX:
368
162
  case G_GLOBAL_VALUE:
369
162
    OperandsMapping =
370
162
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
371
162
    break;
372
162
  case G_SELECT: {
373
4
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
374
4
    (void)Ty;
375
4
    LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
376
4
    (void)Ty2;
377
4
    assert(Ty.getSizeInBits() == 32 && "Unsupported size for G_SELECT");
378
4
    assert(Ty2.getSizeInBits() == 1 && "Unsupported size for G_SELECT");
379
4
    OperandsMapping =
380
4
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
381
4
                            &ARM::ValueMappings[ARM::GPR3OpsIdx],
382
4
                            &ARM::ValueMappings[ARM::GPR3OpsIdx],
383
4
                            &ARM::ValueMappings[ARM::GPR3OpsIdx]});
384
4
    break;
385
162
  }
386
162
  case G_ICMP: {
387
9
    LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
388
9
    (void)Ty2;
389
9
    assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_ICMP");
390
9
    OperandsMapping =
391
9
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
392
9
                            &ARM::ValueMappings[ARM::GPR3OpsIdx],
393
9
                            &ARM::ValueMappings[ARM::GPR3OpsIdx]});
394
9
    break;
395
162
  }
396
162
  case G_FCMP: {
397
6
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
398
6
    (void)Ty;
399
6
    LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
400
6
    LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
401
6
    (void)Ty2;
402
6
    assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
403
6
    assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
404
6
           "Mismatched operand sizes for G_FCMP");
405
6
406
6
    unsigned Size = Ty1.getSizeInBits();
407
6
    assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
408
6
409
6
    auto FPRValueMapping = Size == 32 ? 
&ARM::ValueMappings[ARM::SPR3OpsIdx]4
410
6
                                      : 
&ARM::ValueMappings[ARM::DPR3OpsIdx]2
;
411
6
    OperandsMapping =
412
6
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
413
6
                            FPRValueMapping, FPRValueMapping});
414
6
    break;
415
162
  }
416
162
  case G_MERGE_VALUES: {
417
12
    // We only support G_MERGE_VALUES for creating a double precision floating
418
12
    // point value out of two GPRs.
419
12
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
420
12
    LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
421
12
    LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
422
12
    if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
423
12
        Ty2.getSizeInBits() != 32)
424
0
      return getInvalidInstructionMapping();
425
12
    OperandsMapping =
426
12
        getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
427
12
                            &ARM::ValueMappings[ARM::GPR3OpsIdx],
428
12
                            &ARM::ValueMappings[ARM::GPR3OpsIdx]});
429
12
    break;
430
12
  }
431
12
  case G_UNMERGE_VALUES: {
432
7
    // We only support G_UNMERGE_VALUES for splitting a double precision
433
7
    // floating point value into two GPRs.
434
7
    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
435
7
    LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
436
7
    LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
437
7
    if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
438
7
        Ty2.getSizeInBits() != 64)
439
0
      return getInvalidInstructionMapping();
440
7
    OperandsMapping =
441
7
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
442
7
                            &ARM::ValueMappings[ARM::GPR3OpsIdx],
443
7
                            &ARM::ValueMappings[ARM::DPR3OpsIdx]});
444
7
    break;
445
7
  }
446
9
  case G_BR:
447
9
    OperandsMapping = getOperandsMapping({nullptr});
448
9
    break;
449
7
  case G_BRCOND:
450
7
    OperandsMapping =
451
7
        getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
452
7
    break;
453
7
  case DBG_VALUE: {
454
6
    SmallVector<const ValueMapping *, 4> OperandBanks(NumOperands);
455
6
    const MachineOperand &MaybeReg = MI.getOperand(0);
456
6
    if (MaybeReg.isReg() && MaybeReg.getReg()) {
457
6
      unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
458
6
      if (Size > 32 && 
Size != 642
)
459
0
        return getInvalidInstructionMapping();
460
6
      OperandBanks[0] = Size == 64 ? 
&ARM::ValueMappings[ARM::DPR3OpsIdx]2
461
6
                                   : 
&ARM::ValueMappings[ARM::GPR3OpsIdx]4
;
462
6
    }
463
6
    OperandsMapping = getOperandsMapping(OperandBanks);
464
6
    break;
465
6
  }
466
6
  default:
467
0
    return getInvalidInstructionMapping();
468
692
  }
469
692
470
#ifndef NDEBUG
471
  for (unsigned i = 0; i < NumOperands; i++) {
472
    for (const auto &Mapping : OperandsMapping[i]) {
473
      assert(
474
          (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
475
           MF.getSubtarget<ARMSubtarget>().hasVFP2Base()) &&
476
          "Trying to use floating point register bank on target without vfp");
477
    }
478
  }
479
#endif
480
481
692
  return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
482
692
                               NumOperands);
483
692
}