Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
Line
Count
Source
1
//===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the ARM subclass for SelectionDAGTargetInfo.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
14
#define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
15
16
#include "MCTargetDesc/ARMAddressingModes.h"
17
#include "llvm/CodeGen/RuntimeLibcalls.h"
18
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
19
20
namespace llvm {
21
22
namespace ARM_AM {
23
232k
  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24
232k
    switch (Opcode) {
25
232k
    
default: return ARM_AM::no_shift216k
;
26
232k
    
case ISD::SHL: return ARM_AM::lsl8.67k
;
27
232k
    
case ISD::SRL: return ARM_AM::lsr5.51k
;
28
232k
    
case ISD::SRA: return ARM_AM::asr1.12k
;
29
232k
    
case ISD::ROTR: return ARM_AM::ror36
;
30
232k
    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
31
232k
    // Can't handle RRX here, because it would require folding a flag into
32
232k
    // the addressing mode.  :(  This causes us to miss certain things.
33
232k
    //case ARMISD::RRX: return ARM_AM::rrx;
34
232k
    }
35
232k
  }
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
ARMISelDAGToDAG.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Line
Count
Source
23
216k
  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24
216k
    switch (Opcode) {
25
216k
    
default: return ARM_AM::no_shift201k
;
26
216k
    
case ISD::SHL: return ARM_AM::lsl8.56k
;
27
216k
    
case ISD::SRL: return ARM_AM::lsr5.30k
;
28
216k
    
case ISD::SRA: return ARM_AM::asr1.12k
;
29
216k
    
case ISD::ROTR: return ARM_AM::ror34
;
30
216k
    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
31
216k
    // Can't handle RRX here, because it would require folding a flag into
32
216k
    // the addressing mode.  :(  This causes us to miss certain things.
33
216k
    //case ARMISD::RRX: return ARM_AM::rrx;
34
216k
    }
35
216k
  }
ARMISelLowering.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Line
Count
Source
23
15.0k
  static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) {
24
15.0k
    switch (Opcode) {
25
15.0k
    
default: return ARM_AM::no_shift14.7k
;
26
15.0k
    
case ISD::SHL: return ARM_AM::lsl111
;
27
15.0k
    
case ISD::SRL: return ARM_AM::lsr213
;
28
15.0k
    
case ISD::SRA: return ARM_AM::asr2
;
29
15.0k
    
case ISD::ROTR: return ARM_AM::ror2
;
30
15.0k
    //case ISD::ROTL:  // Only if imm -> turn into ROTR.
31
15.0k
    // Can't handle RRX here, because it would require folding a flag into
32
15.0k
    // the addressing mode.  :(  This causes us to miss certain things.
33
15.0k
    //case ARMISD::RRX: return ARM_AM::rrx;
34
15.0k
    }
35
15.0k
  }
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARM_AM::getShiftOpcForNode(unsigned int)
36
}  // end namespace ARM_AM
37
38
class ARMSelectionDAGInfo : public SelectionDAGTargetInfo {
39
public:
40
  SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
41
                                  SDValue Chain, SDValue Dst, SDValue Src,
42
                                  SDValue Size, unsigned Align, bool isVolatile,
43
                                  bool AlwaysInline,
44
                                  MachinePointerInfo DstPtrInfo,
45
                                  MachinePointerInfo SrcPtrInfo) const override;
46
47
  SDValue
48
  EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
49
                           SDValue Dst, SDValue Src, SDValue Size,
50
                           unsigned Align, bool isVolatile,
51
                           MachinePointerInfo DstPtrInfo,
52
                           MachinePointerInfo SrcPtrInfo) const override;
53
54
  // Adjust parameters for memset, see RTABI section 4.3.4
55
  SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
56
                                  SDValue Chain, SDValue Op1, SDValue Op2,
57
                                  SDValue Op3, unsigned Align, bool isVolatile,
58
                                  MachinePointerInfo DstPtrInfo) const override;
59
60
  SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl,
61
                                 SDValue Chain, SDValue Dst, SDValue Src,
62
                                 SDValue Size, unsigned Align,
63
                                 RTLIB::Libcall LC) const;
64
};
65
66
}
67
68
#endif