Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMSubtarget.h
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//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMSelectionDAGInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/Target/TargetOptions.h"
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#include <memory>
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "ARMGenSubtargetInfo.inc"
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namespace llvm {
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class ARMBaseTargetMachine;
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class GlobalValue;
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class StringRef;
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class ARMSubtarget : public ARMGenSubtargetInfo {
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protected:
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  enum ARMProcFamilyEnum {
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    Others,
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    CortexA12,
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    CortexA15,
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    CortexA17,
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    CortexA32,
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    CortexA35,
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    CortexA5,
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    CortexA53,
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    CortexA55,
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    CortexA57,
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    CortexA7,
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    CortexA72,
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    CortexA73,
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    CortexA75,
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    CortexA76,
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    CortexA8,
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    CortexA9,
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    CortexM3,
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    CortexR4,
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    CortexR4F,
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    CortexR5,
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    CortexR52,
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    CortexR7,
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    Exynos,
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    Krait,
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    Kryo,
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    Swift
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  };
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  enum ARMProcClassEnum {
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    None,
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    AClass,
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    MClass,
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    RClass
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  };
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  enum ARMArchEnum {
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    ARMv2,
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    ARMv2a,
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    ARMv3,
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    ARMv3m,
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    ARMv4,
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    ARMv4t,
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    ARMv5,
91
    ARMv5t,
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    ARMv5te,
93
    ARMv5tej,
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    ARMv6,
95
    ARMv6k,
96
    ARMv6kz,
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    ARMv6m,
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    ARMv6sm,
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    ARMv6t2,
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    ARMv7a,
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    ARMv7em,
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    ARMv7m,
103
    ARMv7r,
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    ARMv7ve,
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    ARMv81a,
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    ARMv82a,
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    ARMv83a,
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    ARMv84a,
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    ARMv85a,
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    ARMv8a,
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    ARMv8mBaseline,
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    ARMv8mMainline,
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    ARMv8r,
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    ARMv81mMainline,
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  };
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public:
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  /// What kind of timing do load multiple/store multiple instructions have.
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  enum ARMLdStMultipleTiming {
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    /// Can load/store 2 registers/cycle.
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    DoubleIssue,
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    /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
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    /// is not 64-bit aligned.
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    DoubleIssueCheckUnalignedAccess,
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    /// Can load/store 1 register/cycle.
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    SingleIssue,
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    /// Can load/store 1 register/cycle, but needs an extra cycle for address
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    /// computation and potentially also for register writeback.
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    SingleIssuePlusExtras,
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  };
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protected:
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  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
134
  ARMProcFamilyEnum ARMProcFamily = Others;
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136
  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
137
  ARMProcClassEnum ARMProcClass = None;
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  /// ARMArch - ARM architecture
140
  ARMArchEnum ARMArch = ARMv4t;
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  /// HasV4TOps, HasV5TOps, HasV5TEOps,
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  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
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  /// Specify whether target support specific ARM ISA variants.
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  bool HasV4TOps = false;
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  bool HasV5TOps = false;
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  bool HasV5TEOps = false;
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  bool HasV6Ops = false;
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  bool HasV6MOps = false;
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  bool HasV6KOps = false;
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  bool HasV6T2Ops = false;
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  bool HasV7Ops = false;
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  bool HasV8Ops = false;
154
  bool HasV8_1aOps = false;
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  bool HasV8_2aOps = false;
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  bool HasV8_3aOps = false;
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  bool HasV8_4aOps = false;
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  bool HasV8_5aOps = false;
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  bool HasV8MBaselineOps = false;
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  bool HasV8MMainlineOps = false;
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  bool HasV8_1MMainlineOps = false;
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  bool HasMVEIntegerOps = false;
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  bool HasMVEFloatOps = false;
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  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
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  /// floating point ISAs are supported.
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  bool HasVFPv2 = false;
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  bool HasVFPv3 = false;
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  bool HasVFPv4 = false;
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  bool HasFPARMv8 = false;
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  bool HasNEON = false;
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  bool HasFPRegs = false;
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  bool HasFPRegs16 = false;
174
  bool HasFPRegs64 = false;
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176
  /// Versions of the VFP flags restricted to single precision, or to
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  /// 16 d-registers, or both.
178
  bool HasVFPv2SP = false;
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  bool HasVFPv3SP = false;
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  bool HasVFPv4SP = false;
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  bool HasFPARMv8SP = false;
182
  bool HasVFPv2D16 = false;
183
  bool HasVFPv3D16 = false;
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  bool HasVFPv4D16 = false;
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  bool HasFPARMv8D16 = false;
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  bool HasVFPv2D16SP = false;
187
  bool HasVFPv3D16SP = false;
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  bool HasVFPv4D16SP = false;
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  bool HasFPARMv8D16SP = false;
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  /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
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  bool HasDotProd = false;
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  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
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  /// specified. Use the method useNEONForSinglePrecisionFP() to
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  /// determine if NEON should actually be used.
197
  bool UseNEONForSinglePrecisionFP = false;
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  /// UseMulOps - True if non-microcoded fused integer multiply-add and
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  /// multiply-subtract instructions should be used.
201
  bool UseMulOps = false;
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  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
204
  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
205
  bool SlowFPVMLx = false;
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  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
208
  /// forwarding to allow mul + mla being issued back to back.
209
  bool HasVMLxForwarding = false;
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  /// SlowFPBrcc - True if floating point compare + branch is slow.
212
  bool SlowFPBrcc = false;
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  /// InThumbMode - True if compiling for Thumb, false for ARM.
215
  bool InThumbMode = false;
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  /// UseSoftFloat - True if we're using software floating point features.
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  bool UseSoftFloat = false;
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  /// UseMISched - True if MachineScheduler should be used for this subtarget.
221
  bool UseMISched = false;
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  /// DisablePostRAScheduler - False if scheduling should happen again after
224
  /// register allocation.
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  bool DisablePostRAScheduler = false;
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  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
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  bool UseAA = false;
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  /// HasThumb2 - True if Thumb2 instructions are supported.
231
  bool HasThumb2 = false;
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  /// NoARM - True if subtarget does not support ARM mode execution.
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  bool NoARM = false;
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  /// ReserveR9 - True if R9 is not available as a general purpose register.
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  bool ReserveR9 = false;
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  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
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  /// 32-bit imms (including global addresses).
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  bool NoMovt = false;
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  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
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  /// must be able to synthesize call stubs for interworking between ARM and
245
  /// Thumb.
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  bool SupportsTailCall = false;
247
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  /// HasFP16 - True if subtarget supports half-precision FP conversions
249
  bool HasFP16 = false;
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  /// HasFullFP16 - True if subtarget supports half-precision FP operations
252
  bool HasFullFP16 = false;
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  /// HasFP16FML - True if subtarget supports half-precision FP fml operations
255
  bool HasFP16FML = false;
256
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  /// HasD32 - True if subtarget has the full 32 double precision
258
  /// FP registers for VFPv3.
259
  bool HasD32 = false;
260
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  /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
262
  bool HasHardwareDivideInThumb = false;
263
264
  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
265
  bool HasHardwareDivideInARM = false;
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  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
268
  /// instructions.
269
  bool HasDataBarrier = false;
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  /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
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  /// instruction.
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  bool HasFullDataBarrier = false;
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  /// HasV7Clrex - True if the subtarget supports CLREX instructions
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  bool HasV7Clrex = false;
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  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
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  /// instructions
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  bool HasAcquireRelease = false;
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  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
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  /// over 16-bit ones.
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  bool Pref32BitThumb = false;
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  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
287
  /// that partially update CPSR and add false dependency on the previous
288
  /// CPSR setting instruction.
289
  bool AvoidCPSRPartialUpdate = false;
290
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  /// CheapPredicableCPSRDef - If true, disable +1 predication cost
292
  /// for instructions updating CPSR. Enabled for Cortex-A57.
293
  bool CheapPredicableCPSRDef = false;
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295
  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
296
  /// movs with shifter operand (i.e. asr, lsl, lsr).
297
  bool AvoidMOVsShifterOperand = false;
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299
  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
300
  /// avoid issue "normal" call instructions to callees which do not return.
301
  bool HasRetAddrStack = false;
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303
  /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
304
  /// a branch predictor or not changes the expected cost of taking a branch
305
  /// which affects the choice of whether to use predicated instructions.
306
  bool HasBranchPredictor = true;
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308
  /// HasMPExtension - True if the subtarget supports Multiprocessing
309
  /// extension (ARMv7 only).
310
  bool HasMPExtension = false;
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312
  /// HasVirtualization - True if the subtarget supports the Virtualization
313
  /// extension.
314
  bool HasVirtualization = false;
315
316
  /// HasFP64 - If true, the floating point unit supports double
317
  /// precision.
318
  bool HasFP64 = false;
319
320
  /// If true, the processor supports the Performance Monitor Extensions. These
321
  /// include a generic cycle-counter as well as more fine-grained (often
322
  /// implementation-specific) events.
323
  bool HasPerfMon = false;
324
325
  /// HasTrustZone - if true, processor supports TrustZone security extensions
326
  bool HasTrustZone = false;
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328
  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
329
  bool Has8MSecExt = false;
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331
  /// HasSHA2 - if true, processor supports SHA1 and SHA256
332
  bool HasSHA2 = false;
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334
  /// HasAES - if true, processor supports AES
335
  bool HasAES = false;
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337
  /// HasCrypto - if true, processor supports Cryptography extensions
338
  bool HasCrypto = false;
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340
  /// HasCRC - if true, processor supports CRC instructions
341
  bool HasCRC = false;
342
343
  /// HasRAS - if true, the processor supports RAS extensions
344
  bool HasRAS = false;
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346
  /// HasLOB - if true, the processor supports the Low Overhead Branch extension
347
  bool HasLOB = false;
348
349
  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
350
  /// particularly effective at zeroing a VFP register.
351
  bool HasZeroCycleZeroing = false;
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353
  /// HasFPAO - if true, processor  does positive address offset computation faster
354
  bool HasFPAO = false;
355
356
  /// HasFuseAES - if true, processor executes back to back AES instruction
357
  /// pairs faster.
358
  bool HasFuseAES = false;
359
360
  /// HasFuseLiterals - if true, processor executes back to back
361
  /// bottom and top halves of literal generation faster.
362
  bool HasFuseLiterals = false;
363
364
  /// If true, if conversion may decide to leave some instructions unpredicated.
365
  bool IsProfitableToUnpredicate = false;
366
367
  /// If true, VMOV will be favored over VGETLNi32.
368
  bool HasSlowVGETLNi32 = false;
369
370
  /// If true, VMOV will be favored over VDUP.
371
  bool HasSlowVDUP32 = false;
372
373
  /// If true, VMOVSR will be favored over VMOVDRR.
374
  bool PreferVMOVSR = false;
375
376
  /// If true, ISHST barriers will be used for Release semantics.
377
  bool PreferISHST = false;
378
379
  /// If true, a VLDM/VSTM starting with an odd register number is considered to
380
  /// take more microops than single VLDRS/VSTRS.
381
  bool SlowOddRegister = false;
382
383
  /// If true, loading into a D subregister will be penalized.
384
  bool SlowLoadDSubregister = false;
385
386
  /// If true, use a wider stride when allocating VFP registers.
387
  bool UseWideStrideVFP = false;
388
389
  /// If true, the AGU and NEON/FPU units are multiplexed.
390
  bool HasMuxedUnits = false;
391
392
  /// If true, VMOVS will never be widened to VMOVD.
393
  bool DontWidenVMOVS = false;
394
395
  /// If true, splat a register between VFP and NEON instructions.
396
  bool SplatVFPToNeon = false;
397
398
  /// If true, run the MLx expansion pass.
399
  bool ExpandMLx = false;
400
401
  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
402
  bool HasVMLxHazards = false;
403
404
  // If true, read thread pointer from coprocessor register.
405
  bool ReadTPHard = false;
406
407
  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
408
  bool UseNEONForFPMovs = false;
409
410
  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
411
  bool CheckVLDnAlign = false;
412
413
  /// If true, VFP instructions are not pipelined.
414
  bool NonpipelinedVFP = false;
415
416
  /// StrictAlign - If true, the subtarget disallows unaligned memory
417
  /// accesses for some types.  For details, see
418
  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
419
  bool StrictAlign = false;
420
421
  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
422
  ///  blocks to conform to ARMv8 rule.
423
  bool RestrictIT = false;
424
425
  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
426
  /// and such) instructions.
427
  bool HasDSP = false;
428
429
  /// NaCl TRAP instruction is generated instead of the regular TRAP.
430
  bool UseNaClTrap = false;
431
432
  /// Generate calls via indirect call instructions.
433
  bool GenLongCalls = false;
434
435
  /// Generate code that does not contain data access to code sections.
436
  bool GenExecuteOnly = false;
437
438
  /// Target machine allowed unsafe FP math (such as use of NEON fp)
439
  bool UnsafeFPMath = false;
440
441
  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
442
  bool UseSjLjEH = false;
443
444
  /// Has speculation barrier
445
  bool HasSB = false;
446
447
  /// Implicitly convert an instruction to a different one if its immediates
448
  /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
449
  bool NegativeImmediates = true;
450
451
  /// stackAlignment - The minimum alignment known to hold of the stack frame on
452
  /// entry to the function and which must be maintained by every function.
453
  unsigned stackAlignment = 4;
454
455
  /// CPUString - String name of used CPU.
456
  std::string CPUString;
457
458
  unsigned MaxInterleaveFactor = 1;
459
460
  /// Clearance before partial register updates (in number of instructions)
461
  unsigned PartialUpdateClearance = 0;
462
463
  /// What kind of timing do load multiple/store multiple have (double issue,
464
  /// single issue etc).
465
  ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
466
467
  /// The adjustment that we need to apply to get the operand latency from the
468
  /// operand cycle returned by the itinerary data for pre-ISel operands.
469
  int PreISelOperandLatencyAdjustment = 2;
470
471
  /// What alignment is preferred for loop bodies, in log2(bytes).
472
  unsigned PrefLoopAlignment = 0;
473
474
  /// OptMinSize - True if we're optimising for minimum code size, equal to
475
  /// the function attribute.
476
  bool OptMinSize = false;
477
478
  /// IsLittle - The target is Little Endian
479
  bool IsLittle;
480
481
  /// TargetTriple - What processor and OS we're targeting.
482
  Triple TargetTriple;
483
484
  /// SchedModel - Processor specific instruction costs.
485
  MCSchedModel SchedModel;
486
487
  /// Selected instruction itineraries (one entry per itinerary class.)
488
  InstrItineraryData InstrItins;
489
490
  /// Options passed via command line that could influence the target
491
  const TargetOptions &Options;
492
493
  const ARMBaseTargetMachine &TM;
494
495
public:
496
  /// This constructor initializes the data members to match that
497
  /// of the specified triple.
498
  ///
499
  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
500
               const ARMBaseTargetMachine &TM, bool IsLittle,
501
               bool MinSize = false);
502
503
  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
504
  /// that still makes it profitable to inline the call.
505
459
  unsigned getMaxInlineSizeThreshold() const {
506
459
    return 64;
507
459
  }
508
509
  /// ParseSubtargetFeatures - Parses features string setting specified
510
  /// subtarget options.  Definition of function is auto generated by tblgen.
511
  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
512
513
  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
514
  /// so that we can use initializer lists for subtarget initialization.
515
  ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
516
517
26.3k
  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
518
26.3k
    return &TSInfo;
519
26.3k
  }
520
521
4.66M
  const ARMBaseInstrInfo *getInstrInfo() const override {
522
4.66M
    return InstrInfo.get();
523
4.66M
  }
524
525
2.53M
  const ARMTargetLowering *getTargetLowering() const override {
526
2.53M
    return &TLInfo;
527
2.53M
  }
528
529
10.7M
  const ARMFrameLowering *getFrameLowering() const override {
530
10.7M
    return FrameLowering.get();
531
10.7M
  }
532
533
8.64M
  const ARMBaseRegisterInfo *getRegisterInfo() const override {
534
8.64M
    return &InstrInfo->getRegisterInfo();
535
8.64M
  }
536
537
  const CallLowering *getCallLowering() const override;
538
  const InstructionSelector *getInstructionSelector() const override;
539
  const LegalizerInfo *getLegalizerInfo() const override;
540
  const RegisterBankInfo *getRegBankInfo() const override;
541
542
private:
543
  ARMSelectionDAGInfo TSInfo;
544
  // Either Thumb1FrameLowering or ARMFrameLowering.
545
  std::unique_ptr<ARMFrameLowering> FrameLowering;
546
  // Either Thumb1InstrInfo or Thumb2InstrInfo.
547
  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
548
  ARMTargetLowering   TLInfo;
549
550
  /// GlobalISel related APIs.
551
  std::unique_ptr<CallLowering> CallLoweringInfo;
552
  std::unique_ptr<InstructionSelector> InstSelector;
553
  std::unique_ptr<LegalizerInfo> Legalizer;
554
  std::unique_ptr<RegisterBankInfo> RegBankInfo;
555
556
  void initializeEnvironment();
557
  void initSubtargetFeatures(StringRef CPU, StringRef FS);
558
  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
559
560
public:
561
  void computeIssueWidth();
562
563
42.7k
  bool hasV4TOps()  const { return HasV4TOps;  }
564
199k
  bool hasV5TOps()  const { return HasV5TOps;  }
565
15.5k
  bool hasV5TEOps() const { return HasV5TEOps; }
566
1.46M
  bool hasV6Ops()   const { return HasV6Ops;   }
567
7.47k
  bool hasV6MOps()  const { return HasV6MOps;  }
568
7.58k
  bool hasV6KOps()  const { return HasV6KOps; }
569
191k
  bool hasV6T2Ops() const { return HasV6T2Ops; }
570
7.88k
  bool hasV7Ops()   const { return HasV7Ops;  }
571
22.5k
  bool hasV8Ops()   const { return HasV8Ops;  }
572
7.47k
  bool hasV8_1aOps() const { return HasV8_1aOps; }
573
0
  bool hasV8_2aOps() const { return HasV8_2aOps; }
574
0
  bool hasV8_3aOps() const { return HasV8_3aOps; }
575
0
  bool hasV8_4aOps() const { return HasV8_4aOps; }
576
0
  bool hasV8_5aOps() const { return HasV8_5aOps; }
577
285k
  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
578
0
  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
579
7.50k
  bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; }
580
277k
  bool hasMVEIntegerOps() const { return HasMVEIntegerOps; }
581
7.65k
  bool hasMVEFloatOps() const { return HasMVEFloatOps; }
582
35.7k
  bool hasFPRegs() const { return HasFPRegs; }
583
8.83k
  bool hasFPRegs16() const { return HasFPRegs16; }
584
7.63k
  bool hasFPRegs64() const { return HasFPRegs64; }
585
586
  /// @{
587
  /// These functions are obsolete, please consider adding subtarget features
588
  /// or properties instead of calling them.
589
0
  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
590
802k
  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
591
824k
  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
592
808k
  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
593
805k
  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
594
482k
  bool isSwift()    const { return ARMProcFamily == Swift; }
595
88.2k
  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
596
808k
  bool isLikeA9() const { return isCortexA9() || 
isCortexA15()805k
||
isKrait()804k
; }
597
0
  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
598
804k
  bool isKrait() const { return ARMProcFamily == Krait; }
599
  /// @}
600
601
3.36k
  bool hasARMOps() const { return !NoARM; }
602
603
268k
  bool hasVFP2Base() const { return HasVFPv2D16SP; }
604
12.9k
  bool hasVFP3Base() const { return HasVFPv3D16SP; }
605
25.4k
  bool hasVFP4Base() const { return HasVFPv4D16SP; }
606
33.8k
  bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
607
3.73M
  bool hasNEON() const { return HasNEON;  }
608
0
  bool hasSHA2() const { return HasSHA2; }
609
0
  bool hasAES() const { return HasAES; }
610
7.51k
  bool hasCrypto() const { return HasCrypto; }
611
7.46k
  bool hasDotProd() const { return HasDotProd; }
612
7.47k
  bool hasCRC() const { return HasCRC; }
613
0
  bool hasRAS() const { return HasRAS; }
614
38.7k
  bool hasLOB() const { return HasLOB; }
615
0
  bool hasVirtualization() const { return HasVirtualization; }
616
617
87.6k
  bool useNEONForSinglePrecisionFP() const {
618
87.6k
    return hasNEON() && 
UseNEONForSinglePrecisionFP45.3k
;
619
87.6k
  }
620
621
16.1k
  bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
622
14.5k
  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
623
17.3k
  bool hasDataBarrier() const { return HasDataBarrier; }
624
0
  bool hasFullDataBarrier() const { return HasFullDataBarrier; }
625
7.79k
  bool hasV7Clrex() const { return HasV7Clrex; }
626
12.9k
  bool hasAcquireRelease() const { return HasAcquireRelease; }
627
628
61.5k
  bool hasAnyDataBarrier() const {
629
61.5k
    return HasDataBarrier || 
(16.2k
hasV6Ops()16.2k
&&
!isThumb()5.26k
);
630
61.5k
  }
631
632
8.40k
  bool useMulOps() const { return UseMulOps; }
633
1.88k
  bool useFPVMLx() const { return !SlowFPVMLx; }
634
115
  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
635
2
  bool isFPBrccSlow() const { return SlowFPBrcc; }
636
132k
  bool hasFP64() const { return HasFP64; }
637
7.46k
  bool hasPerfMon() const { return HasPerfMon; }
638
0
  bool hasTrustZone() const { return HasTrustZone; }
639
0
  bool has8MSecExt() const { return Has8MSecExt; }
640
7.67k
  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
641
105k
  bool hasFPAO() const { return HasFPAO; }
642
219
  bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
643
15.6k
  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
644
14.9k
  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
645
17.0k
  bool preferVMOVSR() const { return PreferVMOVSR; }
646
1.69k
  bool preferISHSTBarriers() const { return PreferISHST; }
647
25.2k
  bool expandMLx() const { return ExpandMLx; }
648
1.12k
  bool hasVMLxHazards() const { return HasVMLxHazards; }
649
88.0k
  bool hasSlowOddRegister() const { return SlowOddRegister; }
650
41.5k
  bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
651
2.10k
  bool useWideStrideVFP() const { return UseWideStrideVFP; }
652
67.4k
  bool hasMuxedUnits() const { return HasMuxedUnits; }
653
81.2k
  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
654
25.2k
  bool useSplatVFPToNeon() const { return SplatVFPToNeon; }
655
565k
  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
656
878k
  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
657
897
  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
658
42.4k
  bool prefers32BitThumb() const { return Pref32BitThumb; }
659
38.6k
  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
660
35.5k
  bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
661
7.53k
  bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
662
114
  bool hasRetAddrStack() const { return HasRetAddrStack; }
663
27.1k
  bool hasBranchPredictor() const { return HasBranchPredictor; }
664
7.46k
  bool hasMPExtension() const { return HasMPExtension; }
665
34.7k
  bool hasDSP() const { return HasDSP; }
666
15.3k
  bool useNaClTrap() const { return UseNaClTrap; }
667
8.25k
  bool useSjLjEH() const { return UseSjLjEH; }
668
0
  bool hasSB() const { return HasSB; }
669
58.8k
  bool genLongCalls() const { return GenLongCalls; }
670
57.8k
  bool genExecuteOnly() const { return GenExecuteOnly; }
671
672
22.2k
  bool hasFP16() const { return HasFP16; }
673
82.2k
  bool hasD32() const { return HasD32; }
674
67.4k
  bool hasFullFP16() const { return HasFullFP16; }
675
0
  bool hasFP16FML() const { return HasFP16FML; }
676
677
5.01k
  bool hasFuseAES() const { return HasFuseAES; }
678
4.97k
  bool hasFuseLiterals() const { return HasFuseLiterals; }
679
  /// Return true if the CPU supports any kind of instruction fusion.
680
4.83k
  bool hasFusion() const { return hasFuseAES() || 
hasFuseLiterals()4.83k
; }
681
682
37.3k
  const Triple &getTargetTriple() const { return TargetTriple; }
683
684
3.09M
  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
685
10.7k
  bool isTargetIOS() const { return TargetTriple.isiOS(); }
686
5.54k
  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
687
11.6k
  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
688
12.3k
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
689
16.1k
  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
690
0
  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
691
989k
  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
692
693
81.0k
  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
694
121k
  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
695
439k
  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
696
697
  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
698
  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
699
  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
700
  // even for GNUEABI, so we can make a distinction here and still conform to
701
  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
702
  // FIXME: The Darwin exception is temporary, while we move users to
703
  // "*-*-*-macho" triples as quickly as possible.
704
36.5k
  bool isTargetAEABI() const {
705
36.5k
    return (TargetTriple.getEnvironment() == Triple::EABI ||
706
36.5k
            
TargetTriple.getEnvironment() == Triple::EABIHF23.9k
) &&
707
36.5k
           
!isTargetDarwin()13.1k
&&
!isTargetWindows()11.1k
;
708
36.5k
  }
709
20.0k
  bool isTargetGNUAEABI() const {
710
20.0k
    return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
711
20.0k
            
TargetTriple.getEnvironment() == Triple::GNUEABIHF15.6k
) &&
712
20.0k
           
!isTargetDarwin()5.37k
&&
!isTargetWindows()5.37k
;
713
20.0k
  }
714
14.6k
  bool isTargetMuslAEABI() const {
715
14.6k
    return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
716
14.6k
            
TargetTriple.getEnvironment() == Triple::MuslEABIHF14.4k
) &&
717
14.6k
           
!isTargetDarwin()311
&&
!isTargetWindows()311
;
718
14.6k
  }
719
720
  // ARM Targets that support EHABI exception handling standard
721
  // Darwin uses SjLj. Other targets might need more checks.
722
749k
  bool isTargetEHABICompatible() const {
723
749k
    return (TargetTriple.getEnvironment() == Triple::EABI ||
724
749k
            
TargetTriple.getEnvironment() == Triple::GNUEABI677k
||
725
749k
            
TargetTriple.getEnvironment() == Triple::MuslEABI660k
||
726
749k
            
TargetTriple.getEnvironment() == Triple::EABIHF659k
||
727
749k
            
TargetTriple.getEnvironment() == Triple::GNUEABIHF652k
||
728
749k
            
TargetTriple.getEnvironment() == Triple::MuslEABIHF647k
||
729
749k
            
isTargetAndroid()647k
) &&
730
749k
           
!isTargetDarwin()104k
&&
!isTargetWindows()88.6k
;
731
749k
  }
732
733
  bool isTargetHardFloat() const;
734
735
655k
  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
736
737
  bool isXRaySupported() const override;
738
739
  bool isAPCS_ABI() const;
740
  bool isAAPCS_ABI() const;
741
  bool isAAPCS16_ABI() const;
742
743
  bool isROPI() const;
744
  bool isRWPI() const;
745
746
149k
  bool useMachineScheduler() const { return UseMISched; }
747
25.0k
  bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
748
147k
  bool useSoftFloat() const { return UseSoftFloat; }
749
3.30M
  bool isThumb() const { return InThumbMode; }
750
113k
  bool hasMinSize() const { return OptMinSize; }
751
3.66M
  bool isThumb1Only() const { return InThumbMode && 
!HasThumb23.13M
; }
752
2.69M
  bool isThumb2() const { return InThumbMode && 
HasThumb22.55M
; }
753
166k
  bool hasThumb2() const { return HasThumb2; }
754
405k
  bool isMClass() const { return ARMProcClass == MClass; }
755
0
  bool isRClass() const { return ARMProcClass == RClass; }
756
0
  bool isAClass() const { return ARMProcClass == AClass; }
757
14.9k
  bool isReadTPHard() const { return ReadTPHard; }
758
759
148k
  bool isR9Reserved() const {
760
148k
    return isTargetMachO() ? 
(91.3k
ReserveR991.3k
||
!HasV6Ops91.3k
) :
ReserveR957.5k
;
761
148k
  }
762
763
1.96M
  bool useR7AsFramePointer() const {
764
1.96M
    return isTargetDarwin() || 
(603k
!isTargetWindows()603k
&&
isThumb()593k
);
765
1.96M
  }
766
767
  /// Returns true if the frame setup is split into two separate pushes (first
768
  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
769
  /// to lr. This is always required on Thumb1-only targets, as the push and
770
  /// pop instructions can't access the high registers.
771
1.05M
  bool splitFramePushPop(const MachineFunction &MF) const {
772
1.05M
    return (useR7AsFramePointer() &&
773
1.05M
            
MF.getTarget().Options.DisableFramePointerElim(MF)840k
) ||
774
1.05M
           
isThumb1Only()475k
;
775
1.05M
  }
776
777
  bool useStride4VFPs() const;
778
779
  bool useMovt() const;
780
781
60.3k
  bool supportsTailCall() const { return SupportsTailCall; }
782
783
7.97k
  bool allowsUnalignedMem() const { return !StrictAlign; }
784
785
280k
  bool restrictIT() const { return RestrictIT; }
786
787
0
  const std::string & getCPUString() const { return CPUString; }
788
789
28.8k
  bool isLittle() const { return IsLittle; }
790
791
  unsigned getMispredictionPenalty() const;
792
793
  /// Returns true if machine scheduler should be enabled.
794
  bool enableMachineScheduler() const override;
795
796
  /// True for some subtargets at > -O0.
797
  bool enablePostRAScheduler() const override;
798
799
  /// Enable use of alias analysis during code generation (during MI
800
  /// scheduling, DAGCombine, etc.).
801
347k
  bool useAA() const override { return UseAA; }
802
803
  // enableAtomicExpand- True if we need to expand our atomics.
804
  bool enableAtomicExpand() const override;
805
806
  /// getInstrItins - Return the instruction itineraries based on subtarget
807
  /// selection.
808
225k
  const InstrItineraryData *getInstrItineraryData() const override {
809
225k
    return &InstrItins;
810
225k
  }
811
812
  /// getStackAlignment - Returns the minimum alignment known to hold of the
813
  /// stack frame on entry to the function and which must be maintained by every
814
  /// function for this subtarget.
815
7.46k
  unsigned getStackAlignment() const { return stackAlignment; }
816
817
1.17k
  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
818
819
495k
  unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
820
821
13.9k
  ARMLdStMultipleTiming getLdStMultipleTiming() const {
822
13.9k
    return LdStMultipleTiming;
823
13.9k
  }
824
825
87.1k
  int getPreISelOperandLatencyAdjustment() const {
826
87.1k
    return PreISelOperandLatencyAdjustment;
827
87.1k
  }
828
829
  /// True if the GV will be accessed via an indirect symbol.
830
  bool isGVIndirectSymbol(const GlobalValue *GV) const;
831
832
  /// Returns the constant pool modifier needed to access the GV.
833
  bool isGVInGOT(const GlobalValue *GV) const;
834
835
  /// True if fast-isel is used.
836
  bool useFastISel() const;
837
838
  /// Returns the correct return opcode for the current feature set.
839
  /// Use BX if available to allow mixing thumb/arm code, but fall back
840
  /// to plain mov pc,lr on ARMv4.
841
1.24k
  unsigned getReturnOpcode() const {
842
1.24k
    if (isThumb())
843
397
      return ARM::tBX_RET;
844
852
    if (hasV4TOps())
845
798
      return ARM::BX_RET;
846
54
    return ARM::MOVPCLR;
847
54
  }
848
849
  /// Allow movt+movw for PIC global address calculation.
850
  /// ELF does not have GOT relocations for movt+movw.
851
  /// ROPI does not use GOT.
852
105k
  bool allowPositionIndependentMovt() const {
853
105k
    return isROPI() || 
!isTargetELF()105k
;
854
105k
  }
855
856
7.46k
  unsigned getPrefLoopAlignment() const {
857
7.46k
    return PrefLoopAlignment;
858
7.46k
  }
859
860
  bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
861
                                   unsigned PhysReg) const override;
862
  unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
863
};
864
865
} // end namespace llvm
866
867
#endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H