Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMTargetMachine.h
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//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#include "ARMSubtarget.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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namespace llvm {
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class ARMBaseTargetMachine : public LLVMTargetMachine {
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public:
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  enum ARMABI {
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    ARM_ABI_UNKNOWN,
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    ARM_ABI_APCS,
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    ARM_ABI_AAPCS, // ARM EABI
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    ARM_ABI_AAPCS16
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  } TargetABI;
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protected:
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  std::unique_ptr<TargetLoweringObjectFile> TLOF;
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  bool isLittle;
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  mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
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public:
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  ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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                       StringRef FS, const TargetOptions &Options,
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                       Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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                       CodeGenOpt::Level OL, bool isLittle);
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  ~ARMBaseTargetMachine() override;
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  const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
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  // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
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  // subtargets are per-function entities based on the target-specific
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  // attributes of each function.
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  const ARMSubtarget *getSubtargetImpl() const = delete;
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  bool isLittleEndian() const { return isLittle; }
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  TargetTransformInfo getTargetTransformInfo(const Function &F) override;
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  // Pass Pipeline Configuration
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  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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  TargetLoweringObjectFile *getObjFileLowering() const override {
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    return TLOF.get();
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  }
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  bool isTargetHardFloat() const {
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    return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
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TargetTriple.getEnvironment() == Triple::MuslEABIHF4.59k
||
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TargetTriple.getEnvironment() == Triple::EABIHF4.59k
||
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(4.40k
TargetTriple.isOSBinFormatMachO()4.40k
&&
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4.40k
            
TargetTriple.getSubArch() == Triple::ARMSubArch_v7em953
) ||
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4.73k
           
TargetTriple.isOSWindows()4.39k
||
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TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS164.26k
;
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  }
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};
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/// ARM/Thumb little endian target machine.
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///
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class ARMLETargetMachine : public ARMBaseTargetMachine {
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public:
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  ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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                     StringRef FS, const TargetOptions &Options,
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                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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                     CodeGenOpt::Level OL, bool JIT);
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};
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/// ARM/Thumb big endian target machine.
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///
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class ARMBETargetMachine : public ARMBaseTargetMachine {
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public:
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  ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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                     StringRef FS, const TargetOptions &Options,
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                     Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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                     CodeGenOpt::Level OL, bool JIT);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H