Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
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//===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// ARM target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "ARMTargetMachine.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Constant.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/SubtargetFeature.h"
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namespace llvm {
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class APInt;
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class ARMTargetLowering;
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class Instruction;
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class Loop;
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class SCEV;
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class ScalarEvolution;
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class Type;
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class Value;
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class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
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  using BaseT = BasicTTIImplBase<ARMTTIImpl>;
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  using TTI = TargetTransformInfo;
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  friend BaseT;
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  const ARMSubtarget *ST;
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  const ARMTargetLowering *TLI;
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  // Currently the following features are excluded from InlineFeatureWhitelist.
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  // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
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  // Depending on whether they are set or unset, different
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  // instructions/registers are available. For example, inlining a callee with
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  // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
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  // fail if the callee uses ARM only instructions, e.g. in inline asm.
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  const FeatureBitset InlineFeatureWhitelist = {
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      ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
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      ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
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      ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
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      ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
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      ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
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      ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
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      ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
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      ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
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      ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
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      ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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      ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
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      ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
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      ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
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      ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
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      ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
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      ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
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      ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
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      ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
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      ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
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      ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
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      ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
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      ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
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      ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
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      ARM::FeatureNoNegativeImmediates
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  };
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6.89k
  const ARMSubtarget *getST() const { return ST; }
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2.14M
  const ARMTargetLowering *getTLI() const { return TLI; }
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public:
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  explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
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      : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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        TLI(ST->getTargetLowering()) {}
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  bool areInlineCompatible(const Function *Caller,
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                           const Function *Callee) const;
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  bool enableInterleavedAccessVectorization() { return true; }
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  bool shouldFavorBackedgeIndex(const Loop *L) const {
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    if (L->getHeader()->getParent()->hasOptSize())
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      return false;
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    return ST->isMClass() && 
ST->isThumb2()62.7k
&&
L->getNumBlocks() == 159.2k
;
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  }
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  /// Floating-point computation using ARMv8 AArch32 Advanced
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  /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
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  /// is IEEE-754 compliant, but it's not covered in this target.
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  bool isFPVectorizationPotentiallyUnsafe() {
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    return !ST->isTargetDarwin();
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  }
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  /// \name Scalar TTI Implementations
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  /// @{
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  int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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                            Type *Ty);
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  using BaseT::getIntImmCost;
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  int getIntImmCost(const APInt &Imm, Type *Ty);
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  int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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  /// @}
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  /// \name Vector TTI Implementations
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  /// @{
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  unsigned getNumberOfRegisters(bool Vector) {
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    if (Vector) {
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      if (ST->hasNEON())
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        return 16;
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      return 0;
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    }
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    if (ST->isThumb1Only())
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      return 8;
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    return 13;
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  }
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  unsigned getRegisterBitWidth(bool Vector) const {
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    if (Vector) {
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      if (ST->hasNEON())
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        return 128;
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      return 0;
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    }
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    return 32;
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  }
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  unsigned getMaxInterleaveFactor(unsigned VF) {
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    return ST->getMaxInterleaveFactor();
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  }
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  int getMemcpyCost(const Instruction *I);
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  int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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  int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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                       const Instruction *I = nullptr);
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  int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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                         const Instruction *I = nullptr);
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  int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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  int getAddressComputationCost(Type *Val, ScalarEvolution *SE,
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                                const SCEV *Ptr);
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  int getArithmeticInstrCost(
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      unsigned Opcode, Type *Ty,
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      TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
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      TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
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      TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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      TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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      ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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  int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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                      unsigned AddressSpace, const Instruction *I = nullptr);
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  int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
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                                 ArrayRef<unsigned> Indices, unsigned Alignment,
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                                 unsigned AddressSpace,
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                                 bool UseMaskForCond = false,
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                                 bool UseMaskForGaps = false);
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  bool isLoweredToCall(const Function *F);
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  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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                                AssumptionCache &AC,
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                                TargetLibraryInfo *LibInfo,
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                                HardwareLoopInfo &HWLoopInfo);
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  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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                               TTI::UnrollingPreferences &UP);
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  bool shouldBuildLookupTablesForConstant(Constant *C) const {
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    // In the ROPI and RWPI relocation models we can't have pointers to global
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    // variables or functions in constant data, so don't convert switches to
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    // lookup tables if any of the values would need relocation.
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    if (ST->isROPI() || 
ST->isRWPI()6.05k
)
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      return !C->needsRelocation();
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    return true;
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  }
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  /// @}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H