Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "MCTargetDesc/ARMAsmBackend.h"
10
#include "MCTargetDesc/ARMAddressingModes.h"
11
#include "MCTargetDesc/ARMAsmBackendDarwin.h"
12
#include "MCTargetDesc/ARMAsmBackendELF.h"
13
#include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
14
#include "MCTargetDesc/ARMFixupKinds.h"
15
#include "MCTargetDesc/ARMMCTargetDesc.h"
16
#include "llvm/ADT/StringSwitch.h"
17
#include "llvm/BinaryFormat/ELF.h"
18
#include "llvm/BinaryFormat/MachO.h"
19
#include "llvm/MC/MCAsmBackend.h"
20
#include "llvm/MC/MCAssembler.h"
21
#include "llvm/MC/MCContext.h"
22
#include "llvm/MC/MCDirectives.h"
23
#include "llvm/MC/MCELFObjectWriter.h"
24
#include "llvm/MC/MCExpr.h"
25
#include "llvm/MC/MCFixupKindInfo.h"
26
#include "llvm/MC/MCObjectWriter.h"
27
#include "llvm/MC/MCRegisterInfo.h"
28
#include "llvm/MC/MCSectionELF.h"
29
#include "llvm/MC/MCSectionMachO.h"
30
#include "llvm/MC/MCSubtargetInfo.h"
31
#include "llvm/MC/MCValue.h"
32
#include "llvm/MC/MCAsmLayout.h"
33
#include "llvm/Support/Debug.h"
34
#include "llvm/Support/EndianStream.h"
35
#include "llvm/Support/ErrorHandling.h"
36
#include "llvm/Support/Format.h"
37
#include "llvm/Support/TargetParser.h"
38
#include "llvm/Support/raw_ostream.h"
39
using namespace llvm;
40
41
namespace {
42
class ARMELFObjectWriter : public MCELFObjectTargetWriter {
43
public:
44
  ARMELFObjectWriter(uint8_t OSABI)
45
      : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
46
0
                                /*HasRelocationAddend*/ false) {}
47
};
48
} // end anonymous namespace
49
50
7
Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
51
7
  if (STI.getTargetTriple().isOSBinFormatELF() && Name == "R_ARM_NONE")
52
7
    return FK_NONE;
53
0
54
0
  return MCAsmBackend::getFixupKind(Name);
55
0
}
56
57
1.10M
const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
58
1.10M
  const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
59
1.10M
      // This table *must* be in the order that the fixup_* kinds are defined in
60
1.10M
      // ARMFixupKinds.h.
61
1.10M
      //
62
1.10M
      // Name                      Offset (bits) Size (bits)     Flags
63
1.10M
      {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
64
1.10M
      {"fixup_t2_ldst_pcrel_12", 0, 32,
65
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
66
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
67
1.10M
      {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
68
1.10M
      {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
69
1.10M
      {"fixup_t2_pcrel_10", 0, 32,
70
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
71
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
72
1.10M
      {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73
1.10M
      {"fixup_t2_pcrel_9", 0, 32,
74
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
75
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
76
1.10M
      {"fixup_thumb_adr_pcrel_10", 0, 8,
77
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
78
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
79
1.10M
      {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
80
1.10M
      {"fixup_t2_adr_pcrel_12", 0, 32,
81
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
82
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
83
1.10M
      {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
84
1.10M
      {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
85
1.10M
      {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86
1.10M
      {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
87
1.10M
      {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
88
1.10M
      {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
89
1.10M
      {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
90
1.10M
      {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
91
1.10M
      {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
92
1.10M
      {"fixup_arm_thumb_blx", 0, 32,
93
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
94
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
95
1.10M
      {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
96
1.10M
      {"fixup_arm_thumb_cp", 0, 8,
97
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
98
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
99
1.10M
      {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
100
1.10M
      // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
101
1.10M
      // - 19.
102
1.10M
      {"fixup_arm_movt_hi16", 0, 20, 0},
103
1.10M
      {"fixup_arm_movw_lo16", 0, 20, 0},
104
1.10M
      {"fixup_t2_movt_hi16", 0, 20, 0},
105
1.10M
      {"fixup_t2_movw_lo16", 0, 20, 0},
106
1.10M
      {"fixup_arm_mod_imm", 0, 12, 0},
107
1.10M
      {"fixup_t2_so_imm", 0, 26, 0},
108
1.10M
      {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
109
1.10M
      {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
110
1.10M
      {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
111
1.10M
      {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112
1.10M
      {"fixup_bfcsel_else_target", 0, 32, 0},
113
1.10M
      {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
114
1.10M
      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
115
1.10M
  };
116
1.10M
  const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
117
1.10M
      // This table *must* be in the order that the fixup_* kinds are defined in
118
1.10M
      // ARMFixupKinds.h.
119
1.10M
      //
120
1.10M
      // Name                      Offset (bits) Size (bits)     Flags
121
1.10M
      {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122
1.10M
      {"fixup_t2_ldst_pcrel_12", 0, 32,
123
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
124
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
125
1.10M
      {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
126
1.10M
      {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
127
1.10M
      {"fixup_t2_pcrel_10", 0, 32,
128
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
129
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
130
1.10M
      {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
131
1.10M
      {"fixup_t2_pcrel_9", 0, 32,
132
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
133
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
134
1.10M
      {"fixup_thumb_adr_pcrel_10", 8, 8,
135
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
136
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
137
1.10M
      {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
138
1.10M
      {"fixup_t2_adr_pcrel_12", 0, 32,
139
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
140
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
141
1.10M
      {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
142
1.10M
      {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
143
1.10M
      {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
144
1.10M
      {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
145
1.10M
      {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
146
1.10M
      {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
147
1.10M
      {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
148
1.10M
      {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
149
1.10M
      {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
150
1.10M
      {"fixup_arm_thumb_blx", 0, 32,
151
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
152
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
153
1.10M
      {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
154
1.10M
      {"fixup_arm_thumb_cp", 8, 8,
155
1.10M
       MCFixupKindInfo::FKF_IsPCRel |
156
1.10M
           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
157
1.10M
      {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
158
1.10M
      // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
159
1.10M
      // - 19.
160
1.10M
      {"fixup_arm_movt_hi16", 12, 20, 0},
161
1.10M
      {"fixup_arm_movw_lo16", 12, 20, 0},
162
1.10M
      {"fixup_t2_movt_hi16", 12, 20, 0},
163
1.10M
      {"fixup_t2_movw_lo16", 12, 20, 0},
164
1.10M
      {"fixup_arm_mod_imm", 20, 12, 0},
165
1.10M
      {"fixup_t2_so_imm", 26, 6, 0},
166
1.10M
      {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
167
1.10M
      {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
168
1.10M
      {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
169
1.10M
      {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
170
1.10M
      {"fixup_bfcsel_else_target", 0, 32, 0},
171
1.10M
      {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
172
1.10M
      {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
173
1.10M
  };
174
1.10M
175
1.10M
  if (Kind < FirstTargetFixupKind)
176
450k
    return MCAsmBackend::getFixupKindInfo(Kind);
177
652k
178
652k
  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
179
652k
         "Invalid kind!");
180
652k
  return (Endian == support::little ? 
InfosLE652k
181
652k
                                    : 
InfosBE214
)[Kind - FirstTargetFixupKind];
182
652k
}
183
184
17.1k
void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
185
17.1k
  switch (Flag) {
186
17.1k
  default:
187
5.18k
    break;
188
17.1k
  case MCAF_Code16:
189
11.6k
    setIsThumb(true);
190
11.6k
    break;
191
17.1k
  case MCAF_Code32:
192
303
    setIsThumb(false);
193
303
    break;
194
17.1k
  }
195
17.1k
}
196
197
unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op,
198
701k
                                         const MCSubtargetInfo &STI) const {
199
701k
  bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
200
701k
  bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
201
701k
202
701k
  switch (Op) {
203
701k
  default:
204
561k
    return Op;
205
701k
  case ARM::tBcc:
206
80.3k
    return HasThumb2 ? 
(unsigned)ARM::t2Bcc79.3k
:
Op1.07k
;
207
701k
  case ARM::tLDRpci:
208
3.42k
    return HasThumb2 ? 
(unsigned)ARM::t2LDRpci2.84k
:
Op585
;
209
701k
  case ARM::tADR:
210
135
    return HasThumb2 ? 
(unsigned)ARM::t2ADR128
:
Op7
;
211
701k
  case ARM::tB:
212
23.8k
    return HasV8MBaselineOps ? 
(unsigned)ARM::t2B23.4k
:
Op439
;
213
701k
  case ARM::tCBZ:
214
25.1k
    return ARM::tHINT;
215
701k
  case ARM::tCBNZ:
216
7.52k
    return ARM::tHINT;
217
701k
  }
218
701k
}
219
220
bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst,
221
701k
                                      const MCSubtargetInfo &STI) const {
222
701k
  if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
223
138k
    return true;
224
563k
  return false;
225
563k
}
226
227
0
static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
228
0
  int64_t Offset = int64_t(Value) - 4;
229
0
  if (Offset < Min || Offset > Max)
230
0
    return "out of range pc-relative fixup value";
231
0
  return nullptr;
232
0
}
233
234
const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
235
90.9k
                                                    uint64_t Value) const {
236
90.9k
  switch ((unsigned)Fixup.getKind()) {
237
90.9k
  case ARM::fixup_arm_thumb_br: {
238
15.2k
    // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
239
15.2k
    // low bit being an implied zero. There's an implied +4 offset for the
240
15.2k
    // branch, so we adjust the other way here to determine what's
241
15.2k
    // encodable.
242
15.2k
    //
243
15.2k
    // Relax if the value is too big for a (signed) i8.
244
15.2k
    int64_t Offset = int64_t(Value) - 4;
245
15.2k
    if (Offset > 2046 || 
Offset < -204815.2k
)
246
4
      return "out of range pc-relative fixup value";
247
15.2k
    break;
248
15.2k
  }
249
52.1k
  case ARM::fixup_arm_thumb_bcc: {
250
52.1k
    // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
251
52.1k
    // low bit being an implied zero. There's an implied +4 offset for the
252
52.1k
    // branch, so we adjust the other way here to determine what's
253
52.1k
    // encodable.
254
52.1k
    //
255
52.1k
    // Relax if the value is too big for a (signed) i8.
256
52.1k
    int64_t Offset = int64_t(Value) - 4;
257
52.1k
    if (Offset > 254 || 
Offset < -25652.1k
)
258
23
      return "out of range pc-relative fixup value";
259
52.1k
    break;
260
52.1k
  }
261
52.1k
  case ARM::fixup_thumb_adr_pcrel_10:
262
2.09k
  case ARM::fixup_arm_thumb_cp: {
263
2.09k
    // If the immediate is negative, greater than 1020, or not a multiple
264
2.09k
    // of four, the wide version of the instruction must be used.
265
2.09k
    int64_t Offset = int64_t(Value) - 4;
266
2.09k
    if (Offset & 3)
267
10
      return "misaligned pc-relative fixup value";
268
2.08k
    else if (Offset > 1020 || 
Offset < 02.07k
)
269
6
      return "out of range pc-relative fixup value";
270
2.07k
    break;
271
2.07k
  }
272
21.4k
  case ARM::fixup_arm_thumb_cb: {
273
21.4k
    // If we have a Thumb CBZ or CBNZ instruction and its target is the next
274
21.4k
    // instruction it is actually out of range for the instruction.
275
21.4k
    // It will be changed to a NOP.
276
21.4k
    int64_t Offset = (Value & ~1);
277
21.4k
    if (Offset == 2)
278
2
      return "will be converted to nop";
279
21.4k
    break;
280
21.4k
  }
281
21.4k
  case ARM::fixup_bf_branch:
282
0
    return checkPCRelOffset(Value, 0, 30);
283
21.4k
  case ARM::fixup_bf_target:
284
0
    return checkPCRelOffset(Value, -0x10000, +0xfffe);
285
21.4k
  case ARM::fixup_bfl_target:
286
0
    return checkPCRelOffset(Value, -0x40000, +0x3fffe);
287
21.4k
  case ARM::fixup_bfc_target:
288
0
    return checkPCRelOffset(Value, -0x1000, +0xffe);
289
21.4k
  case ARM::fixup_wls:
290
0
    return checkPCRelOffset(Value, 0, +0xffe);
291
21.4k
  case ARM::fixup_le:
292
0
    // The offset field in the LE and LETP instructions is an 11-bit
293
0
    // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
294
0
    // interpreted as a negative offset from the value read from pc,
295
0
    // i.e. from instruction_address+4.
296
0
    //
297
0
    // So an LE instruction can in principle address the instruction
298
0
    // immediately after itself, or (not very usefully) the address
299
0
    // half way through the 4-byte LE.
300
0
    return checkPCRelOffset(Value, -0xffe, 0);
301
21.4k
  case ARM::fixup_bfcsel_else_target: {
302
0
    if (Value != 2 && Value != 4)
303
0
      return "out of range label-relative fixup value";
304
0
    break;
305
0
  }
306
0
307
0
  default:
308
0
    llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
309
90.8k
  }
310
90.8k
  return nullptr;
311
90.8k
}
312
313
bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
314
                                         const MCRelaxableFragment *DF,
315
88.8k
                                         const MCAsmLayout &Layout) const {
316
88.8k
  return reasonForFixupRelaxation(Fixup, Value);
317
88.8k
}
318
319
void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
320
                                     const MCSubtargetInfo &STI,
321
126
                                     MCInst &Res) const {
322
126
  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
323
126
324
126
  // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
325
126
  if (RelaxedOp == Inst.getOpcode()) {
326
0
    SmallString<256> Tmp;
327
0
    raw_svector_ostream OS(Tmp);
328
0
    Inst.dump_pretty(OS);
329
0
    OS << "\n";
330
0
    report_fatal_error("unexpected instruction to relax: " + OS.str());
331
0
  }
332
126
333
126
  // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
334
126
  // have to change the operands too.
335
126
  if ((Inst.getOpcode() == ARM::tCBZ || 
Inst.getOpcode() == ARM::tCBNZ125
) &&
336
126
      
RelaxedOp == ARM::tHINT2
) {
337
2
    Res.setOpcode(RelaxedOp);
338
2
    Res.addOperand(MCOperand::createImm(0));
339
2
    Res.addOperand(MCOperand::createImm(14));
340
2
    Res.addOperand(MCOperand::createReg(0));
341
2
    return;
342
2
  }
343
124
344
124
  // The rest of instructions we're relaxing have the same operands.
345
124
  // We just need to update to the proper opcode.
346
124
  Res = Inst;
347
124
  Res.setOpcode(RelaxedOp);
348
124
}
349
350
13.7k
bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
351
13.7k
  const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
352
13.7k
  const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
353
13.7k
  const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
354
13.7k
  const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
355
13.7k
  if (isThumb()) {
356
12.5k
    const uint16_t nopEncoding =
357
12.5k
        hasNOP() ? 
Thumb2_16bitNopEncoding11.7k
:
Thumb1_16bitNopEncoding789
;
358
12.5k
    uint64_t NumNops = Count / 2;
359
13.2k
    for (uint64_t i = 0; i != NumNops; 
++i779
)
360
779
      support::endian::write(OS, nopEncoding, Endian);
361
12.5k
    if (Count & 1)
362
120
      OS << '\0';
363
12.5k
    return true;
364
12.5k
  }
365
1.21k
  // ARM mode
366
1.21k
  const uint32_t nopEncoding =
367
1.21k
      hasNOP() ? 
ARMv6T2_NopEncoding1.06k
:
ARMv4_NopEncoding146
;
368
1.21k
  uint64_t NumNops = Count / 4;
369
1.22k
  for (uint64_t i = 0; i != NumNops; 
++i19
)
370
19
    support::endian::write(OS, nopEncoding, Endian);
371
1.21k
  // FIXME: should this function return false when unable to write exactly
372
1.21k
  // 'Count' bytes with NOP encodings?
373
1.21k
  switch (Count % 4) {
374
1.21k
  default:
375
1.20k
    break; // No leftover bytes to write
376
1.21k
  case 1:
377
1
    OS << '\0';
378
1
    break;
379
1.21k
  case 2:
380
5
    OS.write("\0\0", 2);
381
5
    break;
382
1.21k
  case 3:
383
0
    OS.write("\0\0\xa0", 3);
384
0
    break;
385
1.21k
  }
386
1.21k
387
1.21k
  return true;
388
1.21k
}
389
390
60.3k
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
391
60.3k
  if (IsLittleEndian) {
392
60.3k
    // Note that the halfwords are stored high first and low second in thumb;
393
60.3k
    // so we need to swap the fixup value here to map properly.
394
60.3k
    uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
395
60.3k
    Swapped |= (Value & 0x0000FFFF) << 16;
396
60.3k
    return Swapped;
397
60.3k
  } else
398
13
    return Value;
399
60.3k
}
400
401
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
402
46.2k
                              bool IsLittleEndian) {
403
46.2k
  uint32_t Value;
404
46.2k
405
46.2k
  if (IsLittleEndian) {
406
46.2k
    Value = (SecondHalf & 0xFFFF) << 16;
407
46.2k
    Value |= (FirstHalf & 0xFFFF);
408
46.2k
  } else {
409
3
    Value = (SecondHalf & 0xFFFF);
410
3
    Value |= (FirstHalf & 0xFFFF) << 16;
411
3
  }
412
46.2k
413
46.2k
  return Value;
414
46.2k
}
415
416
unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
417
                                         const MCFixup &Fixup,
418
                                         const MCValue &Target, uint64_t Value,
419
                                         bool IsResolved, MCContext &Ctx,
420
344k
                                         const MCSubtargetInfo* STI) const {
421
344k
  unsigned Kind = Fixup.getKind();
422
344k
423
344k
  // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
424
344k
  // and .word relocations they put the Thumb bit into the addend if possible.
425
344k
  // Other relocation types don't want this bit though (branches couldn't encode
426
344k
  // it if it *was* present, and no other relocations exist) and it can
427
344k
  // interfere with checking valid expressions.
428
344k
  if (const MCSymbolRefExpr *A = Target.getSymA()) {
429
238k
    if (A->hasSubsectionsViaSymbols() && 
Asm.isThumbFunc(&A->getSymbol())235k
&&
430
238k
        
A->getSymbol().isExternal()6.69k
&&
431
238k
        
(4.65k
Kind == FK_Data_44.65k
||
Kind == ARM::fixup_arm_movw_lo163.30k
||
432
4.65k
         
Kind == ARM::fixup_arm_movt_hi163.30k
||
Kind == ARM::fixup_t2_movw_lo163.30k
||
433
4.65k
         
Kind == ARM::fixup_t2_movt_hi163.24k
))
434
1.47k
      Value |= 1;
435
238k
  }
436
344k
437
344k
  switch (Kind) {
438
344k
  default:
439
0
    Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
440
0
    return 0;
441
344k
  case FK_NONE:
442
185k
  case FK_Data_1:
443
185k
  case FK_Data_2:
444
185k
  case FK_Data_4:
445
185k
    return Value;
446
185k
  case FK_SecRel_2:
447
3
    return Value;
448
185k
  case FK_SecRel_4:
449
11
    return Value;
450
185k
  case ARM::fixup_arm_movt_hi16:
451
36
    assert(STI != nullptr);
452
36
    if (IsResolved || 
!STI->getTargetTriple().isOSBinFormatELF()35
)
453
9
      Value >>= 16;
454
36
    LLVM_FALLTHROUGH;
455
75
  case ARM::fixup_arm_movw_lo16: {
456
75
    unsigned Hi4 = (Value & 0xF000) >> 12;
457
75
    unsigned Lo12 = Value & 0x0FFF;
458
75
    // inst{19-16} = Hi4;
459
75
    // inst{11-0} = Lo12;
460
75
    Value = (Hi4 << 16) | (Lo12);
461
75
    return Value;
462
36
  }
463
26.6k
  case ARM::fixup_t2_movt_hi16:
464
26.6k
    assert(STI != nullptr);
465
26.6k
    if (IsResolved || 
!STI->getTargetTriple().isOSBinFormatELF()26.6k
)
466
26.6k
      Value >>= 16;
467
26.6k
    LLVM_FALLTHROUGH;
468
53.2k
  case ARM::fixup_t2_movw_lo16: {
469
53.2k
    unsigned Hi4 = (Value & 0xF000) >> 12;
470
53.2k
    unsigned i = (Value & 0x800) >> 11;
471
53.2k
    unsigned Mid3 = (Value & 0x700) >> 8;
472
53.2k
    unsigned Lo8 = Value & 0x0FF;
473
53.2k
    // inst{19-16} = Hi4;
474
53.2k
    // inst{26} = i;
475
53.2k
    // inst{14-12} = Mid3;
476
53.2k
    // inst{7-0} = Lo8;
477
53.2k
    Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
478
53.2k
    return swapHalfWords(Value, Endian == support::little);
479
26.6k
  }
480
26.6k
  case ARM::fixup_arm_ldst_pcrel_12:
481
34
    // ARM PC-relative values are offset by 8.
482
34
    Value -= 4;
483
34
    LLVM_FALLTHROUGH;
484
47
  case ARM::fixup_t2_ldst_pcrel_12: {
485
47
    // Offset by 4, adjusted by two due to the half-word ordering of thumb.
486
47
    Value -= 4;
487
47
    bool isAdd = true;
488
47
    if ((int64_t)Value < 0) {
489
9
      Value = -Value;
490
9
      isAdd = false;
491
9
    }
492
47
    if (Value >= 4096) {
493
2
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
494
2
      return 0;
495
2
    }
496
45
    Value |= isAdd << 23;
497
45
498
45
    // Same addressing mode as fixup_arm_pcrel_10,
499
45
    // but with 16-bit halfwords swapped.
500
45
    if (Kind == ARM::fixup_t2_ldst_pcrel_12)
501
13
      return swapHalfWords(Value, Endian == support::little);
502
32
503
32
    return Value;
504
32
  }
505
32
  case ARM::fixup_arm_adr_pcrel_12: {
506
7
    // ARM PC-relative values are offset by 8.
507
7
    Value -= 8;
508
7
    unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
509
7
    if ((int64_t)Value < 0) {
510
1
      Value = -Value;
511
1
      opc = 2; // 0b0010
512
1
    }
513
7
    if (ARM_AM::getSOImmVal(Value) == -1) {
514
0
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
515
0
      return 0;
516
0
    }
517
7
    // Encode the immediate and shift the opcode into place.
518
7
    return ARM_AM::getSOImmVal(Value) | (opc << 21);
519
7
  }
520
7
521
20
  case ARM::fixup_t2_adr_pcrel_12: {
522
20
    Value -= 4;
523
20
    unsigned opc = 0;
524
20
    if ((int64_t)Value < 0) {
525
1
      Value = -Value;
526
1
      opc = 5;
527
1
    }
528
20
529
20
    uint32_t out = (opc << 21);
530
20
    out |= (Value & 0x800) << 15;
531
20
    out |= (Value & 0x700) << 4;
532
20
    out |= (Value & 0x0FF);
533
20
534
20
    return swapHalfWords(out, Endian == support::little);
535
7
  }
536
7
537
1.04k
  case ARM::fixup_arm_condbranch:
538
1.04k
  case ARM::fixup_arm_uncondbranch:
539
1.04k
  case ARM::fixup_arm_uncondbl:
540
1.04k
  case ARM::fixup_arm_condbl:
541
1.04k
  case ARM::fixup_arm_blx:
542
1.04k
    // These values don't encode the low two bits since they're always zero.
543
1.04k
    // Offset by 8 just as above.
544
1.04k
    if (const MCSymbolRefExpr *SRE =
545
1.03k
            dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
546
1.03k
      if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
547
0
        return 0;
548
1.04k
    return 0xffffff & ((Value - 8) >> 2);
549
2.39k
  case ARM::fixup_t2_uncondbranch: {
550
2.39k
    Value = Value - 4;
551
2.39k
    if (!isInt<25>(Value)) {
552
2
      Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
553
2
      return 0;
554
2
    }
555
2.38k
556
2.38k
    Value >>= 1; // Low bit is not encoded.
557
2.38k
558
2.38k
    uint32_t out = 0;
559
2.38k
    bool I = Value & 0x800000;
560
2.38k
    bool J1 = Value & 0x400000;
561
2.38k
    bool J2 = Value & 0x200000;
562
2.38k
    J1 ^= I;
563
2.38k
    J2 ^= I;
564
2.38k
565
2.38k
    out |= I << 26;                 // S bit
566
2.38k
    out |= !J1 << 13;               // J1 bit
567
2.38k
    out |= !J2 << 11;               // J2 bit
568
2.38k
    out |= (Value & 0x1FF800) << 5; // imm6 field
569
2.38k
    out |= (Value & 0x0007FF);      // imm11 field
570
2.38k
571
2.38k
    return swapHalfWords(out, Endian == support::little);
572
2.38k
  }
573
4.30k
  case ARM::fixup_t2_condbranch: {
574
4.30k
    Value = Value - 4;
575
4.30k
    if (!isInt<21>(Value)) {
576
2
      Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
577
2
      return 0;
578
2
    }
579
4.30k
580
4.30k
    Value >>= 1; // Low bit is not encoded.
581
4.30k
582
4.30k
    uint64_t out = 0;
583
4.30k
    out |= (Value & 0x80000) << 7; // S bit
584
4.30k
    out |= (Value & 0x40000) >> 7; // J2 bit
585
4.30k
    out |= (Value & 0x20000) >> 4; // J1 bit
586
4.30k
    out |= (Value & 0x1F800) << 5; // imm6 field
587
4.30k
    out |= (Value & 0x007FF);      // imm11 field
588
4.30k
589
4.30k
    return swapHalfWords(out, Endian == support::little);
590
4.30k
  }
591
46.2k
  case ARM::fixup_arm_thumb_bl: {
592
46.2k
    if (!isInt<25>(Value - 4) ||
593
46.2k
        
(46.2k
!STI->getFeatureBits()[ARM::FeatureThumb2]46.2k
&&
594
46.2k
         
!STI->getFeatureBits()[ARM::HasV8MBaselineOps]913
&&
595
46.2k
         
!STI->getFeatureBits()[ARM::HasV6MOps]851
&&
596
46.2k
         
!isInt<23>(Value - 4)117
)) {
597
14
      Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
598
14
      return 0;
599
14
    }
600
46.1k
601
46.1k
    // The value doesn't encode the low bit (always zero) and is offset by
602
46.1k
    // four. The 32-bit immediate value is encoded as
603
46.1k
    //   imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
604
46.1k
    // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
605
46.1k
    // The value is encoded into disjoint bit positions in the destination
606
46.1k
    // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
607
46.1k
    // J = either J1 or J2 bit
608
46.1k
    //
609
46.1k
    //   BL:  xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
610
46.1k
    //
611
46.1k
    // Note that the halfwords are stored high first, low second; so we need
612
46.1k
    // to transpose the fixup value here to map properly.
613
46.1k
    uint32_t offset = (Value - 4) >> 1;
614
46.1k
    uint32_t signBit = (offset & 0x800000) >> 23;
615
46.1k
    uint32_t I1Bit = (offset & 0x400000) >> 22;
616
46.1k
    uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
617
46.1k
    uint32_t I2Bit = (offset & 0x200000) >> 21;
618
46.1k
    uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
619
46.1k
    uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
620
46.1k
    uint32_t imm11Bits = (offset & 0x000007FF);
621
46.1k
622
46.1k
    uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
623
46.1k
    uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
624
46.1k
                           (uint16_t)imm11Bits);
625
46.1k
    return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
626
46.1k
  }
627
46.1k
  case ARM::fixup_arm_thumb_blx: {
628
21
    // The value doesn't encode the low two bits (always zero) and is offset by
629
21
    // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
630
21
    //   imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
631
21
    // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
632
21
    // The value is encoded into disjoint bit positions in the destination
633
21
    // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
634
21
    // J = either J1 or J2 bit, 0 = zero.
635
21
    //
636
21
    //   BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
637
21
    //
638
21
    // Note that the halfwords are stored high first, low second; so we need
639
21
    // to transpose the fixup value here to map properly.
640
21
    if (Value % 4 != 0) {
641
2
      Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
642
2
      return 0;
643
2
    }
644
19
645
19
    uint32_t offset = (Value - 4) >> 2;
646
19
    if (const MCSymbolRefExpr *SRE =
647
17
            dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
648
17
      if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
649
0
        offset = 0;
650
19
    uint32_t signBit = (offset & 0x400000) >> 22;
651
19
    uint32_t I1Bit = (offset & 0x200000) >> 21;
652
19
    uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
653
19
    uint32_t I2Bit = (offset & 0x100000) >> 20;
654
19
    uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
655
19
    uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
656
19
    uint32_t imm10LBits = (offset & 0x3FF);
657
19
658
19
    uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
659
19
    uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
660
19
                           ((uint16_t)imm10LBits) << 1);
661
19
    return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
662
19
  }
663
2.03k
  case ARM::fixup_thumb_adr_pcrel_10:
664
2.03k
  case ARM::fixup_arm_thumb_cp:
665
2.03k
    // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
666
2.03k
    // could have an error on our hands.
667
2.03k
    assert(STI != nullptr);
668
2.03k
    if (!STI->getFeatureBits()[ARM::FeatureThumb2] && 
IsResolved592
) {
669
590
      const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
670
590
      if (FixupDiagnostic) {
671
9
        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
672
9
        return 0;
673
9
      }
674
2.02k
    }
675
2.02k
    // Offset by 4, and don't encode the low two bits.
676
2.02k
    return ((Value - 4) >> 2) & 0xff;
677
11.1k
  case ARM::fixup_arm_thumb_cb: {
678
11.1k
    // CB instructions can only branch to offsets in [4, 126] in multiples of 2
679
11.1k
    // so ensure that the raw value LSB is zero and it lies in [2, 130].
680
11.1k
    // An offset of 2 will be relaxed to a NOP.
681
11.1k
    if ((int64_t)Value < 2 || 
Value > 0x8211.1k
||
Value & 111.1k
) {
682
12
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
683
12
      return 0;
684
12
    }
685
11.1k
    // Offset by 4 and don't encode the lower bit, which is always 0.
686
11.1k
    // FIXME: diagnose if no Thumb2
687
11.1k
    uint32_t Binary = (Value - 4) >> 1;
688
11.1k
    return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
689
11.1k
  }
690
11.1k
  case ARM::fixup_arm_thumb_br:
691
8.94k
    // Offset by 4 and don't encode the lower bit, which is always 0.
692
8.94k
    assert(STI != nullptr);
693
8.94k
    if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
694
8.94k
        
!STI->getFeatureBits()[ARM::HasV8MBaselineOps]440
) {
695
439
      const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
696
439
      if (FixupDiagnostic) {
697
3
        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
698
3
        return 0;
699
3
      }
700
8.93k
    }
701
8.93k
    return ((Value - 4) >> 1) & 0x7ff;
702
29.1k
  case ARM::fixup_arm_thumb_bcc:
703
29.1k
    // Offset by 4 and don't encode the lower bit, which is always 0.
704
29.1k
    assert(STI != nullptr);
705
29.1k
    if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
706
1.07k
      const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
707
1.07k
      if (FixupDiagnostic) {
708
2
        Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
709
2
        return 0;
710
2
      }
711
29.1k
    }
712
29.1k
    return ((Value - 4) >> 1) & 0xff;
713
29.1k
  case ARM::fixup_arm_pcrel_10_unscaled: {
714
1
    Value = Value - 8; // ARM fixups offset by an additional word and don't
715
1
                       // need to adjust for the half-word ordering.
716
1
    bool isAdd = true;
717
1
    if ((int64_t)Value < 0) {
718
0
      Value = -Value;
719
0
      isAdd = false;
720
0
    }
721
1
    // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
722
1
    if (Value >= 256) {
723
0
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
724
0
      return 0;
725
0
    }
726
1
    Value = (Value & 0xf) | ((Value & 0xf0) << 4);
727
1
    return Value | (isAdd << 23);
728
1
  }
729
73
  case ARM::fixup_arm_pcrel_10:
730
73
    Value = Value - 4; // ARM fixups offset by an additional word and don't
731
73
                       // need to adjust for the half-word ordering.
732
73
    LLVM_FALLTHROUGH;
733
497
  case ARM::fixup_t2_pcrel_10: {
734
497
    // Offset by 4, adjusted by two due to the half-word ordering of thumb.
735
497
    Value = Value - 4;
736
497
    bool isAdd = true;
737
497
    if ((int64_t)Value < 0) {
738
87
      Value = -Value;
739
87
      isAdd = false;
740
87
    }
741
497
    // These values don't encode the low two bits since they're always zero.
742
497
    Value >>= 2;
743
497
    if (Value >= 256) {
744
0
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
745
0
      return 0;
746
0
    }
747
497
    Value |= isAdd << 23;
748
497
749
497
    // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
750
497
    // swapped.
751
497
    if (Kind == ARM::fixup_t2_pcrel_10)
752
424
      return swapHalfWords(Value, Endian == support::little);
753
73
754
73
    return Value;
755
73
  }
756
73
  case ARM::fixup_arm_pcrel_9:
757
2
    Value = Value - 4; // ARM fixups offset by an additional word and don't
758
2
                       // need to adjust for the half-word ordering.
759
2
    LLVM_FALLTHROUGH;
760
2
  case ARM::fixup_t2_pcrel_9: {
761
2
    // Offset by 4, adjusted by two due to the half-word ordering of thumb.
762
2
    Value = Value - 4;
763
2
    bool isAdd = true;
764
2
    if ((int64_t)Value < 0) {
765
0
      Value = -Value;
766
0
      isAdd = false;
767
0
    }
768
2
    // These values don't encode the low bit since it's always zero.
769
2
    if (Value & 1) {
770
0
      Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
771
0
      return 0;
772
0
    }
773
2
    Value >>= 1;
774
2
    if (Value >= 256) {
775
0
      Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
776
0
      return 0;
777
0
    }
778
2
    Value |= isAdd << 23;
779
2
780
2
    // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
781
2
    // swapped.
782
2
    if (Kind == ARM::fixup_t2_pcrel_9)
783
0
      return swapHalfWords(Value, Endian == support::little);
784
2
785
2
    return Value;
786
2
  }
787
7
  case ARM::fixup_arm_mod_imm:
788
7
    Value = ARM_AM::getSOImmVal(Value);
789
7
    if (Value >> 12) {
790
1
      Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
791
1
      return 0;
792
1
    }
793
6
    return Value;
794
13
  case ARM::fixup_t2_so_imm: {
795
13
    Value = ARM_AM::getT2SOImmVal(Value);
796
13
    if ((int64_t)Value < 0) {
797
1
      Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
798
1
      return 0;
799
1
    }
800
12
    // Value will contain a 12-bit value broken up into a 4-bit shift in bits
801
12
    // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
802
12
    // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
803
12
    // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
804
12
    // half-word.
805
12
    uint64_t EncValue = 0;
806
12
    EncValue |= (Value & 0x800) << 15;
807
12
    EncValue |= (Value & 0x700) << 4;
808
12
    EncValue |= (Value & 0xff);
809
12
    return swapHalfWords(EncValue, Endian == support::little);
810
12
  }
811
12
  case ARM::fixup_bf_branch: {
812
0
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
813
0
    if (FixupDiagnostic) {
814
0
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
815
0
      return 0;
816
0
    }
817
0
    uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
818
0
    return swapHalfWords(out, Endian == support::little);
819
0
  }
820
0
  case ARM::fixup_bf_target:
821
0
  case ARM::fixup_bfl_target:
822
0
  case ARM::fixup_bfc_target: {
823
0
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
824
0
    if (FixupDiagnostic) {
825
0
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
826
0
      return 0;
827
0
    }
828
0
    uint32_t out = 0;
829
0
    uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
830
0
                            Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
831
0
    out |= (((Value - 4) >> 1) & 0x1) << 11;
832
0
    out |= (((Value - 4) >> 1) & 0x7fe);
833
0
    out |= (((Value - 4) >> 1) & HighBitMask) << 5;
834
0
    return swapHalfWords(out, Endian == support::little);
835
0
  }
836
0
  case ARM::fixup_bfcsel_else_target: {
837
0
    // If this is a fixup of a branch future's else target then it should be a
838
0
    // constant MCExpr representing the distance between the branch targetted
839
0
    // and the instruction after that same branch.
840
0
    Value = Target.getConstant();
841
0
842
0
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
843
0
    if (FixupDiagnostic) {
844
0
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
845
0
      return 0;
846
0
    }
847
0
    uint32_t out = ((Value >> 2) & 1) << 17;
848
0
    return swapHalfWords(out, Endian == support::little);
849
0
  }
850
0
  case ARM::fixup_wls:
851
0
  case ARM::fixup_le: {
852
0
    const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
853
0
    if (FixupDiagnostic) {
854
0
      Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
855
0
      return 0;
856
0
    }
857
0
    uint64_t real_value = Value - 4;
858
0
    uint32_t out = 0;
859
0
    if (Kind == ARM::fixup_le)
860
0
      real_value = -real_value;
861
0
    out |= ((real_value >> 1) & 0x1) << 11;
862
0
    out |= ((real_value >> 1) & 0x7fe);
863
0
    return swapHalfWords(out, Endian == support::little);
864
0
  }
865
344k
  }
866
344k
}
867
868
bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
869
                                          const MCFixup &Fixup,
870
251k
                                          const MCValue &Target) {
871
251k
  const MCSymbolRefExpr *A = Target.getSymA();
872
251k
  const MCSymbol *Sym = A ? 
&A->getSymbol()145k
:
nullptr105k
;
873
251k
  const unsigned FixupKind = Fixup.getKind() ;
874
251k
  if (FixupKind == FK_NONE)
875
2
    return true;
876
251k
  if (FixupKind == ARM::fixup_arm_thumb_bl) {
877
103
    assert(Sym && "How did we resolve this?");
878
103
879
103
    // If the symbol is external the linker will handle it.
880
103
    // FIXME: Should we handle it as an optimization?
881
103
882
103
    // If the symbol is out of range, produce a relocation and hope the
883
103
    // linker can handle it. GNU AS produces an error in this case.
884
103
    if (Sym->isExternal())
885
49
      return true;
886
251k
  }
887
251k
  // Create relocations for unconditional branches to function symbols with
888
251k
  // different execution mode in ELF binaries.
889
251k
  if (Sym && 
Sym->isELF()145k
) {
890
533
    unsigned Type = cast<MCSymbolELF>(Sym)->getType();
891
533
    if ((Type == ELF::STT_FUNC || 
Type == ELF::STT_GNU_IFUNC503
)) {
892
30
      if (Asm.isThumbFunc(Sym) && 
(FixupKind == ARM::fixup_arm_uncondbranch)11
)
893
1
        return true;
894
29
      if (!Asm.isThumbFunc(Sym) && 
(19
FixupKind == ARM::fixup_arm_thumb_br19
||
895
19
                                    
FixupKind == ARM::fixup_arm_thumb_bl18
||
896
19
                                    
FixupKind == ARM::fixup_t2_condbranch16
||
897
19
                                    
FixupKind == ARM::fixup_t2_uncondbranch12
))
898
10
        return true;
899
251k
    }
900
533
  }
901
251k
  // We must always generate a relocation for BL/BLX instructions if we have
902
251k
  // a symbol to reference, as the linker relies on knowing the destination
903
251k
  // symbol's thumb-ness to get interworking right.
904
251k
  if (A && 
(145k
FixupKind == ARM::fixup_arm_thumb_blx145k
||
905
145k
            
FixupKind == ARM::fixup_arm_blx145k
||
906
145k
            
FixupKind == ARM::fixup_arm_uncondbl145k
||
907
145k
            
FixupKind == ARM::fixup_arm_condbl145k
))
908
25
    return true;
909
251k
  return false;
910
251k
}
911
912
/// getFixupKindNumBytes - The number of bytes the fixup may change.
913
344k
static unsigned getFixupKindNumBytes(unsigned Kind) {
914
344k
  switch (Kind) {
915
344k
  default:
916
0
    llvm_unreachable("Unknown fixup kind!");
917
344k
918
344k
  case FK_NONE:
919
7
    return 0;
920
344k
921
344k
  case FK_Data_1:
922
33.8k
  case ARM::fixup_arm_thumb_bcc:
923
33.8k
  case ARM::fixup_arm_thumb_cp:
924
33.8k
  case ARM::fixup_thumb_adr_pcrel_10:
925
33.8k
    return 1;
926
33.8k
927
33.8k
  case FK_Data_2:
928
21.9k
  case ARM::fixup_arm_thumb_br:
929
21.9k
  case ARM::fixup_arm_thumb_cb:
930
21.9k
  case ARM::fixup_arm_mod_imm:
931
21.9k
    return 2;
932
21.9k
933
21.9k
  case ARM::fixup_arm_pcrel_10_unscaled:
934
1.16k
  case ARM::fixup_arm_ldst_pcrel_12:
935
1.16k
  case ARM::fixup_arm_pcrel_10:
936
1.16k
  case ARM::fixup_arm_pcrel_9:
937
1.16k
  case ARM::fixup_arm_adr_pcrel_12:
938
1.16k
  case ARM::fixup_arm_uncondbl:
939
1.16k
  case ARM::fixup_arm_condbl:
940
1.16k
  case ARM::fixup_arm_blx:
941
1.16k
  case ARM::fixup_arm_condbranch:
942
1.16k
  case ARM::fixup_arm_uncondbranch:
943
1.16k
    return 3;
944
1.16k
945
287k
  case FK_Data_4:
946
287k
  case ARM::fixup_t2_ldst_pcrel_12:
947
287k
  case ARM::fixup_t2_condbranch:
948
287k
  case ARM::fixup_t2_uncondbranch:
949
287k
  case ARM::fixup_t2_pcrel_10:
950
287k
  case ARM::fixup_t2_pcrel_9:
951
287k
  case ARM::fixup_t2_adr_pcrel_12:
952
287k
  case ARM::fixup_arm_thumb_bl:
953
287k
  case ARM::fixup_arm_thumb_blx:
954
287k
  case ARM::fixup_arm_movt_hi16:
955
287k
  case ARM::fixup_arm_movw_lo16:
956
287k
  case ARM::fixup_t2_movt_hi16:
957
287k
  case ARM::fixup_t2_movw_lo16:
958
287k
  case ARM::fixup_t2_so_imm:
959
287k
  case ARM::fixup_bf_branch:
960
287k
  case ARM::fixup_bf_target:
961
287k
  case ARM::fixup_bfl_target:
962
287k
  case ARM::fixup_bfc_target:
963
287k
  case ARM::fixup_bfcsel_else_target:
964
287k
  case ARM::fixup_wls:
965
287k
  case ARM::fixup_le:
966
287k
    return 4;
967
287k
968
287k
  case FK_SecRel_2:
969
3
    return 2;
970
287k
  case FK_SecRel_4:
971
11
    return 4;
972
344k
  }
973
344k
}
974
975
/// getFixupKindContainerSizeBytes - The number of bytes of the
976
/// container involved in big endian.
977
51
static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
978
51
  switch (Kind) {
979
51
  default:
980
0
    llvm_unreachable("Unknown fixup kind!");
981
51
982
51
  case FK_NONE:
983
2
    return 0;
984
51
985
51
  case FK_Data_1:
986
1
    return 1;
987
51
  case FK_Data_2:
988
1
    return 2;
989
51
  case FK_Data_4:
990
11
    return 4;
991
51
992
51
  case ARM::fixup_arm_thumb_bcc:
993
3
  case ARM::fixup_arm_thumb_cp:
994
3
  case ARM::fixup_thumb_adr_pcrel_10:
995
3
  case ARM::fixup_arm_thumb_br:
996
3
  case ARM::fixup_arm_thumb_cb:
997
3
    // Instruction size is 2 bytes.
998
3
    return 2;
999
3
1000
33
  case ARM::fixup_arm_pcrel_10_unscaled:
1001
33
  case ARM::fixup_arm_ldst_pcrel_12:
1002
33
  case ARM::fixup_arm_pcrel_10:
1003
33
  case ARM::fixup_arm_pcrel_9:
1004
33
  case ARM::fixup_arm_adr_pcrel_12:
1005
33
  case ARM::fixup_arm_uncondbl:
1006
33
  case ARM::fixup_arm_condbl:
1007
33
  case ARM::fixup_arm_blx:
1008
33
  case ARM::fixup_arm_condbranch:
1009
33
  case ARM::fixup_arm_uncondbranch:
1010
33
  case ARM::fixup_t2_ldst_pcrel_12:
1011
33
  case ARM::fixup_t2_condbranch:
1012
33
  case ARM::fixup_t2_uncondbranch:
1013
33
  case ARM::fixup_t2_pcrel_10:
1014
33
  case ARM::fixup_t2_adr_pcrel_12:
1015
33
  case ARM::fixup_arm_thumb_bl:
1016
33
  case ARM::fixup_arm_thumb_blx:
1017
33
  case ARM::fixup_arm_movt_hi16:
1018
33
  case ARM::fixup_arm_movw_lo16:
1019
33
  case ARM::fixup_t2_movt_hi16:
1020
33
  case ARM::fixup_t2_movw_lo16:
1021
33
  case ARM::fixup_arm_mod_imm:
1022
33
  case ARM::fixup_t2_so_imm:
1023
33
  case ARM::fixup_bf_branch:
1024
33
  case ARM::fixup_bf_target:
1025
33
  case ARM::fixup_bfl_target:
1026
33
  case ARM::fixup_bfc_target:
1027
33
  case ARM::fixup_bfcsel_else_target:
1028
33
  case ARM::fixup_wls:
1029
33
  case ARM::fixup_le:
1030
33
    // Instruction size is 4 bytes.
1031
33
    return 4;
1032
51
  }
1033
51
}
1034
1035
void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
1036
                               const MCValue &Target,
1037
                               MutableArrayRef<char> Data, uint64_t Value,
1038
                               bool IsResolved,
1039
344k
                               const MCSubtargetInfo* STI) const {
1040
344k
  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
1041
344k
  MCContext &Ctx = Asm.getContext();
1042
344k
  Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
1043
344k
  if (!Value)
1044
25.5k
    return; // Doesn't change encoding.
1045
318k
1046
318k
  unsigned Offset = Fixup.getOffset();
1047
318k
  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
1048
318k
1049
318k
  // Used to point to big endian bytes.
1050
318k
  unsigned FullSizeBytes;
1051
318k
  if (Endian == support::big) {
1052
51
    FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
1053
51
    assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
1054
51
    assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
1055
51
  }
1056
318k
1057
318k
  // For each byte of the fragment that the fixup touches, mask in the bits from
1058
318k
  // the fixup value. The Value has been "split up" into the appropriate
1059
318k
  // bitfields above.
1060
1.44M
  for (unsigned i = 0; i != NumBytes; 
++i1.13M
) {
1061
1.13M
    unsigned Idx = Endian == support::little ? 
i1.13M
:
(FullSizeBytes - 1 - i)163
;
1062
1.13M
    Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1063
1.13M
  }
1064
318k
}
1065
1066
namespace CU {
1067
1068
/// Compact unwind encoding values.
1069
enum CompactUnwindEncodings {
1070
  UNWIND_ARM_MODE_MASK                         = 0x0F000000,
1071
  UNWIND_ARM_MODE_FRAME                        = 0x01000000,
1072
  UNWIND_ARM_MODE_FRAME_D                      = 0x02000000,
1073
  UNWIND_ARM_MODE_DWARF                        = 0x04000000,
1074
1075
  UNWIND_ARM_FRAME_STACK_ADJUST_MASK           = 0x00C00000,
1076
1077
  UNWIND_ARM_FRAME_FIRST_PUSH_R4               = 0x00000001,
1078
  UNWIND_ARM_FRAME_FIRST_PUSH_R5               = 0x00000002,
1079
  UNWIND_ARM_FRAME_FIRST_PUSH_R6               = 0x00000004,
1080
1081
  UNWIND_ARM_FRAME_SECOND_PUSH_R8              = 0x00000008,
1082
  UNWIND_ARM_FRAME_SECOND_PUSH_R9              = 0x00000010,
1083
  UNWIND_ARM_FRAME_SECOND_PUSH_R10             = 0x00000020,
1084
  UNWIND_ARM_FRAME_SECOND_PUSH_R11             = 0x00000040,
1085
  UNWIND_ARM_FRAME_SECOND_PUSH_R12             = 0x00000080,
1086
1087
  UNWIND_ARM_FRAME_D_REG_COUNT_MASK            = 0x00000F00,
1088
1089
  UNWIND_ARM_DWARF_SECTION_OFFSET              = 0x00FFFFFF
1090
};
1091
1092
} // end CU namespace
1093
1094
/// Generate compact unwind encoding for the function based on the CFI
1095
/// instructions. If the CFI instructions describe a frame that cannot be
1096
/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1097
/// tells the runtime to fallback and unwind using dwarf.
1098
uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
1099
2.78k
    ArrayRef<MCCFIInstruction> Instrs) const {
1100
2.78k
  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
1101
2.78k
  // Only armv7k uses CFI based unwinding.
1102
2.78k
  if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
1103
12
    return 0;
1104
2.77k
  // No .cfi directives means no frame.
1105
2.77k
  if (Instrs.empty())
1106
746
    return 0;
1107
2.02k
  // Start off assuming CFA is at SP+0.
1108
2.02k
  int CFARegister = ARM::SP;
1109
2.02k
  int CFARegisterOffset = 0;
1110
2.02k
  // Mark savable registers as initially unsaved
1111
2.02k
  DenseMap<unsigned, int> RegOffsets;
1112
2.02k
  int FloatRegCount = 0;
1113
2.02k
  // Process each .cfi directive and build up compact unwind info.
1114
16.9k
  for (size_t i = 0, e = Instrs.size(); i != e; 
++i14.9k
) {
1115
14.9k
    int Reg;
1116
14.9k
    const MCCFIInstruction &Inst = Instrs[i];
1117
14.9k
    switch (Inst.getOperation()) {
1118
14.9k
    case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1119
1.62k
      CFARegisterOffset = -Inst.getOffset();
1120
1.62k
      CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
1121
1.62k
      break;
1122
14.9k
    case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1123
2.04k
      CFARegisterOffset = -Inst.getOffset();
1124
2.04k
      break;
1125
14.9k
    case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1126
402
      CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
1127
402
      break;
1128
14.9k
    case MCCFIInstruction::OpOffset: // DW_CFA_offset
1129
10.8k
      Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
1130
10.8k
      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1131
10.8k
        RegOffsets[Reg] = Inst.getOffset();
1132
48
      else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1133
48
        RegOffsets[Reg] = Inst.getOffset();
1134
48
        ++FloatRegCount;
1135
48
      } else {
1136
0
        DEBUG_WITH_TYPE("compact-unwind",
1137
0
                        llvm::dbgs() << ".cfi_offset on unknown register="
1138
0
                                     << Inst.getRegister() << "\n");
1139
0
        return CU::UNWIND_ARM_MODE_DWARF;
1140
0
      }
1141
10.8k
      break;
1142
10.8k
    case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1143
0
      // Ignore
1144
0
      break;
1145
10.8k
    default:
1146
0
      // Directive not convertable to compact unwind, bail out.
1147
0
      DEBUG_WITH_TYPE("compact-unwind",
1148
0
                      llvm::dbgs()
1149
0
                          << "CFI directive not compatiable with comact "
1150
0
                             "unwind encoding, opcode=" << Inst.getOperation()
1151
0
                          << "\n");
1152
0
      return CU::UNWIND_ARM_MODE_DWARF;
1153
10.8k
      
break0
;
1154
14.9k
    }
1155
14.9k
  }
1156
2.02k
1157
2.02k
  // If no frame set up, return no unwind info.
1158
2.02k
  if ((CFARegister == ARM::SP) && 
(CFARegisterOffset == 0)4
)
1159
0
    return 0;
1160
2.02k
1161
2.02k
  // Verify standard frame (lr/r7) was used.
1162
2.02k
  if (CFARegister != ARM::R7) {
1163
4
    DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1164
4
                                                   << CFARegister
1165
4
                                                   << " instead of r7\n");
1166
4
    return CU::UNWIND_ARM_MODE_DWARF;
1167
4
  }
1168
2.02k
  int StackAdjust = CFARegisterOffset - 8;
1169
2.02k
  if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1170
0
    DEBUG_WITH_TYPE("compact-unwind",
1171
0
                    llvm::dbgs()
1172
0
                        << "LR not saved as standard frame, StackAdjust="
1173
0
                        << StackAdjust
1174
0
                        << ", CFARegisterOffset=" << CFARegisterOffset
1175
0
                        << ", lr save at offset=" << RegOffsets[14] << "\n");
1176
0
    return CU::UNWIND_ARM_MODE_DWARF;
1177
0
  }
1178
2.02k
  if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1179
0
    DEBUG_WITH_TYPE("compact-unwind",
1180
0
                    llvm::dbgs() << "r7 not saved as standard frame\n");
1181
0
    return CU::UNWIND_ARM_MODE_DWARF;
1182
0
  }
1183
2.02k
  uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1184
2.02k
1185
2.02k
  // If var-args are used, there may be a stack adjust required.
1186
2.02k
  switch (StackAdjust) {
1187
2.02k
  case 0:
1188
2.00k
    break;
1189
2.02k
  case 4:
1190
4
    CompactUnwindEncoding |= 0x00400000;
1191
4
    break;
1192
2.02k
  case 8:
1193
9
    CompactUnwindEncoding |= 0x00800000;
1194
9
    break;
1195
2.02k
  case 12:
1196
9
    CompactUnwindEncoding |= 0x00C00000;
1197
9
    break;
1198
2.02k
  default:
1199
1
    DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1200
1
                                          << ".cfi_def_cfa stack adjust ("
1201
1
                                          << StackAdjust << ") out of range\n");
1202
1
    return CU::UNWIND_ARM_MODE_DWARF;
1203
2.02k
  }
1204
2.02k
1205
2.02k
  // If r6 is saved, it must be right below r7.
1206
2.02k
  static struct {
1207
2.02k
    unsigned Reg;
1208
2.02k
    unsigned Encoding;
1209
2.02k
  } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1210
2.02k
                   {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
1211
2.02k
                   {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
1212
2.02k
                   {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
1213
2.02k
                   {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
1214
2.02k
                   {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
1215
2.02k
                   {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
1216
2.02k
                   {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};
1217
2.02k
1218
2.02k
  int CurOffset = -8 - StackAdjust;
1219
16.1k
  for (auto CSReg : GPRCSRegs) {
1220
16.1k
    auto Offset = RegOffsets.find(CSReg.Reg);
1221
16.1k
    if (Offset == RegOffsets.end())
1222
9.38k
      continue;
1223
6.78k
1224
6.78k
    int RegOffset = Offset->second;
1225
6.78k
    if (RegOffset != CurOffset - 4) {
1226
1
      DEBUG_WITH_TYPE("compact-unwind",
1227
1
                      llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1228
1
                                   << RegOffset << " but only supported at "
1229
1
                                   << CurOffset << "\n");
1230
1
      return CU::UNWIND_ARM_MODE_DWARF;
1231
1
    }
1232
6.78k
    CompactUnwindEncoding |= CSReg.Encoding;
1233
6.78k
    CurOffset -= 4;
1234
6.78k
  }
1235
2.02k
1236
2.02k
  // If no floats saved, we are done.
1237
2.02k
  
if (2.02k
FloatRegCount == 02.02k
)
1238
2.00k
    return CompactUnwindEncoding;
1239
18
1240
18
  // Switch mode to include D register saving.
1241
18
  CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1242
18
  CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1243
18
1244
18
  // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1245
18
  // but needs coordination with the linker and libunwind.
1246
18
  if (FloatRegCount > 4) {
1247
4
    DEBUG_WITH_TYPE("compact-unwind",
1248
4
                    llvm::dbgs() << "unsupported number of D registers saved ("
1249
4
                                 << FloatRegCount << ")\n");
1250
4
      return CU::UNWIND_ARM_MODE_DWARF;
1251
4
  }
1252
14
1253
14
  // Floating point registers must either be saved sequentially, or we defer to
1254
14
  // DWARF. No gaps allowed here so check that each saved d-register is
1255
14
  // precisely where it should be.
1256
14
  static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1257
31
  for (int Idx = FloatRegCount - 1; Idx >= 0; 
--Idx17
) {
1258
17
    auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1259
17
    if (Offset == RegOffsets.end()) {
1260
0
      DEBUG_WITH_TYPE("compact-unwind",
1261
0
                      llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1262
0
                                   << MRI.getName(FPRCSRegs[Idx])
1263
0
                                   << " not saved\n");
1264
0
      return CU::UNWIND_ARM_MODE_DWARF;
1265
17
    } else if (Offset->second != CurOffset - 8) {
1266
0
      DEBUG_WITH_TYPE("compact-unwind",
1267
0
                      llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1268
0
                                   << MRI.getName(FPRCSRegs[Idx])
1269
0
                                   << " saved at " << Offset->second
1270
0
                                   << ", expected at " << CurOffset - 8
1271
0
                                   << "\n");
1272
0
      return CU::UNWIND_ARM_MODE_DWARF;
1273
0
    }
1274
17
    CurOffset -= 8;
1275
17
  }
1276
14
1277
14
  return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1278
14
}
1279
1280
3.72k
static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
1281
3.72k
  ARM::ArchKind AK = ARM::parseArch(Arch);
1282
3.72k
  switch (AK) {
1283
3.72k
  default:
1284
186
    return MachO::CPU_SUBTYPE_ARM_V7;
1285
3.72k
  case ARM::ArchKind::ARMV4T:
1286
3
    return MachO::CPU_SUBTYPE_ARM_V4T;
1287
3.72k
  case ARM::ArchKind::ARMV5T:
1288
13
  case ARM::ArchKind::ARMV5TE:
1289
13
  case ARM::ArchKind::ARMV5TEJ:
1290
13
    return MachO::CPU_SUBTYPE_ARM_V5;
1291
81
  case ARM::ArchKind::ARMV6:
1292
81
  case ARM::ArchKind::ARMV6K:
1293
81
    return MachO::CPU_SUBTYPE_ARM_V6;
1294
1.41k
  case ARM::ArchKind::ARMV7A:
1295
1.41k
    return MachO::CPU_SUBTYPE_ARM_V7;
1296
504
  case ARM::ArchKind::ARMV7S:
1297
504
    return MachO::CPU_SUBTYPE_ARM_V7S;
1298
689
  case ARM::ArchKind::ARMV7K:
1299
689
    return MachO::CPU_SUBTYPE_ARM_V7K;
1300
196
  case ARM::ArchKind::ARMV6M:
1301
196
    return MachO::CPU_SUBTYPE_ARM_V6M;
1302
226
  case ARM::ArchKind::ARMV7M:
1303
226
    return MachO::CPU_SUBTYPE_ARM_V7M;
1304
410
  case ARM::ArchKind::ARMV7EM:
1305
410
    return MachO::CPU_SUBTYPE_ARM_V7EM;
1306
3.72k
  }
1307
3.72k
}
1308
1309
static MCAsmBackend *createARMAsmBackend(const Target &T,
1310
                                         const MCSubtargetInfo &STI,
1311
                                         const MCRegisterInfo &MRI,
1312
                                         const MCTargetOptions &Options,
1313
7.22k
                                         support::endianness Endian) {
1314
7.22k
  const Triple &TheTriple = STI.getTargetTriple();
1315
7.22k
  switch (TheTriple.getObjectFormat()) {
1316
7.22k
  default:
1317
0
    llvm_unreachable("unsupported object format");
1318
7.22k
  case Triple::MachO: {
1319
3.72k
    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
1320
3.72k
    return new ARMAsmBackendDarwin(T, STI, MRI, CS);
1321
7.22k
  }
1322
7.22k
  case Triple::COFF:
1323
98
    assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1324
98
    return new ARMAsmBackendWinCOFF(T, STI);
1325
7.22k
  case Triple::ELF:
1326
3.40k
    assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1327
3.40k
    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1328
3.40k
    return new ARMAsmBackendELF(T, STI, OSABI, Endian);
1329
7.22k
  }
1330
7.22k
}
1331
1332
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
1333
                                          const MCSubtargetInfo &STI,
1334
                                          const MCRegisterInfo &MRI,
1335
7.15k
                                          const MCTargetOptions &Options) {
1336
7.15k
  return createARMAsmBackend(T, STI, MRI, Options, support::little);
1337
7.15k
}
1338
1339
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
1340
                                          const MCSubtargetInfo &STI,
1341
                                          const MCRegisterInfo &MRI,
1342
72
                                          const MCTargetOptions &Options) {
1343
72
  return createARMAsmBackend(T, STI, MRI, Options, support::big);
1344
72
}