Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
Line
Count
Source (jump to first uncovered line)
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//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This class prints an ARM MCInst to a .s file.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "ARMInstPrinter.h"
14
#include "Utils/ARMBaseInfo.h"
15
#include "MCTargetDesc/ARMAddressingModes.h"
16
#include "MCTargetDesc/ARMBaseInfo.h"
17
#include "llvm/MC/MCAsmInfo.h"
18
#include "llvm/MC/MCExpr.h"
19
#include "llvm/MC/MCInst.h"
20
#include "llvm/MC/MCInstrInfo.h"
21
#include "llvm/MC/MCRegisterInfo.h"
22
#include "llvm/MC/MCSubtargetInfo.h"
23
#include "llvm/MC/SubtargetFeature.h"
24
#include "llvm/Support/Casting.h"
25
#include "llvm/Support/ErrorHandling.h"
26
#include "llvm/Support/MathExtras.h"
27
#include "llvm/Support/raw_ostream.h"
28
#include <algorithm>
29
#include <cassert>
30
#include <cstdint>
31
32
using namespace llvm;
33
34
#define DEBUG_TYPE "asm-printer"
35
36
#define PRINT_ALIAS_INSTR
37
#include "ARMGenAsmWriter.inc"
38
39
/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
40
///
41
/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
42
2.37k
static unsigned translateShiftImm(unsigned imm) {
43
2.37k
  // lsr #32 and asr #32 exist, but should be encoded as a 0.
44
2.37k
  assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
45
2.37k
46
2.37k
  if (imm == 0)
47
68
    return 32;
48
2.31k
  return imm;
49
2.31k
}
50
51
/// Prints the shift value with an immediate value.
52
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
53
2.23k
                             unsigned ShImm, bool UseMarkup) {
54
2.23k
  if (ShOpc == ARM_AM::no_shift || 
(1.86k
ShOpc == ARM_AM::lsl1.86k
&&
!ShImm920
))
55
413
    return;
56
1.82k
  O << ", ";
57
1.82k
58
1.82k
  assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
59
1.82k
  O << getShiftOpcStr(ShOpc);
60
1.82k
61
1.82k
  if (ShOpc != ARM_AM::rrx) {
62
1.74k
    O << " ";
63
1.74k
    if (UseMarkup)
64
0
      O << "<imm:";
65
1.74k
    O << "#" << translateShiftImm(ShImm);
66
1.74k
    if (UseMarkup)
67
0
      O << ">";
68
1.74k
  }
69
1.82k
}
70
71
ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
72
                               const MCRegisterInfo &MRI)
73
4.11k
    : MCInstPrinter(MAI, MII, MRI) {}
74
75
20
bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
76
20
  if (Opt == "reg-names-std") {
77
8
    DefaultAltIdx = ARM::NoRegAltName;
78
8
    return true;
79
8
  }
80
12
  if (Opt == "reg-names-raw") {
81
11
    DefaultAltIdx = ARM::RegNamesRaw;
82
11
    return true;
83
11
  }
84
1
  return false;
85
1
}
86
87
347k
void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
88
347k
  OS << markup("<reg:") << getRegisterName(RegNo, DefaultAltIdx) << markup(">");
89
347k
}
90
91
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
92
185k
                               StringRef Annot, const MCSubtargetInfo &STI) {
93
185k
  unsigned Opcode = MI->getOpcode();
94
185k
95
185k
  switch (Opcode) {
96
185k
  // Check for MOVs and print canonical forms, instead.
97
185k
  case ARM::MOVsr: {
98
143
    // FIXME: Thumb variants?
99
143
    const MCOperand &Dst = MI->getOperand(0);
100
143
    const MCOperand &MO1 = MI->getOperand(1);
101
143
    const MCOperand &MO2 = MI->getOperand(2);
102
143
    const MCOperand &MO3 = MI->getOperand(3);
103
143
104
143
    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
105
143
    printSBitModifierOperand(MI, 6, STI, O);
106
143
    printPredicateOperand(MI, 4, STI, O);
107
143
108
143
    O << '\t';
109
143
    printRegName(O, Dst.getReg());
110
143
    O << ", ";
111
143
    printRegName(O, MO1.getReg());
112
143
113
143
    O << ", ";
114
143
    printRegName(O, MO2.getReg());
115
143
    assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
116
143
    printAnnotation(O, Annot);
117
143
    return;
118
185k
  }
119
185k
120
185k
  case ARM::MOVsi: {
121
656
    // FIXME: Thumb variants?
122
656
    const MCOperand &Dst = MI->getOperand(0);
123
656
    const MCOperand &MO1 = MI->getOperand(1);
124
656
    const MCOperand &MO2 = MI->getOperand(2);
125
656
126
656
    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
127
656
    printSBitModifierOperand(MI, 5, STI, O);
128
656
    printPredicateOperand(MI, 3, STI, O);
129
656
130
656
    O << '\t';
131
656
    printRegName(O, Dst.getReg());
132
656
    O << ", ";
133
656
    printRegName(O, MO1.getReg());
134
656
135
656
    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
136
26
      printAnnotation(O, Annot);
137
26
      return;
138
26
    }
139
630
140
630
    O << ", " << markup("<imm:") << "#"
141
630
      << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
142
630
    printAnnotation(O, Annot);
143
630
    return;
144
630
  }
145
630
146
630
  // A8.6.123 PUSH
147
2.67k
  case ARM::STMDB_UPD:
148
2.67k
  case ARM::t2STMDB_UPD:
149
2.67k
    if (MI->getOperand(0).getReg() == ARM::SP && 
MI->getNumOperands() > 52.66k
) {
150
2.64k
      // Should only print PUSH if there are at least two registers in the list.
151
2.64k
      O << '\t' << "push";
152
2.64k
      printPredicateOperand(MI, 2, STI, O);
153
2.64k
      if (Opcode == ARM::t2STMDB_UPD)
154
230
        O << ".w";
155
2.64k
      O << '\t';
156
2.64k
      printRegisterList(MI, 4, STI, O);
157
2.64k
      printAnnotation(O, Annot);
158
2.64k
      return;
159
2.64k
    } else
160
33
      break;
161
0
162
259
  case ARM::STR_PRE_IMM:
163
259
    if (MI->getOperand(2).getReg() == ARM::SP &&
164
259
        
MI->getOperand(3).getImm() == -4240
) {
165
221
      O << '\t' << "push";
166
221
      printPredicateOperand(MI, 4, STI, O);
167
221
      O << "\t{";
168
221
      printRegName(O, MI->getOperand(1).getReg());
169
221
      O << "}";
170
221
      printAnnotation(O, Annot);
171
221
      return;
172
221
    } else
173
38
      break;
174
0
175
0
  // A8.6.122 POP
176
2.76k
  case ARM::LDMIA_UPD:
177
2.76k
  case ARM::t2LDMIA_UPD:
178
2.76k
    if (MI->getOperand(0).getReg() == ARM::SP && 
MI->getNumOperands() > 52.70k
) {
179
2.68k
      // Should only print POP if there are at least two registers in the list.
180
2.68k
      O << '\t' << "pop";
181
2.68k
      printPredicateOperand(MI, 2, STI, O);
182
2.68k
      if (Opcode == ARM::t2LDMIA_UPD)
183
303
        O << ".w";
184
2.68k
      O << '\t';
185
2.68k
      printRegisterList(MI, 4, STI, O);
186
2.68k
      printAnnotation(O, Annot);
187
2.68k
      return;
188
2.68k
    } else
189
74
      break;
190
0
191
503
  case ARM::LDR_POST_IMM:
192
503
    if (MI->getOperand(2).getReg() == ARM::SP &&
193
503
        
MI->getOperand(4).getImm() == 4222
) {
194
218
      O << '\t' << "pop";
195
218
      printPredicateOperand(MI, 5, STI, O);
196
218
      O << "\t{";
197
218
      printRegName(O, MI->getOperand(0).getReg());
198
218
      O << "}";
199
218
      printAnnotation(O, Annot);
200
218
      return;
201
218
    } else
202
285
      break;
203
0
204
0
  // A8.6.355 VPUSH
205
432
  case ARM::VSTMSDB_UPD:
206
432
  case ARM::VSTMDDB_UPD:
207
432
    if (MI->getOperand(0).getReg() == ARM::SP) {
208
430
      O << '\t' << "vpush";
209
430
      printPredicateOperand(MI, 2, STI, O);
210
430
      O << '\t';
211
430
      printRegisterList(MI, 4, STI, O);
212
430
      printAnnotation(O, Annot);
213
430
      return;
214
430
    } else
215
2
      break;
216
0
217
0
  // A8.6.354 VPOP
218
442
  case ARM::VLDMSIA_UPD:
219
442
  case ARM::VLDMDIA_UPD:
220
442
    if (MI->getOperand(0).getReg() == ARM::SP) {
221
438
      O << '\t' << "vpop";
222
438
      printPredicateOperand(MI, 2, STI, O);
223
438
      O << '\t';
224
438
      printRegisterList(MI, 4, STI, O);
225
438
      printAnnotation(O, Annot);
226
438
      return;
227
438
    } else
228
4
      break;
229
0
230
217
  case ARM::tLDMIA: {
231
217
    bool Writeback = true;
232
217
    unsigned BaseReg = MI->getOperand(0).getReg();
233
1.03k
    for (unsigned i = 3; i < MI->getNumOperands(); 
++i815
) {
234
815
      if (MI->getOperand(i).getReg() == BaseReg)
235
162
        Writeback = false;
236
815
    }
237
217
238
217
    O << "\tldm";
239
217
240
217
    printPredicateOperand(MI, 1, STI, O);
241
217
    O << '\t';
242
217
    printRegName(O, BaseReg);
243
217
    if (Writeback)
244
55
      O << "!";
245
217
    O << ", ";
246
217
    printRegisterList(MI, 3, STI, O);
247
217
    printAnnotation(O, Annot);
248
217
    return;
249
0
  }
250
0
251
0
  // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
252
0
  // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
253
0
  // a single GPRPair reg operand is used in the .td file to replace the two
254
0
  // GPRs. However, when decoding them, the two GRPs cannot be automatically
255
0
  // expressed as a GPRPair, so we have to manually merge them.
256
0
  // FIXME: We would really like to be able to tablegen'erate this.
257
170
  case ARM::LDREXD:
258
170
  case ARM::STREXD:
259
170
  case ARM::LDAEXD:
260
170
  case ARM::STLEXD: {
261
170
    const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
262
170
    bool isStore = Opcode == ARM::STREXD || 
Opcode == ARM::STLEXD112
;
263
170
    unsigned Reg = MI->getOperand(isStore ? 
173
:
097
).getReg();
264
170
    if (MRC.contains(Reg)) {
265
0
      MCInst NewMI;
266
0
      MCOperand NewReg;
267
0
      NewMI.setOpcode(Opcode);
268
0
269
0
      if (isStore)
270
0
        NewMI.addOperand(MI->getOperand(0));
271
0
      NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
272
0
          Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
273
0
      NewMI.addOperand(NewReg);
274
0
275
0
      // Copy the rest operands into NewMI.
276
0
      for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
277
0
        NewMI.addOperand(MI->getOperand(i));
278
0
      printInstruction(&NewMI, STI, O);
279
0
      return;
280
0
    }
281
170
    break;
282
170
  }
283
170
  case ARM::TSB:
284
4
  case ARM::t2TSB:
285
4
    O << "\ttsb\tcsync";
286
4
    return;
287
92
  case ARM::t2DSB:
288
92
    switch (MI->getOperand(0).getImm()) {
289
92
    default:
290
84
      if (!printAliasInstr(MI, STI, O))
291
82
        printInstruction(MI, STI, O);
292
84
      break;
293
92
    case 0:
294
4
      O << "\tssbb";
295
4
      break;
296
92
    case 4:
297
4
      O << "\tpssbb";
298
4
      break;
299
92
    }
300
92
    printAnnotation(O, Annot);
301
92
    return;
302
178k
  }
303
178k
304
178k
  if (!printAliasInstr(MI, STI, O))
305
177k
    printInstruction(MI, STI, O);
306
178k
307
178k
  printAnnotation(O, Annot);
308
178k
}
309
310
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
311
278k
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
312
278k
  const MCOperand &Op = MI->getOperand(OpNo);
313
278k
  if (Op.isReg()) {
314
241k
    unsigned Reg = Op.getReg();
315
241k
    printRegName(O, Reg);
316
241k
  } else 
if (37.1k
Op.isImm()37.1k
) {
317
20.8k
    O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
318
20.8k
  } else {
319
16.2k
    assert(Op.isExpr() && "unknown operand kind in printOperand");
320
16.2k
    const MCExpr *Expr = Op.getExpr();
321
16.2k
    switch (Expr->getKind()) {
322
16.2k
    case MCExpr::Binary:
323
2
      O << '#';
324
2
      Expr->print(O, &MAI);
325
2
      break;
326
16.2k
    case MCExpr::Constant: {
327
1
      // If a symbolic branch target was added as a constant expression then
328
1
      // print that address in hex. And only print 32 unsigned bits for the
329
1
      // address.
330
1
      const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
331
1
      int64_t TargetAddress;
332
1
      if (!Constant->evaluateAsAbsolute(TargetAddress)) {
333
0
        O << '#';
334
0
        Expr->print(O, &MAI);
335
1
      } else {
336
1
        O << "0x";
337
1
        O.write_hex(static_cast<uint32_t>(TargetAddress));
338
1
      }
339
1
      break;
340
16.2k
    }
341
16.2k
    default:
342
16.2k
      // FIXME: Should we always treat this as if it is a constant literal and
343
16.2k
      // prefix it with '#'?
344
16.2k
      Expr->print(O, &MAI);
345
16.2k
      break;
346
16.2k
    }
347
16.2k
  }
348
278k
}
349
350
void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
351
                                               const MCSubtargetInfo &STI,
352
1.34k
                                               raw_ostream &O) {
353
1.34k
  const MCOperand &MO1 = MI->getOperand(OpNum);
354
1.34k
  if (MO1.isExpr()) {
355
1.16k
    MO1.getExpr()->print(O, &MAI);
356
1.16k
    return;
357
1.16k
  }
358
183
359
183
  O << markup("<mem:") << "[pc, ";
360
183
361
183
  int32_t OffImm = (int32_t)MO1.getImm();
362
183
  bool isSub = OffImm < 0;
363
183
364
183
  // Special value for #-0. All others are normal.
365
183
  if (OffImm == INT32_MIN)
366
183
    
OffImm = 023
;
367
183
  if (isSub) {
368
76
    O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
369
107
  } else {
370
107
    O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
371
107
  }
372
183
  O << "]" << markup(">");
373
183
}
374
375
// so_reg is a 4-operand unit corresponding to register forms of the A5.1
376
// "Addressing Mode 1 - Data-processing operands" forms.  This includes:
377
//    REG 0   0           - e.g. R5
378
//    REG REG 0,SH_OPC    - e.g. R5, ROR R3
379
//    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
380
void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
381
                                          const MCSubtargetInfo &STI,
382
471
                                          raw_ostream &O) {
383
471
  const MCOperand &MO1 = MI->getOperand(OpNum);
384
471
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
385
471
  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
386
471
387
471
  printRegName(O, MO1.getReg());
388
471
389
471
  // Print the shift opc.
390
471
  ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
391
471
  O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
392
471
  if (ShOpc == ARM_AM::rrx)
393
0
    return;
394
471
395
471
  O << ' ';
396
471
  printRegName(O, MO2.getReg());
397
471
  assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
398
471
}
399
400
void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
401
                                          const MCSubtargetInfo &STI,
402
900
                                          raw_ostream &O) {
403
900
  const MCOperand &MO1 = MI->getOperand(OpNum);
404
900
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
405
900
406
900
  printRegName(O, MO1.getReg());
407
900
408
900
  // Print the shift opc.
409
900
  printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
410
900
                   ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
411
900
}
412
413
//===--------------------------------------------------------------------===//
414
// Addressing Mode #2
415
//===--------------------------------------------------------------------===//
416
417
void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
418
                                                const MCSubtargetInfo &STI,
419
491
                                                raw_ostream &O) {
420
491
  const MCOperand &MO1 = MI->getOperand(Op);
421
491
  const MCOperand &MO2 = MI->getOperand(Op + 1);
422
491
  const MCOperand &MO3 = MI->getOperand(Op + 2);
423
491
424
491
  O << markup("<mem:") << "[";
425
491
  printRegName(O, MO1.getReg());
426
491
427
491
  if (!MO2.getReg()) {
428
0
    if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
429
0
      O << ", " << markup("<imm:") << "#"
430
0
        << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
431
0
        << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
432
0
    }
433
0
    O << "]" << markup(">");
434
0
    return;
435
0
  }
436
491
437
491
  O << ", ";
438
491
  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
439
491
  printRegName(O, MO2.getReg());
440
491
441
491
  printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
442
491
                   ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
443
491
  O << "]" << markup(">");
444
491
}
445
446
void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
447
                                      const MCSubtargetInfo &STI,
448
27
                                      raw_ostream &O) {
449
27
  const MCOperand &MO1 = MI->getOperand(Op);
450
27
  const MCOperand &MO2 = MI->getOperand(Op + 1);
451
27
  O << markup("<mem:") << "[";
452
27
  printRegName(O, MO1.getReg());
453
27
  O << ", ";
454
27
  printRegName(O, MO2.getReg());
455
27
  O << "]" << markup(">");
456
27
}
457
458
void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
459
                                      const MCSubtargetInfo &STI,
460
9
                                      raw_ostream &O) {
461
9
  const MCOperand &MO1 = MI->getOperand(Op);
462
9
  const MCOperand &MO2 = MI->getOperand(Op + 1);
463
9
  O << markup("<mem:") << "[";
464
9
  printRegName(O, MO1.getReg());
465
9
  O << ", ";
466
9
  printRegName(O, MO2.getReg());
467
9
  O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
468
9
}
469
470
void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
471
                                           const MCSubtargetInfo &STI,
472
491
                                           raw_ostream &O) {
473
491
  const MCOperand &MO1 = MI->getOperand(Op);
474
491
475
491
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
476
0
    printOperand(MI, Op, STI, O);
477
0
    return;
478
0
  }
479
491
480
#ifndef NDEBUG
481
  const MCOperand &MO3 = MI->getOperand(Op + 2);
482
  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
483
  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
484
#endif
485
486
491
  printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
487
491
}
488
489
void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
490
                                                 unsigned OpNum,
491
                                                 const MCSubtargetInfo &STI,
492
1.83k
                                                 raw_ostream &O) {
493
1.83k
  const MCOperand &MO1 = MI->getOperand(OpNum);
494
1.83k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
495
1.83k
496
1.83k
  if (!MO1.getReg()) {
497
1.77k
    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
498
1.77k
    O << markup("<imm:") << '#'
499
1.77k
      << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
500
1.77k
      << markup(">");
501
1.77k
    return;
502
1.77k
  }
503
56
504
56
  O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
505
56
  printRegName(O, MO1.getReg());
506
56
507
56
  printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
508
56
                   ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
509
56
}
510
511
//===--------------------------------------------------------------------===//
512
// Addressing Mode #3
513
//===--------------------------------------------------------------------===//
514
515
void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
516
                                                raw_ostream &O,
517
1.04k
                                                bool AlwaysPrintImm0) {
518
1.04k
  const MCOperand &MO1 = MI->getOperand(Op);
519
1.04k
  const MCOperand &MO2 = MI->getOperand(Op + 1);
520
1.04k
  const MCOperand &MO3 = MI->getOperand(Op + 2);
521
1.04k
522
1.04k
  O << markup("<mem:") << '[';
523
1.04k
  printRegName(O, MO1.getReg());
524
1.04k
525
1.04k
  if (MO2.getReg()) {
526
35
    O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
527
35
    printRegName(O, MO2.getReg());
528
35
    O << ']' << markup(">");
529
35
    return;
530
35
  }
531
1.01k
532
1.01k
  // If the op is sub we have to print the immediate even if it is 0
533
1.01k
  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
534
1.01k
  ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
535
1.01k
536
1.01k
  if (AlwaysPrintImm0 || 
ImmOffs986
||
(op == ARM_AM::sub)722
) {
537
292
    O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
538
292
      << markup(">");
539
292
  }
540
1.01k
  O << ']' << markup(">");
541
1.01k
}
542
543
template <bool AlwaysPrintImm0>
544
void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
545
                                           const MCSubtargetInfo &STI,
546
1.04k
                                           raw_ostream &O) {
547
1.04k
  const MCOperand &MO1 = MI->getOperand(Op);
548
1.04k
  if (!MO1.isReg()) { //  For label symbolic references.
549
1
    printOperand(MI, Op, STI, O);
550
1
    return;
551
1
  }
552
1.04k
553
1.04k
  assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
554
1.04k
             ARMII::IndexModePost &&
555
1.04k
         "unexpected idxmode");
556
1.04k
  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
557
1.04k
}
void llvm::ARMInstPrinter::printAddrMode3Operand<false>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
546
1.00k
                                           raw_ostream &O) {
547
1.00k
  const MCOperand &MO1 = MI->getOperand(Op);
548
1.00k
  if (!MO1.isReg()) { //  For label symbolic references.
549
1
    printOperand(MI, Op, STI, O);
550
1
    return;
551
1
  }
552
1.00k
553
1.00k
  assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
554
1.00k
             ARMII::IndexModePost &&
555
1.00k
         "unexpected idxmode");
556
1.00k
  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
557
1.00k
}
void llvm::ARMInstPrinter::printAddrMode3Operand<true>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
546
45
                                           raw_ostream &O) {
547
45
  const MCOperand &MO1 = MI->getOperand(Op);
548
45
  if (!MO1.isReg()) { //  For label symbolic references.
549
0
    printOperand(MI, Op, STI, O);
550
0
    return;
551
0
  }
552
45
553
45
  assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
554
45
             ARMII::IndexModePost &&
555
45
         "unexpected idxmode");
556
45
  printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
557
45
}
558
559
void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
560
                                                 unsigned OpNum,
561
                                                 const MCSubtargetInfo &STI,
562
396
                                                 raw_ostream &O) {
563
396
  const MCOperand &MO1 = MI->getOperand(OpNum);
564
396
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
565
396
566
396
  if (MO1.getReg()) {
567
28
    O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
568
28
    printRegName(O, MO1.getReg());
569
28
    return;
570
28
  }
571
368
572
368
  unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
573
368
  O << markup("<imm:") << '#'
574
368
    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
575
368
    << markup(">");
576
368
}
577
578
void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
579
                                             const MCSubtargetInfo &STI,
580
25
                                             raw_ostream &O) {
581
25
  const MCOperand &MO = MI->getOperand(OpNum);
582
25
  unsigned Imm = MO.getImm();
583
25
  O << markup("<imm:") << '#' << ((Imm & 256) ? 
""15
:
"-"10
) << (Imm & 0xff)
584
25
    << markup(">");
585
25
}
586
587
void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
588
                                            const MCSubtargetInfo &STI,
589
27
                                            raw_ostream &O) {
590
27
  const MCOperand &MO1 = MI->getOperand(OpNum);
591
27
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
592
27
593
27
  O << (MO2.getImm() ? 
""18
:
"-"9
);
594
27
  printRegName(O, MO1.getReg());
595
27
}
596
597
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
598
                                               const MCSubtargetInfo &STI,
599
221
                                               raw_ostream &O) {
600
221
  const MCOperand &MO = MI->getOperand(OpNum);
601
221
  unsigned Imm = MO.getImm();
602
221
  O << markup("<imm:") << '#' << ((Imm & 256) ? 
""106
:
"-"115
) << ((Imm & 0xff) << 2)
603
221
    << markup(">");
604
221
}
605
606
template<int shift>
607
void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
608
                                               const MCSubtargetInfo &STI,
609
155
                                               raw_ostream &O) {
610
155
  const MCOperand &MO1 = MI->getOperand(OpNum);
611
155
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612
155
613
155
  O << markup("<mem:") << "[";
614
155
  printRegName(O, MO1.getReg());
615
155
  O << ", ";
616
155
  printRegName(O, MO2.getReg());
617
155
618
155
  if (shift > 0)
619
41
    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
620
155
621
155
  O << "]" << markup(">");
622
155
}
void llvm::ARMInstPrinter::printMveAddrModeRQOperand<0>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
609
114
                                               raw_ostream &O) {
610
114
  const MCOperand &MO1 = MI->getOperand(OpNum);
611
114
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612
114
613
114
  O << markup("<mem:") << "[";
614
114
  printRegName(O, MO1.getReg());
615
114
  O << ", ";
616
114
  printRegName(O, MO2.getReg());
617
114
618
114
  if (shift > 0)
619
0
    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
620
114
621
114
  O << "]" << markup(">");
622
114
}
void llvm::ARMInstPrinter::printMveAddrModeRQOperand<3>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
609
14
                                               raw_ostream &O) {
610
14
  const MCOperand &MO1 = MI->getOperand(OpNum);
611
14
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612
14
613
14
  O << markup("<mem:") << "[";
614
14
  printRegName(O, MO1.getReg());
615
14
  O << ", ";
616
14
  printRegName(O, MO2.getReg());
617
14
618
14
  if (shift > 0)
619
14
    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
620
14
621
14
  O << "]" << markup(">");
622
14
}
void llvm::ARMInstPrinter::printMveAddrModeRQOperand<1>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
609
13
                                               raw_ostream &O) {
610
13
  const MCOperand &MO1 = MI->getOperand(OpNum);
611
13
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612
13
613
13
  O << markup("<mem:") << "[";
614
13
  printRegName(O, MO1.getReg());
615
13
  O << ", ";
616
13
  printRegName(O, MO2.getReg());
617
13
618
13
  if (shift > 0)
619
13
    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
620
13
621
13
  O << "]" << markup(">");
622
13
}
void llvm::ARMInstPrinter::printMveAddrModeRQOperand<2>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
609
14
                                               raw_ostream &O) {
610
14
  const MCOperand &MO1 = MI->getOperand(OpNum);
611
14
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
612
14
613
14
  O << markup("<mem:") << "[";
614
14
  printRegName(O, MO1.getReg());
615
14
  O << ", ";
616
14
  printRegName(O, MO2.getReg());
617
14
618
14
  if (shift > 0)
619
14
    printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
620
14
621
14
  O << "]" << markup(">");
622
14
}
623
624
void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
625
                                               const MCSubtargetInfo &STI,
626
0
                                               raw_ostream &O) {
627
0
  const MCOperand &MO1 = MI->getOperand(OpNum);
628
0
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
629
0
630
0
  O << markup("<mem:") << "[";
631
0
  printRegName(O, MO1.getReg());
632
0
633
0
  int64_t Imm = MO2.getImm();
634
0
  if (Imm != 0)
635
0
    O << ", " << markup("<imm:") << '#' << Imm << markup(">");
636
0
637
0
  O << "]" << markup(">");
638
0
}
639
640
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
641
                                           const MCSubtargetInfo &STI,
642
0
                                           raw_ostream &O) {
643
0
  ARM_AM::AMSubMode Mode =
644
0
      ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
645
0
  O << ARM_AM::getAMSubModeStr(Mode);
646
0
}
647
648
template <bool AlwaysPrintImm0>
649
void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
650
                                           const MCSubtargetInfo &STI,
651
5.83k
                                           raw_ostream &O) {
652
5.83k
  const MCOperand &MO1 = MI->getOperand(OpNum);
653
5.83k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
654
5.83k
655
5.83k
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
656
901
    printOperand(MI, OpNum, STI, O);
657
901
    return;
658
901
  }
659
4.93k
660
4.93k
  O << markup("<mem:") << "[";
661
4.93k
  printRegName(O, MO1.getReg());
662
4.93k
663
4.93k
  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
664
4.93k
  ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
665
4.93k
  if (AlwaysPrintImm0 || 
ImmOffs4.76k
||
Op == ARM_AM::sub2.79k
) {
666
2.21k
    O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
667
2.21k
      << ImmOffs * 4 << markup(">");
668
2.21k
  }
669
4.93k
  O << "]" << markup(">");
670
4.93k
}
void llvm::ARMInstPrinter::printAddrMode5Operand<false>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
651
5.66k
                                           raw_ostream &O) {
652
5.66k
  const MCOperand &MO1 = MI->getOperand(OpNum);
653
5.66k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
654
5.66k
655
5.66k
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
656
901
    printOperand(MI, OpNum, STI, O);
657
901
    return;
658
901
  }
659
4.76k
660
4.76k
  O << markup("<mem:") << "[";
661
4.76k
  printRegName(O, MO1.getReg());
662
4.76k
663
4.76k
  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
664
4.76k
  ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
665
4.76k
  if (AlwaysPrintImm0 || ImmOffs || 
Op == ARM_AM::sub2.79k
) {
666
2.03k
    O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
667
2.03k
      << ImmOffs * 4 << markup(">");
668
2.03k
  }
669
4.76k
  O << "]" << markup(">");
670
4.76k
}
void llvm::ARMInstPrinter::printAddrMode5Operand<true>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
651
174
                                           raw_ostream &O) {
652
174
  const MCOperand &MO1 = MI->getOperand(OpNum);
653
174
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
654
174
655
174
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
656
0
    printOperand(MI, OpNum, STI, O);
657
0
    return;
658
0
  }
659
174
660
174
  O << markup("<mem:") << "[";
661
174
  printRegName(O, MO1.getReg());
662
174
663
174
  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
664
174
  ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
665
174
  if (AlwaysPrintImm0 || 
ImmOffs0
||
Op == ARM_AM::sub0
) {
666
174
    O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
667
174
      << ImmOffs * 4 << markup(">");
668
174
  }
669
174
  O << "]" << markup(">");
670
174
}
671
672
template <bool AlwaysPrintImm0>
673
void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
674
                                               const MCSubtargetInfo &STI,
675
912
                                               raw_ostream &O) {
676
912
  const MCOperand &MO1 = MI->getOperand(OpNum);
677
912
  const MCOperand &MO2 = MI->getOperand(OpNum+1);
678
912
679
912
  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
680
268
    printOperand(MI, OpNum, STI, O);
681
268
    return;
682
268
  }
683
644
684
644
  O << markup("<mem:") << "[";
685
644
  printRegName(O, MO1.getReg());
686
644
687
644
  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
688
644
  unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
689
644
  if (AlwaysPrintImm0 || ImmOffs || 
Op == ARM_AM::sub527
) {
690
117
    O << ", "
691
117
      << markup("<imm:")
692
117
      << "#"
693
117
      << ARM_AM::getAddrOpcStr(ARM_AM::getAM5FP16Op(MO2.getImm()))
694
117
      << ImmOffs * 2
695
117
      << markup(">");
696
117
  }
697
644
  O << "]" << markup(">");
698
644
}
699
700
void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
701
                                           const MCSubtargetInfo &STI,
702
7.23k
                                           raw_ostream &O) {
703
7.23k
  const MCOperand &MO1 = MI->getOperand(OpNum);
704
7.23k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
705
7.23k
706
7.23k
  O << markup("<mem:") << "[";
707
7.23k
  printRegName(O, MO1.getReg());
708
7.23k
  if (MO2.getImm()) {
709
3.45k
    O << ":" << (MO2.getImm() << 3);
710
3.45k
  }
711
7.23k
  O << "]" << markup(">");
712
7.23k
}
713
714
void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
715
                                           const MCSubtargetInfo &STI,
716
5.14k
                                           raw_ostream &O) {
717
5.14k
  const MCOperand &MO1 = MI->getOperand(OpNum);
718
5.14k
  O << markup("<mem:") << "[";
719
5.14k
  printRegName(O, MO1.getReg());
720
5.14k
  O << "]" << markup(">");
721
5.14k
}
722
723
void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
724
                                                 unsigned OpNum,
725
                                                 const MCSubtargetInfo &STI,
726
720
                                                 raw_ostream &O) {
727
720
  const MCOperand &MO = MI->getOperand(OpNum);
728
720
  if (MO.getReg() == 0)
729
394
    O << "!";
730
326
  else {
731
326
    O << ", ";
732
326
    printRegName(O, MO.getReg());
733
326
  }
734
720
}
735
736
void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
737
                                                    unsigned OpNum,
738
                                                    const MCSubtargetInfo &STI,
739
309
                                                    raw_ostream &O) {
740
309
  const MCOperand &MO = MI->getOperand(OpNum);
741
309
  uint32_t v = ~MO.getImm();
742
309
  int32_t lsb = countTrailingZeros(v);
743
309
  int32_t width = (32 - countLeadingZeros(v)) - lsb;
744
309
  assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
745
309
  O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
746
309
    << '#' << width << markup(">");
747
309
}
748
749
void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
750
                                     const MCSubtargetInfo &STI,
751
612
                                     raw_ostream &O) {
752
612
  unsigned val = MI->getOperand(OpNum).getImm();
753
612
  O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
754
612
}
755
756
void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
757
                                          const MCSubtargetInfo &STI,
758
36
                                          raw_ostream &O) {
759
36
  unsigned val = MI->getOperand(OpNum).getImm();
760
36
  O << ARM_ISB::InstSyncBOptToString(val);
761
36
}
762
763
void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
764
                                          const MCSubtargetInfo &STI,
765
0
                                          raw_ostream &O) {
766
0
  unsigned val = MI->getOperand(OpNum).getImm();
767
0
  O << ARM_TSB::TraceSyncBOptToString(val);
768
0
}
769
770
void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
771
                                          const MCSubtargetInfo &STI,
772
160
                                          raw_ostream &O) {
773
160
  unsigned ShiftOp = MI->getOperand(OpNum).getImm();
774
160
  bool isASR = (ShiftOp & (1 << 5)) != 0;
775
160
  unsigned Amt = ShiftOp & 0x1f;
776
160
  if (isASR) {
777
19
    O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 
327
:
Amt12
)
778
19
      << markup(">");
779
141
  } else if (Amt) {
780
13
    O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
781
13
  }
782
160
}
783
784
void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
785
                                         const MCSubtargetInfo &STI,
786
47
                                         raw_ostream &O) {
787
47
  unsigned Imm = MI->getOperand(OpNum).getImm();
788
47
  if (Imm == 0)
789
20
    return;
790
27
  assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
791
27
  O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
792
27
}
793
794
void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
795
                                         const MCSubtargetInfo &STI,
796
26
                                         raw_ostream &O) {
797
26
  unsigned Imm = MI->getOperand(OpNum).getImm();
798
26
  // A shift amount of 32 is encoded as 0.
799
26
  if (Imm == 0)
800
0
    Imm = 32;
801
26
  assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
802
26
  O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
803
26
}
804
805
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
806
                                       const MCSubtargetInfo &STI,
807
11.9k
                                       raw_ostream &O) {
808
11.9k
  if (MI->getOpcode() != ARM::t2CLRM) {
809
11.9k
    assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
810
11.9k
                          [&](const MCOperand &LHS, const MCOperand &RHS) {
811
11.9k
                            return MRI.getEncodingValue(LHS.getReg()) <
812
11.9k
                                   MRI.getEncodingValue(RHS.getReg());
813
11.9k
                          }));
814
11.9k
  }
815
11.9k
816
11.9k
  O << "{";
817
48.9k
  for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; 
++i37.0k
) {
818
37.0k
    if (i != OpNum)
819
25.1k
      O << ", ";
820
37.0k
    printRegName(O, MI->getOperand(i).getReg());
821
37.0k
  }
822
11.9k
  O << "}";
823
11.9k
}
824
825
void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
826
                                         const MCSubtargetInfo &STI,
827
170
                                         raw_ostream &O) {
828
170
  unsigned Reg = MI->getOperand(OpNum).getReg();
829
170
  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
830
170
  O << ", ";
831
170
  printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
832
170
}
833
834
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
835
                                        const MCSubtargetInfo &STI,
836
28
                                        raw_ostream &O) {
837
28
  const MCOperand &Op = MI->getOperand(OpNum);
838
28
  if (Op.getImm())
839
17
    O << "be";
840
11
  else
841
11
    O << "le";
842
28
}
843
844
void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
845
51
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
846
51
  const MCOperand &Op = MI->getOperand(OpNum);
847
51
  O << ARM_PROC::IModToString(Op.getImm());
848
51
}
849
850
void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
851
51
                                   const MCSubtargetInfo &STI, raw_ostream &O) {
852
51
  const MCOperand &Op = MI->getOperand(OpNum);
853
51
  unsigned IFlags = Op.getImm();
854
204
  for (int i = 2; i >= 0; 
--i153
)
855
153
    if (IFlags & (1 << i))
856
70
      O << ARM_PROC::IFlagsToString(1 << i);
857
51
858
51
  if (IFlags == 0)
859
3
    O << "none";
860
51
}
861
862
void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
863
                                         const MCSubtargetInfo &STI,
864
516
                                         raw_ostream &O) {
865
516
  const MCOperand &Op = MI->getOperand(OpNum);
866
516
  const FeatureBitset &FeatureBits = STI.getFeatureBits();
867
516
  if (FeatureBits[ARM::FeatureMClass]) {
868
339
869
339
    unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
870
339
    unsigned Opcode = MI->getOpcode();
871
339
872
339
    // For writes, handle extended mask bits if the DSP extension is present.
873
339
    if (Opcode == ARM::t2MSR_M && 
FeatureBits[ARM::FeatureDSP]195
) {
874
106
      auto TheReg =ARMSysReg::lookupMClassSysRegBy12bitSYSmValue(SYSm);
875
106
      if (TheReg && 
TheReg->isInRequiredFeatures({ARM::FeatureDSP})102
) {
876
33
          O << TheReg->Name;
877
33
          return;
878
33
      }
879
306
    }
880
306
881
306
    // Handle the basic 8-bit mask.
882
306
    SYSm &= 0xff;
883
306
    if (Opcode == ARM::t2MSR_M && 
FeatureBits [ARM::HasV7Ops]162
) {
884
112
      // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
885
112
      // alias for MSR APSR_nzcvq.
886
112
      auto TheReg = ARMSysReg::lookupMClassSysRegAPSRNonDeprecated(SYSm);
887
112
      if (TheReg) {
888
37
          O << TheReg->Name;
889
37
          return;
890
37
      }
891
269
    }
892
269
893
269
    auto TheReg = ARMSysReg::lookupMClassSysRegBy8bitSYSmValue(SYSm);
894
269
    if (TheReg) {
895
259
      O << TheReg->Name;
896
259
      return;
897
259
    }
898
10
899
10
    O << SYSm;
900
10
901
10
    return;
902
10
  }
903
177
904
177
  // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
905
177
  // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
906
177
  unsigned SpecRegRBit = Op.getImm() >> 4;
907
177
  unsigned Mask = Op.getImm() & 0xf;
908
177
909
177
  if (!SpecRegRBit && 
(145
Mask == 8145
||
Mask == 499
||
Mask == 1288
)) {
910
71
    O << "APSR_";
911
71
    switch (Mask) {
912
71
    default:
913
0
      llvm_unreachable("Unexpected mask value!");
914
71
    case 4:
915
11
      O << "g";
916
11
      return;
917
71
    case 8:
918
46
      O << "nzcvq";
919
46
      return;
920
71
    case 12:
921
14
      O << "nzcvqg";
922
14
      return;
923
106
    }
924
106
  }
925
106
926
106
  if (SpecRegRBit)
927
32
    O << "SPSR";
928
74
  else
929
74
    O << "CPSR";
930
106
931
106
  if (Mask) {
932
106
    O << '_';
933
106
    if (Mask & 8)
934
82
      O << 'f';
935
106
    if (Mask & 4)
936
39
      O << 's';
937
106
    if (Mask & 2)
938
49
      O << 'x';
939
106
    if (Mask & 1)
940
84
      O << 'c';
941
106
  }
942
106
}
943
944
void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
945
                                           const MCSubtargetInfo &STI,
946
264
                                           raw_ostream &O) {
947
264
  uint32_t Banked = MI->getOperand(OpNum).getImm();
948
264
  auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
949
264
  assert(TheReg && "invalid banked register operand");
950
264
  std::string Name = TheReg->Name;
951
264
952
264
  uint32_t isSPSR = (Banked & 0x20) >> 5;
953
264
  if (isSPSR)
954
56
    Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
955
264
  O << Name;
956
264
}
957
958
void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
959
                                           const MCSubtargetInfo &STI,
960
169k
                                           raw_ostream &O) {
961
169k
  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
962
169k
  // Handle the undefined 15 CC value here for printing so we don't abort().
963
169k
  if ((unsigned)CC == 15)
964
4
    O << "<und>";
965
169k
  else if (CC != ARMCC::AL)
966
9.50k
    O << ARMCondCodeToString(CC);
967
169k
}
968
969
void ARMInstPrinter::printMandatoryRestrictedPredicateOperand(
970
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
971
156
    raw_ostream &O) {
972
156
  if ((ARMCC::CondCodes)MI->getOperand(OpNum).getImm() == ARMCC::HS)
973
12
    O << "cs";
974
144
  else
975
144
    printMandatoryPredicateOperand(MI, OpNum, STI, O);
976
156
}
977
978
void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
979
                                                    unsigned OpNum,
980
                                                    const MCSubtargetInfo &STI,
981
4.60k
                                                    raw_ostream &O) {
982
4.60k
  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
983
4.60k
  O << ARMCondCodeToString(CC);
984
4.60k
}
985
986
void ARMInstPrinter::printMandatoryInvertedPredicateOperand(const MCInst *MI,
987
                                                            unsigned OpNum,
988
                                                            const MCSubtargetInfo &STI,
989
56
                                                            raw_ostream &O) {
990
56
  ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
991
56
  O << ARMCondCodeToString(ARMCC::getOppositeCondition(CC));
992
56
}
993
994
void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
995
                                              const MCSubtargetInfo &STI,
996
36.7k
                                              raw_ostream &O) {
997
36.7k
  if (MI->getOperand(OpNum).getReg()) {
998
12.3k
    assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
999
12.3k
           "Expect ARM CPSR register!");
1000
12.3k
    O << 's';
1001
12.3k
  }
1002
36.7k
}
1003
1004
void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1005
                                          const MCSubtargetInfo &STI,
1006
1.73k
                                          raw_ostream &O) {
1007
1.73k
  O << MI->getOperand(OpNum).getImm();
1008
1.73k
}
1009
1010
void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1011
                                     const MCSubtargetInfo &STI,
1012
1.21k
                                     raw_ostream &O) {
1013
1.21k
  O << "p" << MI->getOperand(OpNum).getImm();
1014
1.21k
}
1015
1016
void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1017
                                     const MCSubtargetInfo &STI,
1018
1.57k
                                     raw_ostream &O) {
1019
1.57k
  O << "c" << MI->getOperand(OpNum).getImm();
1020
1.57k
}
1021
1022
void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1023
                                          const MCSubtargetInfo &STI,
1024
105
                                          raw_ostream &O) {
1025
105
  O << "{" << MI->getOperand(OpNum).getImm() << "}";
1026
105
}
1027
1028
void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1029
0
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
1030
0
  llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1031
0
}
1032
1033
template <unsigned scale>
1034
void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1035
                                          const MCSubtargetInfo &STI,
1036
395
                                          raw_ostream &O) {
1037
395
  const MCOperand &MO = MI->getOperand(OpNum);
1038
395
1039
395
  if (MO.isExpr()) {
1040
355
    MO.getExpr()->print(O, &MAI);
1041
355
    return;
1042
355
  }
1043
40
1044
40
  int32_t OffImm = (int32_t)MO.getImm() << scale;
1045
40
1046
40
  O << markup("<imm:");
1047
40
  if (OffImm == INT32_MIN)
1048
40
    
O << "#-0"4
;
1049
36
  else if (OffImm < 0)
1050
11
    O << "#-" << -OffImm;
1051
25
  else
1052
25
    O << "#" << OffImm;
1053
40
  O << markup(">");
1054
40
}
void llvm::ARMInstPrinter::printAdrLabelOperand<0u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1036
232
                                          raw_ostream &O) {
1037
232
  const MCOperand &MO = MI->getOperand(OpNum);
1038
232
1039
232
  if (MO.isExpr()) {
1040
207
    MO.getExpr()->print(O, &MAI);
1041
207
    return;
1042
207
  }
1043
25
1044
25
  int32_t OffImm = (int32_t)MO.getImm() << scale;
1045
25
1046
25
  O << markup("<imm:");
1047
25
  if (OffImm == INT32_MIN)
1048
25
    
O << "#-0"4
;
1049
21
  else if (OffImm < 0)
1050
11
    O << "#-" << -OffImm;
1051
10
  else
1052
10
    O << "#" << OffImm;
1053
25
  O << markup(">");
1054
25
}
void llvm::ARMInstPrinter::printAdrLabelOperand<2u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1036
163
                                          raw_ostream &O) {
1037
163
  const MCOperand &MO = MI->getOperand(OpNum);
1038
163
1039
163
  if (MO.isExpr()) {
1040
148
    MO.getExpr()->print(O, &MAI);
1041
148
    return;
1042
148
  }
1043
15
1044
15
  int32_t OffImm = (int32_t)MO.getImm() << scale;
1045
15
1046
15
  O << markup("<imm:");
1047
15
  if (OffImm == INT32_MIN)
1048
15
    
O << "#-0"0
;
1049
15
  else if (OffImm < 0)
1050
0
    O << "#-" << -OffImm;
1051
15
  else
1052
15
    O << "#" << OffImm;
1053
15
  O << markup(">");
1054
15
}
1055
1056
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1057
                                            const MCSubtargetInfo &STI,
1058
2.78k
                                            raw_ostream &O) {
1059
2.78k
  O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1060
2.78k
    << markup(">");
1061
2.78k
}
1062
1063
void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1064
                                     const MCSubtargetInfo &STI,
1065
786
                                     raw_ostream &O) {
1066
786
  unsigned Imm = MI->getOperand(OpNum).getImm();
1067
786
  O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 
3212
:
Imm774
))
1068
786
    << markup(">");
1069
786
}
1070
1071
void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1072
                                      const MCSubtargetInfo &STI,
1073
4.35k
                                      raw_ostream &O) {
1074
4.35k
  // (3 - the number of trailing zeros) is the number of then / else.
1075
4.35k
  unsigned Mask = MI->getOperand(OpNum).getImm();
1076
4.35k
  unsigned NumTZ = countTrailingZeros(Mask);
1077
4.35k
  assert(NumTZ <= 3 && "Invalid IT mask!");
1078
5.00k
  for (unsigned Pos = 3, e = NumTZ; Pos > e; 
--Pos652
) {
1079
652
    if ((Mask >> Pos) & 1)
1080
253
      O << 'e';
1081
399
    else
1082
399
      O << 't';
1083
652
  }
1084
4.35k
}
1085
1086
void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1087
                                                 const MCSubtargetInfo &STI,
1088
492
                                                 raw_ostream &O) {
1089
492
  const MCOperand &MO1 = MI->getOperand(Op);
1090
492
  const MCOperand &MO2 = MI->getOperand(Op + 1);
1091
492
1092
492
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1093
0
    printOperand(MI, Op, STI, O);
1094
0
    return;
1095
0
  }
1096
492
1097
492
  O << markup("<mem:") << "[";
1098
492
  printRegName(O, MO1.getReg());
1099
492
  if (unsigned RegNum = MO2.getReg()) {
1100
492
    O << ", ";
1101
492
    printRegName(O, RegNum);
1102
492
  }
1103
492
  O << "]" << markup(">");
1104
492
}
1105
1106
void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1107
                                                    unsigned Op,
1108
                                                    const MCSubtargetInfo &STI,
1109
                                                    raw_ostream &O,
1110
8.38k
                                                    unsigned Scale) {
1111
8.38k
  const MCOperand &MO1 = MI->getOperand(Op);
1112
8.38k
  const MCOperand &MO2 = MI->getOperand(Op + 1);
1113
8.38k
1114
8.38k
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1115
0
    printOperand(MI, Op, STI, O);
1116
0
    return;
1117
0
  }
1118
8.38k
1119
8.38k
  O << markup("<mem:") << "[";
1120
8.38k
  printRegName(O, MO1.getReg());
1121
8.38k
  if (unsigned ImmOffs = MO2.getImm()) {
1122
3.61k
    O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1123
3.61k
      << markup(">");
1124
3.61k
  }
1125
8.38k
  O << "]" << markup(">");
1126
8.38k
}
1127
1128
void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1129
                                                     unsigned Op,
1130
                                                     const MCSubtargetInfo &STI,
1131
1.60k
                                                     raw_ostream &O) {
1132
1.60k
  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1133
1.60k
}
1134
1135
void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1136
                                                     unsigned Op,
1137
                                                     const MCSubtargetInfo &STI,
1138
800
                                                     raw_ostream &O) {
1139
800
  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1140
800
}
1141
1142
void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1143
                                                     unsigned Op,
1144
                                                     const MCSubtargetInfo &STI,
1145
3.14k
                                                     raw_ostream &O) {
1146
3.14k
  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1147
3.14k
}
1148
1149
void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1150
                                                 const MCSubtargetInfo &STI,
1151
2.83k
                                                 raw_ostream &O) {
1152
2.83k
  printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1153
2.83k
}
1154
1155
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1156
// register with shift forms.
1157
// REG 0   0           - e.g. R5
1158
// REG IMM, SH_OPC     - e.g. R5, LSL #3
1159
void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1160
                                      const MCSubtargetInfo &STI,
1161
748
                                      raw_ostream &O) {
1162
748
  const MCOperand &MO1 = MI->getOperand(OpNum);
1163
748
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1164
748
1165
748
  unsigned Reg = MO1.getReg();
1166
748
  printRegName(O, Reg);
1167
748
1168
748
  // Print the shift opc.
1169
748
  assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1170
748
  printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1171
748
                   ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1172
748
}
1173
1174
template <bool AlwaysPrintImm0>
1175
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1176
                                               const MCSubtargetInfo &STI,
1177
8.35k
                                               raw_ostream &O) {
1178
8.35k
  const MCOperand &MO1 = MI->getOperand(OpNum);
1179
8.35k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1180
8.35k
1181
8.35k
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1182
732
    printOperand(MI, OpNum, STI, O);
1183
732
    return;
1184
732
  }
1185
7.62k
1186
7.62k
  O << markup("<mem:") << "[";
1187
7.62k
  printRegName(O, MO1.getReg());
1188
7.62k
1189
7.62k
  int32_t OffImm = (int32_t)MO2.getImm();
1190
7.62k
  bool isSub = OffImm < 0;
1191
7.62k
  // Special value for #-0. All others are normal.
1192
7.62k
  if (OffImm == INT32_MIN)
1193
7.62k
    
OffImm = 04
;
1194
7.62k
  if (isSub) {
1195
188
    O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1196
7.43k
  } else if (AlwaysPrintImm0 || 
OffImm > 07.33k
) {
1197
5.30k
    O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1198
5.30k
  }
1199
7.62k
  O << "]" << markup(">");
1200
7.62k
}
void llvm::ARMInstPrinter::printAddrModeImm12Operand<false>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1177
8.22k
                                               raw_ostream &O) {
1178
8.22k
  const MCOperand &MO1 = MI->getOperand(OpNum);
1179
8.22k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1180
8.22k
1181
8.22k
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1182
732
    printOperand(MI, OpNum, STI, O);
1183
732
    return;
1184
732
  }
1185
7.49k
1186
7.49k
  O << markup("<mem:") << "[";
1187
7.49k
  printRegName(O, MO1.getReg());
1188
7.49k
1189
7.49k
  int32_t OffImm = (int32_t)MO2.getImm();
1190
7.49k
  bool isSub = OffImm < 0;
1191
7.49k
  // Special value for #-0. All others are normal.
1192
7.49k
  if (OffImm == INT32_MIN)
1193
7.49k
    
OffImm = 02
;
1194
7.49k
  if (isSub) {
1195
159
    O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1196
7.33k
  } else if (AlwaysPrintImm0 || OffImm > 0) {
1197
5.20k
    O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1198
5.20k
  }
1199
7.49k
  O << "]" << markup(">");
1200
7.49k
}
void llvm::ARMInstPrinter::printAddrModeImm12Operand<true>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1177
127
                                               raw_ostream &O) {
1178
127
  const MCOperand &MO1 = MI->getOperand(OpNum);
1179
127
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1180
127
1181
127
  if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1182
0
    printOperand(MI, OpNum, STI, O);
1183
0
    return;
1184
0
  }
1185
127
1186
127
  O << markup("<mem:") << "[";
1187
127
  printRegName(O, MO1.getReg());
1188
127
1189
127
  int32_t OffImm = (int32_t)MO2.getImm();
1190
127
  bool isSub = OffImm < 0;
1191
127
  // Special value for #-0. All others are normal.
1192
127
  if (OffImm == INT32_MIN)
1193
127
    
OffImm = 02
;
1194
127
  if (isSub) {
1195
29
    O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1196
98
  } else if (AlwaysPrintImm0 || 
OffImm > 00
) {
1197
98
    O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1198
98
  }
1199
127
  O << "]" << markup(">");
1200
127
}
1201
1202
template <bool AlwaysPrintImm0>
1203
void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1204
                                                unsigned OpNum,
1205
                                                const MCSubtargetInfo &STI,
1206
1.83k
                                                raw_ostream &O) {
1207
1.83k
  const MCOperand &MO1 = MI->getOperand(OpNum);
1208
1.83k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1209
1.83k
1210
1.83k
  O << markup("<mem:") << "[";
1211
1.83k
  printRegName(O, MO1.getReg());
1212
1.83k
1213
1.83k
  int32_t OffImm = (int32_t)MO2.getImm();
1214
1.83k
  bool isSub = OffImm < 0;
1215
1.83k
  // Don't print +0.
1216
1.83k
  if (OffImm == INT32_MIN)
1217
1.83k
    
OffImm = 024
;
1218
1.83k
  if (isSub) {
1219
468
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1220
1.36k
  } else if (AlwaysPrintImm0 || 
OffImm > 01.05k
) {
1221
612
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1222
612
  }
1223
1.83k
  O << "]" << markup(">");
1224
1.83k
}
void llvm::ARMInstPrinter::printT2AddrModeImm8Operand<false>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1206
1.41k
                                                raw_ostream &O) {
1207
1.41k
  const MCOperand &MO1 = MI->getOperand(OpNum);
1208
1.41k
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1209
1.41k
1210
1.41k
  O << markup("<mem:") << "[";
1211
1.41k
  printRegName(O, MO1.getReg());
1212
1.41k
1213
1.41k
  int32_t OffImm = (int32_t)MO2.getImm();
1214
1.41k
  bool isSub = OffImm < 0;
1215
1.41k
  // Don't print +0.
1216
1.41k
  if (OffImm == INT32_MIN)
1217
1.41k
    
OffImm = 022
;
1218
1.41k
  if (isSub) {
1219
361
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1220
1.05k
  } else if (AlwaysPrintImm0 || OffImm > 0) {
1221
302
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1222
302
  }
1223
1.41k
  O << "]" << markup(">");
1224
1.41k
}
void llvm::ARMInstPrinter::printT2AddrModeImm8Operand<true>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1206
417
                                                raw_ostream &O) {
1207
417
  const MCOperand &MO1 = MI->getOperand(OpNum);
1208
417
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1209
417
1210
417
  O << markup("<mem:") << "[";
1211
417
  printRegName(O, MO1.getReg());
1212
417
1213
417
  int32_t OffImm = (int32_t)MO2.getImm();
1214
417
  bool isSub = OffImm < 0;
1215
417
  // Don't print +0.
1216
417
  if (OffImm == INT32_MIN)
1217
417
    
OffImm = 02
;
1218
417
  if (isSub) {
1219
107
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1220
310
  } else if (AlwaysPrintImm0 || 
OffImm > 00
) {
1221
310
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1222
310
  }
1223
417
  O << "]" << markup(">");
1224
417
}
1225
1226
template <bool AlwaysPrintImm0>
1227
void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1228
                                                  unsigned OpNum,
1229
                                                  const MCSubtargetInfo &STI,
1230
650
                                                  raw_ostream &O) {
1231
650
  const MCOperand &MO1 = MI->getOperand(OpNum);
1232
650
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1233
650
1234
650
  if (!MO1.isReg()) { //  For label symbolic references.
1235
0
    printOperand(MI, OpNum, STI, O);
1236
0
    return;
1237
0
  }
1238
650
1239
650
  O << markup("<mem:") << "[";
1240
650
  printRegName(O, MO1.getReg());
1241
650
1242
650
  int32_t OffImm = (int32_t)MO2.getImm();
1243
650
  bool isSub = OffImm < 0;
1244
650
1245
650
  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1246
650
1247
650
  // Don't print +0.
1248
650
  if (OffImm == INT32_MIN)
1249
650
    
OffImm = 043
;
1250
650
  if (isSub) {
1251
134
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1252
516
  } else if (AlwaysPrintImm0 || 
OffImm > 0455
) {
1253
282
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1254
282
  }
1255
650
  O << "]" << markup(">");
1256
650
}
void llvm::ARMInstPrinter::printT2AddrModeImm8s4Operand<false>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1230
534
                                                  raw_ostream &O) {
1231
534
  const MCOperand &MO1 = MI->getOperand(OpNum);
1232
534
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1233
534
1234
534
  if (!MO1.isReg()) { //  For label symbolic references.
1235
0
    printOperand(MI, OpNum, STI, O);
1236
0
    return;
1237
0
  }
1238
534
1239
534
  O << markup("<mem:") << "[";
1240
534
  printRegName(O, MO1.getReg());
1241
534
1242
534
  int32_t OffImm = (int32_t)MO2.getImm();
1243
534
  bool isSub = OffImm < 0;
1244
534
1245
534
  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1246
534
1247
534
  // Don't print +0.
1248
534
  if (OffImm == INT32_MIN)
1249
534
    
OffImm = 022
;
1250
534
  if (isSub) {
1251
79
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1252
455
  } else if (AlwaysPrintImm0 || OffImm > 0) {
1253
221
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1254
221
  }
1255
534
  O << "]" << markup(">");
1256
534
}
void llvm::ARMInstPrinter::printT2AddrModeImm8s4Operand<true>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1230
116
                                                  raw_ostream &O) {
1231
116
  const MCOperand &MO1 = MI->getOperand(OpNum);
1232
116
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1233
116
1234
116
  if (!MO1.isReg()) { //  For label symbolic references.
1235
0
    printOperand(MI, OpNum, STI, O);
1236
0
    return;
1237
0
  }
1238
116
1239
116
  O << markup("<mem:") << "[";
1240
116
  printRegName(O, MO1.getReg());
1241
116
1242
116
  int32_t OffImm = (int32_t)MO2.getImm();
1243
116
  bool isSub = OffImm < 0;
1244
116
1245
116
  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1246
116
1247
116
  // Don't print +0.
1248
116
  if (OffImm == INT32_MIN)
1249
116
    
OffImm = 021
;
1250
116
  if (isSub) {
1251
55
    O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1252
61
  } else if (AlwaysPrintImm0 || 
OffImm > 00
) {
1253
61
    O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1254
61
  }
1255
116
  O << "]" << markup(">");
1256
116
}
1257
1258
void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1259
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1260
139
    raw_ostream &O) {
1261
139
  const MCOperand &MO1 = MI->getOperand(OpNum);
1262
139
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1263
139
1264
139
  O << markup("<mem:") << "[";
1265
139
  printRegName(O, MO1.getReg());
1266
139
  if (MO2.getImm()) {
1267
22
    O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1268
22
      << markup(">");
1269
22
  }
1270
139
  O << "]" << markup(">");
1271
139
}
1272
1273
void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1274
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1275
1.32k
    raw_ostream &O) {
1276
1.32k
  const MCOperand &MO1 = MI->getOperand(OpNum);
1277
1.32k
  int32_t OffImm = (int32_t)MO1.getImm();
1278
1.32k
  O << ", " << markup("<imm:");
1279
1.32k
  if (OffImm == INT32_MIN)
1280
1.32k
    
O << "#-0"2
;
1281
1.32k
  else if (OffImm < 0)
1282
91
    O << "#-" << -OffImm;
1283
1.23k
  else
1284
1.23k
    O << "#" << OffImm;
1285
1.32k
  O << markup(">");
1286
1.32k
}
1287
1288
void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1289
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1290
189
    raw_ostream &O) {
1291
189
  const MCOperand &MO1 = MI->getOperand(OpNum);
1292
189
  int32_t OffImm = (int32_t)MO1.getImm();
1293
189
1294
189
  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1295
189
1296
189
  O << ", " << markup("<imm:");
1297
189
  if (OffImm == INT32_MIN)
1298
189
    
O << "#-0"21
;
1299
168
  else if (OffImm < 0)
1300
99
    O << "#-" << -OffImm;
1301
69
  else
1302
69
    O << "#" << OffImm;
1303
189
  O << markup(">");
1304
189
}
1305
1306
void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1307
                                                 unsigned OpNum,
1308
                                                 const MCSubtargetInfo &STI,
1309
672
                                                 raw_ostream &O) {
1310
672
  const MCOperand &MO1 = MI->getOperand(OpNum);
1311
672
  const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1312
672
  const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1313
672
1314
672
  O << markup("<mem:") << "[";
1315
672
  printRegName(O, MO1.getReg());
1316
672
1317
672
  assert(MO2.getReg() && "Invalid so_reg load / store address!");
1318
672
  O << ", ";
1319
672
  printRegName(O, MO2.getReg());
1320
672
1321
672
  unsigned ShAmt = MO3.getImm();
1322
672
  if (ShAmt) {
1323
338
    assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1324
338
    O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1325
338
  }
1326
672
  O << "]" << markup(">");
1327
672
}
1328
1329
void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1330
                                       const MCSubtargetInfo &STI,
1331
462
                                       raw_ostream &O) {
1332
462
  const MCOperand &MO = MI->getOperand(OpNum);
1333
462
  O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1334
462
    << markup(">");
1335
462
}
1336
1337
void ARMInstPrinter::printVMOVModImmOperand(const MCInst *MI, unsigned OpNum,
1338
                                            const MCSubtargetInfo &STI,
1339
554
                                            raw_ostream &O) {
1340
554
  unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1341
554
  unsigned EltBits;
1342
554
  uint64_t Val = ARM_AM::decodeVMOVModImm(EncodedImm, EltBits);
1343
554
  O << markup("<imm:") << "#0x";
1344
554
  O.write_hex(Val);
1345
554
  O << markup(">");
1346
554
}
1347
1348
void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1349
                                            const MCSubtargetInfo &STI,
1350
270
                                            raw_ostream &O) {
1351
270
  unsigned Imm = MI->getOperand(OpNum).getImm();
1352
270
  O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1353
270
}
1354
1355
void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1356
                                        const MCSubtargetInfo &STI,
1357
1.09k
                                        raw_ostream &O) {
1358
1.09k
  unsigned Imm = MI->getOperand(OpNum).getImm();
1359
1.09k
  if (Imm == 0)
1360
682
    return;
1361
417
  assert(Imm <= 3 && "illegal ror immediate!");
1362
417
  O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1363
417
}
1364
1365
void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1366
                                        const MCSubtargetInfo &STI,
1367
10.3k
                                        raw_ostream &O) {
1368
10.3k
  MCOperand Op = MI->getOperand(OpNum);
1369
10.3k
1370
10.3k
  // Support for fixups (MCFixup)
1371
10.3k
  if (Op.isExpr())
1372
2
    return printOperand(MI, OpNum, STI, O);
1373
10.3k
1374
10.3k
  unsigned Bits = Op.getImm() & 0xFF;
1375
10.3k
  unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1376
10.3k
1377
10.3k
  bool PrintUnsigned = false;
1378
10.3k
  switch (MI->getOpcode()) {
1379
10.3k
  case ARM::MOVi:
1380
3.12k
    // Movs to PC should be treated unsigned
1381
3.12k
    PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1382
3.12k
    break;
1383
10.3k
  case ARM::MSRi:
1384
63
    // Movs to special registers should be treated unsigned
1385
63
    PrintUnsigned = true;
1386
63
    break;
1387
10.3k
  }
1388
10.3k
1389
10.3k
  int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1390
10.3k
  if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1391
9.97k
    // #rot has the least possible value
1392
9.97k
    O << "#" << markup("<imm:");
1393
9.97k
    if (PrintUnsigned)
1394
58
      O << static_cast<uint32_t>(Rotated);
1395
9.91k
    else
1396
9.91k
      O << Rotated;
1397
9.97k
    O << markup(">");
1398
9.97k
    return;
1399
9.97k
  }
1400
341
1401
341
  // Explicit #bits, #rot implied
1402
341
  O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1403
341
    << Rot << markup(">");
1404
341
}
1405
1406
void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1407
32
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
1408
32
  O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1409
32
    << markup(">");
1410
32
}
1411
1412
void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1413
32
                                  const MCSubtargetInfo &STI, raw_ostream &O) {
1414
32
  O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1415
32
    << markup(">");
1416
32
}
1417
1418
void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1419
                                      const MCSubtargetInfo &STI,
1420
2.96k
                                      raw_ostream &O) {
1421
2.96k
  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1422
2.96k
}
1423
1424
void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1425
                                        const MCSubtargetInfo &STI,
1426
428
                                        raw_ostream &O) {
1427
428
  O << "{";
1428
428
  printRegName(O, MI->getOperand(OpNum).getReg());
1429
428
  O << "}";
1430
428
}
1431
1432
void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1433
                                        const MCSubtargetInfo &STI,
1434
4.47k
                                        raw_ostream &O) {
1435
4.47k
  unsigned Reg = MI->getOperand(OpNum).getReg();
1436
4.47k
  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1437
4.47k
  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1438
4.47k
  O << "{";
1439
4.47k
  printRegName(O, Reg0);
1440
4.47k
  O << ", ";
1441
4.47k
  printRegName(O, Reg1);
1442
4.47k
  O << "}";
1443
4.47k
}
1444
1445
void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1446
                                              const MCSubtargetInfo &STI,
1447
84
                                              raw_ostream &O) {
1448
84
  unsigned Reg = MI->getOperand(OpNum).getReg();
1449
84
  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1450
84
  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1451
84
  O << "{";
1452
84
  printRegName(O, Reg0);
1453
84
  O << ", ";
1454
84
  printRegName(O, Reg1);
1455
84
  O << "}";
1456
84
}
1457
1458
void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1459
                                          const MCSubtargetInfo &STI,
1460
145
                                          raw_ostream &O) {
1461
145
  // Normally, it's not safe to use register enum values directly with
1462
145
  // addition to get the next register, but for VFP registers, the
1463
145
  // sort order is guaranteed because they're all of the form D<n>.
1464
145
  O << "{";
1465
145
  printRegName(O, MI->getOperand(OpNum).getReg());
1466
145
  O << ", ";
1467
145
  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1468
145
  O << ", ";
1469
145
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1470
145
  O << "}";
1471
145
}
1472
1473
void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1474
                                         const MCSubtargetInfo &STI,
1475
429
                                         raw_ostream &O) {
1476
429
  // Normally, it's not safe to use register enum values directly with
1477
429
  // addition to get the next register, but for VFP registers, the
1478
429
  // sort order is guaranteed because they're all of the form D<n>.
1479
429
  O << "{";
1480
429
  printRegName(O, MI->getOperand(OpNum).getReg());
1481
429
  O << ", ";
1482
429
  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1483
429
  O << ", ";
1484
429
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1485
429
  O << ", ";
1486
429
  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1487
429
  O << "}";
1488
429
}
1489
1490
void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1491
                                                unsigned OpNum,
1492
                                                const MCSubtargetInfo &STI,
1493
40
                                                raw_ostream &O) {
1494
40
  O << "{";
1495
40
  printRegName(O, MI->getOperand(OpNum).getReg());
1496
40
  O << "[]}";
1497
40
}
1498
1499
void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1500
                                                unsigned OpNum,
1501
                                                const MCSubtargetInfo &STI,
1502
78
                                                raw_ostream &O) {
1503
78
  unsigned Reg = MI->getOperand(OpNum).getReg();
1504
78
  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1505
78
  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1506
78
  O << "{";
1507
78
  printRegName(O, Reg0);
1508
78
  O << "[], ";
1509
78
  printRegName(O, Reg1);
1510
78
  O << "[]}";
1511
78
}
1512
1513
void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1514
                                                  unsigned OpNum,
1515
                                                  const MCSubtargetInfo &STI,
1516
0
                                                  raw_ostream &O) {
1517
0
  // Normally, it's not safe to use register enum values directly with
1518
0
  // addition to get the next register, but for VFP registers, the
1519
0
  // sort order is guaranteed because they're all of the form D<n>.
1520
0
  O << "{";
1521
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1522
0
  O << "[], ";
1523
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1524
0
  O << "[], ";
1525
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1526
0
  O << "[]}";
1527
0
}
1528
1529
void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1530
                                                 unsigned OpNum,
1531
                                                 const MCSubtargetInfo &STI,
1532
0
                                                 raw_ostream &O) {
1533
0
  // Normally, it's not safe to use register enum values directly with
1534
0
  // addition to get the next register, but for VFP registers, the
1535
0
  // sort order is guaranteed because they're all of the form D<n>.
1536
0
  O << "{";
1537
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1538
0
  O << "[], ";
1539
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1540
0
  O << "[], ";
1541
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1542
0
  O << "[], ";
1543
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1544
0
  O << "[]}";
1545
0
}
1546
1547
void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1548
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1549
51
    raw_ostream &O) {
1550
51
  unsigned Reg = MI->getOperand(OpNum).getReg();
1551
51
  unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1552
51
  unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1553
51
  O << "{";
1554
51
  printRegName(O, Reg0);
1555
51
  O << "[], ";
1556
51
  printRegName(O, Reg1);
1557
51
  O << "[]}";
1558
51
}
1559
1560
void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1561
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1562
0
    raw_ostream &O) {
1563
0
  // Normally, it's not safe to use register enum values directly with
1564
0
  // addition to get the next register, but for VFP registers, the
1565
0
  // sort order is guaranteed because they're all of the form D<n>.
1566
0
  O << "{";
1567
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1568
0
  O << "[], ";
1569
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1570
0
  O << "[], ";
1571
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1572
0
  O << "[]}";
1573
0
}
1574
1575
void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1576
    const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1577
0
    raw_ostream &O) {
1578
0
  // Normally, it's not safe to use register enum values directly with
1579
0
  // addition to get the next register, but for VFP registers, the
1580
0
  // sort order is guaranteed because they're all of the form D<n>.
1581
0
  O << "{";
1582
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1583
0
  O << "[], ";
1584
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1585
0
  O << "[], ";
1586
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1587
0
  O << "[], ";
1588
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1589
0
  O << "[]}";
1590
0
}
1591
1592
void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1593
                                                unsigned OpNum,
1594
                                                const MCSubtargetInfo &STI,
1595
0
                                                raw_ostream &O) {
1596
0
  // Normally, it's not safe to use register enum values directly with
1597
0
  // addition to get the next register, but for VFP registers, the
1598
0
  // sort order is guaranteed because they're all of the form D<n>.
1599
0
  O << "{";
1600
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1601
0
  O << ", ";
1602
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1603
0
  O << ", ";
1604
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1605
0
  O << "}";
1606
0
}
1607
1608
void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1609
                                               const MCSubtargetInfo &STI,
1610
0
                                               raw_ostream &O) {
1611
0
  // Normally, it's not safe to use register enum values directly with
1612
0
  // addition to get the next register, but for VFP registers, the
1613
0
  // sort order is guaranteed because they're all of the form D<n>.
1614
0
  O << "{";
1615
0
  printRegName(O, MI->getOperand(OpNum).getReg());
1616
0
  O << ", ";
1617
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1618
0
  O << ", ";
1619
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1620
0
  O << ", ";
1621
0
  printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1622
0
  O << "}";
1623
0
}
1624
1625
template<unsigned NumRegs>
1626
void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
1627
                                        const MCSubtargetInfo &STI,
1628
133
                                        raw_ostream &O) {
1629
133
  unsigned Reg = MI->getOperand(OpNum).getReg();
1630
133
  const char *Prefix = "{";
1631
519
  for (unsigned i = 0; i < NumRegs; 
i++386
) {
1632
386
    O << Prefix;
1633
386
    printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1634
386
    Prefix = ", ";
1635
386
  }
1636
133
  O << "}";
1637
133
}
void llvm::ARMInstPrinter::printMVEVectorList<2u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1628
73
                                        raw_ostream &O) {
1629
73
  unsigned Reg = MI->getOperand(OpNum).getReg();
1630
73
  const char *Prefix = "{";
1631
219
  for (unsigned i = 0; i < NumRegs; 
i++146
) {
1632
146
    O << Prefix;
1633
146
    printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1634
146
    Prefix = ", ";
1635
146
  }
1636
73
  O << "}";
1637
73
}
void llvm::ARMInstPrinter::printMVEVectorList<4u>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1628
60
                                        raw_ostream &O) {
1629
60
  unsigned Reg = MI->getOperand(OpNum).getReg();
1630
60
  const char *Prefix = "{";
1631
300
  for (unsigned i = 0; i < NumRegs; 
i++240
) {
1632
240
    O << Prefix;
1633
240
    printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i));
1634
240
    Prefix = ", ";
1635
240
  }
1636
60
  O << "}";
1637
60
}
1638
1639
template<int64_t Angle, int64_t Remainder>
1640
void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1641
                                            const MCSubtargetInfo &STI,
1642
201
                                            raw_ostream &O) {
1643
201
  unsigned Val = MI->getOperand(OpNo).getImm();
1644
201
  O << "#" << (Val * Angle) + Remainder;
1645
201
}
void llvm::ARMInstPrinter::printComplexRotationOp<90ll, 0ll>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1642
128
                                            raw_ostream &O) {
1643
128
  unsigned Val = MI->getOperand(OpNo).getImm();
1644
128
  O << "#" << (Val * Angle) + Remainder;
1645
128
}
void llvm::ARMInstPrinter::printComplexRotationOp<180ll, 90ll>(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
Line
Count
Source
1642
73
                                            raw_ostream &O) {
1643
73
  unsigned Val = MI->getOperand(OpNo).getImm();
1644
73
  O << "#" << (Val * Angle) + Remainder;
1645
73
}
1646
1647
void ARMInstPrinter::printVPTPredicateOperand(const MCInst *MI, unsigned OpNum,
1648
                                              const MCSubtargetInfo &STI,
1649
3.86k
                                              raw_ostream &O) {
1650
3.86k
  ARMVCC::VPTCodes CC = (ARMVCC::VPTCodes)MI->getOperand(OpNum).getImm();
1651
3.86k
  if (CC != ARMVCC::None)
1652
170
    O << ARMVPTPredToString(CC);
1653
3.86k
}
1654
1655
void ARMInstPrinter::printVPTMask(const MCInst *MI, unsigned OpNum,
1656
                                  const MCSubtargetInfo &STI,
1657
80
                                  raw_ostream &O) {
1658
80
  // (3 - the number of trailing zeroes) is the number of them / else.
1659
80
  unsigned Mask = MI->getOperand(OpNum).getImm();
1660
80
  unsigned NumTZ = countTrailingZeros(Mask);
1661
80
  assert(NumTZ <= 3 && "Invalid VPT mask!");
1662
182
  for (unsigned Pos = 3, e = NumTZ; Pos > e; 
--Pos102
) {
1663
102
    bool T = ((Mask >> Pos) & 1) == 0;
1664
102
    if (T)
1665
24
      O << 't';
1666
78
    else
1667
78
      O << 'e';
1668
102
  }
1669
80
}
1670
1671
void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
1672
                                             const MCSubtargetInfo &STI,
1673
36
                                             raw_ostream &O) {
1674
36
  uint32_t Val = MI->getOperand(OpNum).getImm();
1675
36
  O << markup("<imm:") << "#0x";
1676
36
  O.write_hex(Val);
1677
36
  O << markup(">");
1678
36
}
1679
1680
void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
1681
                                        const MCSubtargetInfo &STI,
1682
8
                                        raw_ostream &O) {
1683
8
  uint32_t Val = MI->getOperand(OpNum).getImm();
1684
8
  assert(Val <= 1 && "Invalid MVE saturate operand");
1685
8
  O << "#" << (Val == 1 ? 
484
:
644
);
1686
8
}