Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "MCTargetDesc/ARMMCExpr.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <cstdlib>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
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STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
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namespace {
49
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class ARMMCCodeEmitter : public MCCodeEmitter {
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  const MCInstrInfo &MCII;
52
  MCContext &CTX;
53
  bool IsLittleEndian;
54
55
public:
56
  ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57
3.90k
    : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58
3.90k
  }
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  ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
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  ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
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3.89k
  ~ARMMCCodeEmitter() override = default;
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710k
  bool isThumb(const MCSubtargetInfo &STI) const {
64
710k
    return STI.getFeatureBits()[ARM::ModeThumb];
65
710k
  }
66
67
21.8k
  bool isThumb2(const MCSubtargetInfo &STI) const {
68
21.8k
    return isThumb(STI) && 
STI.getFeatureBits()[ARM::FeatureThumb2]18.7k
;
69
21.8k
  }
70
71
0
  bool isTargetMachO(const MCSubtargetInfo &STI) const {
72
0
    const Triple &TT = STI.getTargetTriple();
73
0
    return TT.isOSBinFormatMachO();
74
0
  }
75
76
  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77
78
  // getBinaryCodeForInstr - TableGen'erated function for getting the
79
  // binary encoding for an instruction.
80
  uint64_t getBinaryCodeForInstr(const MCInst &MI,
81
                                 SmallVectorImpl<MCFixup> &Fixups,
82
                                 const MCSubtargetInfo &STI) const;
83
84
  /// getMachineOpValue - Return binary encoding of operand. If the machine
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  /// operand requires relocation, record the relocation and return zero.
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  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
87
                             SmallVectorImpl<MCFixup> &Fixups,
88
                             const MCSubtargetInfo &STI) const;
89
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  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91
  /// the specified operand. This is used for operands with :lower16: and
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  /// :upper16: prefixes.
93
  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
94
                               SmallVectorImpl<MCFixup> &Fixups,
95
                               const MCSubtargetInfo &STI) const;
96
97
  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98
                              unsigned &Reg, unsigned &Imm,
99
                              SmallVectorImpl<MCFixup> &Fixups,
100
                              const MCSubtargetInfo &STI) const;
101
102
  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103
  /// BL branch target.
104
  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105
                                   SmallVectorImpl<MCFixup> &Fixups,
106
                                   const MCSubtargetInfo &STI) const;
107
108
  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
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  /// BLX branch target.
110
  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111
                                    SmallVectorImpl<MCFixup> &Fixups,
112
                                    const MCSubtargetInfo &STI) const;
113
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  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115
  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116
                                   SmallVectorImpl<MCFixup> &Fixups,
117
                                   const MCSubtargetInfo &STI) const;
118
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  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120
  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121
                                    SmallVectorImpl<MCFixup> &Fixups,
122
                                    const MCSubtargetInfo &STI) const;
123
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  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
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  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126
                                   SmallVectorImpl<MCFixup> &Fixups,
127
                                   const MCSubtargetInfo &STI) const;
128
129
  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130
  /// branch target.
131
  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132
                                  SmallVectorImpl<MCFixup> &Fixups,
133
                                  const MCSubtargetInfo &STI) const;
134
135
  /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136
  /// immediate Thumb2 direct branch target.
137
  uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138
                                       SmallVectorImpl<MCFixup> &Fixups,
139
                                       const MCSubtargetInfo &STI) const;
140
141
  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142
  /// branch target.
143
  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144
                                     SmallVectorImpl<MCFixup> &Fixups,
145
                                     const MCSubtargetInfo &STI) const;
146
  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147
                                 SmallVectorImpl<MCFixup> &Fixups,
148
                                 const MCSubtargetInfo &STI) const;
149
  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150
                                  SmallVectorImpl<MCFixup> &Fixups,
151
                                  const MCSubtargetInfo &STI) const;
152
153
  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154
  /// ADR label target.
155
  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156
                              SmallVectorImpl<MCFixup> &Fixups,
157
                              const MCSubtargetInfo &STI) const;
158
  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159
                              SmallVectorImpl<MCFixup> &Fixups,
160
                              const MCSubtargetInfo &STI) const;
161
  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162
                              SmallVectorImpl<MCFixup> &Fixups,
163
                              const MCSubtargetInfo &STI) const;
164
165
  uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166
                            SmallVectorImpl<MCFixup> &Fixups,
167
                            const MCSubtargetInfo &STI) const;
168
169
  /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170
  /// operand.
171
  uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
172
                                 SmallVectorImpl<MCFixup> &Fixups,
173
                                 const MCSubtargetInfo &STI) const;
174
175
  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176
  /// operand.
177
  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
178
                                   SmallVectorImpl<MCFixup> &Fixups,
179
                                   const MCSubtargetInfo &STI) const;
180
181
  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182
  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
183
                                         SmallVectorImpl<MCFixup> &Fixups,
184
                                         const MCSubtargetInfo &STI) const;
185
186
  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187
  /// operand.
188
  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
189
                                   SmallVectorImpl<MCFixup> &Fixups,
190
                                   const MCSubtargetInfo &STI) const;
191
192
  /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193
  /// operand.
194
  uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
195
                                      SmallVectorImpl<MCFixup> &Fixups,
196
                                      const MCSubtargetInfo &STI) const;
197
198
  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199
  /// operand.
200
  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
201
                                   SmallVectorImpl<MCFixup> &Fixups,
202
                                   const MCSubtargetInfo &STI) const;
203
204
  /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205
  /// operand.
206
  template<unsigned Bits, unsigned Shift>
207
  uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
208
                                 SmallVectorImpl<MCFixup> &Fixups,
209
                                 const MCSubtargetInfo &STI) const;
210
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  /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212
  /// operand.
213
  uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
214
                                   SmallVectorImpl<MCFixup> &Fixups,
215
                                   const MCSubtargetInfo &STI) const;
216
217
  /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218
  /// operand.
219
  template<int shift>
220
  uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
221
                                  SmallVectorImpl<MCFixup> &Fixups,
222
                                  const MCSubtargetInfo &STI) const;
223
224
  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225
  /// operand as needed by load/store instructions.
226
  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
227
                               SmallVectorImpl<MCFixup> &Fixups,
228
                               const MCSubtargetInfo &STI) const;
229
230
  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231
  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
232
                               SmallVectorImpl<MCFixup> &Fixups,
233
0
                               const MCSubtargetInfo &STI) const {
234
0
    ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
235
0
    switch (Mode) {
236
0
    default: llvm_unreachable("Unknown addressing sub-mode!");
237
0
    case ARM_AM::da: return 0;
238
0
    case ARM_AM::ia: return 1;
239
0
    case ARM_AM::db: return 2;
240
0
    case ARM_AM::ib: return 3;
241
0
    }
242
0
  }
243
244
  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245
  ///
246
94
  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247
94
    switch (ShOpc) {
248
94
    case ARM_AM::no_shift:
249
64
    case ARM_AM::lsl: return 0;
250
64
    
case ARM_AM::lsr: return 113
;
251
64
    
case ARM_AM::asr: return 210
;
252
64
    case ARM_AM::ror:
253
7
    case ARM_AM::rrx: return 3;
254
7
    default:
255
0
      llvm_unreachable("Invalid ShiftOpc!");
256
94
    }
257
94
  }
258
259
  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260
  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
261
                                     SmallVectorImpl<MCFixup> &Fixups,
262
                                     const MCSubtargetInfo &STI) const;
263
264
  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265
  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
266
                                SmallVectorImpl<MCFixup> &Fixups,
267
                                const MCSubtargetInfo &STI) const;
268
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  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270
  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
271
                                     SmallVectorImpl<MCFixup> &Fixups,
272
                                     const MCSubtargetInfo &STI) const;
273
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  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275
  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
276
                               SmallVectorImpl<MCFixup> &Fixups,
277
                               const MCSubtargetInfo &STI) const;
278
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  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280
  /// operand.
281
  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
282
                                     SmallVectorImpl<MCFixup> &Fixups,
283
                                     const MCSubtargetInfo &STI) const;
284
285
  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286
  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
287
                                SmallVectorImpl<MCFixup> &Fixups,
288
                                const MCSubtargetInfo &STI) const;
289
290
  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291
  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
292
                                SmallVectorImpl<MCFixup> &Fixups,
293
                                const MCSubtargetInfo &STI) const;
294
295
  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296
  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
297
                               SmallVectorImpl<MCFixup> &Fixups,
298
                               const MCSubtargetInfo &STI) const;
299
300
  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301
  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
302
                               SmallVectorImpl<MCFixup> &Fixups,
303
                               const MCSubtargetInfo &STI) const;
304
305
  /// getCCOutOpValue - Return encoding of the 's' bit.
306
  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
307
                           SmallVectorImpl<MCFixup> &Fixups,
308
55.5k
                           const MCSubtargetInfo &STI) const {
309
55.5k
    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310
55.5k
    // '1' respectively.
311
55.5k
    return MI.getOperand(Op).getReg() == ARM::CPSR;
312
55.5k
  }
313
314
  unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315
                            SmallVectorImpl<MCFixup> &Fixups,
316
2.96k
                            const MCSubtargetInfo &ST) const {
317
2.96k
    const MCOperand &MO = MI.getOperand(Op);
318
2.96k
319
2.96k
    // Support for fixups (MCFixup)
320
2.96k
    if (MO.isExpr()) {
321
9
      const MCExpr *Expr = MO.getExpr();
322
9
      // Fixups resolve to plain values that need to be encoded.
323
9
      MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
324
9
      Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325
9
      return 0;
326
9
    }
327
2.95k
328
2.95k
    // Immediate is already in its encoded format
329
2.95k
    return MO.getImm();
330
2.95k
  }
331
332
  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333
  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
334
                           SmallVectorImpl<MCFixup> &Fixups,
335
36.9k
                           const MCSubtargetInfo &STI) const {
336
36.9k
    const MCOperand &MO = MI.getOperand(Op);
337
36.9k
338
36.9k
    // Support for fixups (MCFixup)
339
36.9k
    if (MO.isExpr()) {
340
14
      const MCExpr *Expr = MO.getExpr();
341
14
      // Fixups resolve to plain values that need to be encoded.
342
14
      MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
343
14
      Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
344
14
      return 0;
345
14
    }
346
36.9k
    unsigned SoImm = MO.getImm();
347
36.9k
    unsigned Encoded =  ARM_AM::getT2SOImmVal(SoImm);
348
36.9k
    assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349
36.9k
    return Encoded;
350
36.9k
  }
351
352
  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
353
    SmallVectorImpl<MCFixup> &Fixups,
354
    const MCSubtargetInfo &STI) const;
355
  template<unsigned Bits, unsigned Shift>
356
  unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
357
    SmallVectorImpl<MCFixup> &Fixups,
358
    const MCSubtargetInfo &STI) const;
359
  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
360
    SmallVectorImpl<MCFixup> &Fixups,
361
    const MCSubtargetInfo &STI) const;
362
363
  /// getSORegOpValue - Return an encoded so_reg shifted register value.
364
  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
365
                           SmallVectorImpl<MCFixup> &Fixups,
366
                           const MCSubtargetInfo &STI) const;
367
  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
368
                           SmallVectorImpl<MCFixup> &Fixups,
369
                           const MCSubtargetInfo &STI) const;
370
  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
371
                             SmallVectorImpl<MCFixup> &Fixups,
372
                             const MCSubtargetInfo &STI) const;
373
374
  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
375
                                   SmallVectorImpl<MCFixup> &Fixups,
376
68
                                   const MCSubtargetInfo &STI) const {
377
68
    return 64 - MI.getOperand(Op).getImm();
378
68
  }
379
380
  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
381
                                      SmallVectorImpl<MCFixup> &Fixups,
382
                                      const MCSubtargetInfo &STI) const;
383
384
  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
385
                                  SmallVectorImpl<MCFixup> &Fixups,
386
                                  const MCSubtargetInfo &STI) const;
387
  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
388
                                      SmallVectorImpl<MCFixup> &Fixups,
389
                                      const MCSubtargetInfo &STI) const;
390
  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
391
                                        SmallVectorImpl<MCFixup> &Fixups,
392
                                        const MCSubtargetInfo &STI) const;
393
  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
394
                                        SmallVectorImpl<MCFixup> &Fixups,
395
                                        const MCSubtargetInfo &STI) const;
396
  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
397
                                     SmallVectorImpl<MCFixup> &Fixups,
398
                                     const MCSubtargetInfo &STI) const;
399
400
  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
401
                             SmallVectorImpl<MCFixup> &Fixups,
402
                             const MCSubtargetInfo &STI) const;
403
  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
404
                              SmallVectorImpl<MCFixup> &Fixups,
405
                              const MCSubtargetInfo &STI) const;
406
  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
407
                              SmallVectorImpl<MCFixup> &Fixups,
408
                              const MCSubtargetInfo &STI) const;
409
  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
410
                              SmallVectorImpl<MCFixup> &Fixups,
411
                              const MCSubtargetInfo &STI) const;
412
413
  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
414
                                 SmallVectorImpl<MCFixup> &Fixups,
415
                                 const MCSubtargetInfo &STI) const;
416
  template <uint8_t shift, bool invert>
417
  unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
418
                                 SmallVectorImpl<MCFixup> &Fixups,
419
36
                                 const MCSubtargetInfo &STI) const {
420
36
    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421
36
    const MCOperand MO = MI.getOperand(Op);
422
36
    return (invert ? 
(MO.getImm() ^ 0xff)0
: MO.getImm()) >> shift;
423
36
  }
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getExpandedImmOpValue<(unsigned char)0, false>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
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Source
419
13
                                 const MCSubtargetInfo &STI) const {
420
13
    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421
13
    const MCOperand MO = MI.getOperand(Op);
422
13
    return (invert ? 
(MO.getImm() ^ 0xff)0
: MO.getImm()) >> shift;
423
13
  }
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getExpandedImmOpValue<(unsigned char)16, false>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
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Source
419
5
                                 const MCSubtargetInfo &STI) const {
420
5
    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421
5
    const MCOperand MO = MI.getOperand(Op);
422
5
    return (invert ? 
(MO.getImm() ^ 0xff)0
: MO.getImm()) >> shift;
423
5
  }
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getExpandedImmOpValue<(unsigned char)24, false>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
419
5
                                 const MCSubtargetInfo &STI) const {
420
5
    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421
5
    const MCOperand MO = MI.getOperand(Op);
422
5
    return (invert ? 
(MO.getImm() ^ 0xff)0
: MO.getImm()) >> shift;
423
5
  }
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getExpandedImmOpValue<(unsigned char)8, false>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
419
13
                                 const MCSubtargetInfo &STI) const {
420
13
    static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
421
13
    const MCOperand MO = MI.getOperand(Op);
422
13
    return (invert ? 
(MO.getImm() ^ 0xff)0
: MO.getImm()) >> shift;
423
13
  }
424
425
  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
426
                                      unsigned EncodedValue,
427
                                      const MCSubtargetInfo &STI) const;
428
  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
429
                                          unsigned EncodedValue,
430
                                          const MCSubtargetInfo &STI) const;
431
  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
432
                                    unsigned EncodedValue,
433
                                    const MCSubtargetInfo &STI) const;
434
  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
435
                                   unsigned EncodedValue,
436
                                   const MCSubtargetInfo &STI) const;
437
438
  unsigned VFPThumb2PostEncoder(const MCInst &MI,
439
                                unsigned EncodedValue,
440
                                const MCSubtargetInfo &STI) const;
441
442
  uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
443
                              SmallVectorImpl<MCFixup> &Fixups,
444
                              const MCSubtargetInfo &STI) const;
445
446
1.80M
  void EmitByte(unsigned char C, raw_ostream &OS) const {
447
1.80M
    OS << (char)C;
448
1.80M
  }
449
450
889k
  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
451
889k
    // Output the constant in little endian byte order.
452
2.69M
    for (unsigned i = 0; i != Size; 
++i1.80M
) {
453
1.80M
      unsigned Shift = IsLittleEndian ? 
i * 81.79M
:
(Size - 1 - i) * 810.7k
;
454
1.80M
      EmitByte((Val >> Shift) & 0xff, OS);
455
1.80M
    }
456
889k
  }
457
458
  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
459
                         SmallVectorImpl<MCFixup> &Fixups,
460
                         const MCSubtargetInfo &STI) const override;
461
462
  template <bool isNeg, ARM::Fixups fixup>
463
  uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
464
                              SmallVectorImpl<MCFixup> &Fixups,
465
                              const MCSubtargetInfo &STI) const;
466
467
  uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
468
                                   SmallVectorImpl<MCFixup> &Fixups,
469
                                   const MCSubtargetInfo &STI) const;
470
471
  uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
472
                             SmallVectorImpl<MCFixup> &Fixups,
473
                             const MCSubtargetInfo &STI) const;
474
  uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
475
                                        SmallVectorImpl<MCFixup> &Fixups,
476
                                        const MCSubtargetInfo &STI) const;
477
  template <unsigned size>
478
  uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
479
                                        SmallVectorImpl<MCFixup> &Fixups,
480
                                        const MCSubtargetInfo &STI) const;
481
};
482
483
} // end anonymous namespace
484
485
/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
486
/// instructions, and rewrite them to their Thumb2 form if we are currently in
487
/// Thumb2 mode.
488
unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
489
                                                 unsigned EncodedValue,
490
4.16k
                                                 const MCSubtargetInfo &STI) const {
491
4.16k
  if (isThumb2(STI)) {
492
2.52k
    // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
493
2.52k
    // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
494
2.52k
    // set to 1111.
495
2.52k
    unsigned Bit24 = EncodedValue & 0x01000000;
496
2.52k
    unsigned Bit28 = Bit24 << 4;
497
2.52k
    EncodedValue &= 0xEFFFFFFF;
498
2.52k
    EncodedValue |= Bit28;
499
2.52k
    EncodedValue |= 0x0F000000;
500
2.52k
  }
501
4.16k
502
4.16k
  return EncodedValue;
503
4.16k
}
504
505
/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
506
/// instructions, and rewrite them to their Thumb2 form if we are currently in
507
/// Thumb2 mode.
508
unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
509
                                                 unsigned EncodedValue,
510
3.75k
                                                 const MCSubtargetInfo &STI) const {
511
3.75k
  if (isThumb2(STI)) {
512
3.33k
    EncodedValue &= 0xF0FFFFFF;
513
3.33k
    EncodedValue |= 0x09000000;
514
3.33k
  }
515
3.75k
516
3.75k
  return EncodedValue;
517
3.75k
}
518
519
/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
520
/// instructions, and rewrite them to their Thumb2 form if we are currently in
521
/// Thumb2 mode.
522
unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
523
                                                 unsigned EncodedValue,
524
161
                                                 const MCSubtargetInfo &STI) const {
525
161
  if (isThumb2(STI)) {
526
132
    EncodedValue &= 0x00FFFFFF;
527
132
    EncodedValue |= 0xEE000000;
528
132
  }
529
161
530
161
  return EncodedValue;
531
161
}
532
533
/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
534
/// if we are in Thumb2.
535
unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
536
                                                 unsigned EncodedValue,
537
202
                                                 const MCSubtargetInfo &STI) const {
538
202
  if (isThumb2(STI)) {
539
101
    EncodedValue |= 0xC000000; // Set bits 27-26
540
101
  }
541
202
542
202
  return EncodedValue;
543
202
}
544
545
/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
546
/// them to their Thumb2 form if we are currently in Thumb2 mode.
547
unsigned ARMMCCodeEmitter::
548
VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
549
8.62k
                     const MCSubtargetInfo &STI) const {
550
8.62k
  if (isThumb2(STI)) {
551
7.85k
    EncodedValue &= 0x0FFFFFFF;
552
7.85k
    EncodedValue |= 0xE0000000;
553
7.85k
  }
554
8.62k
  return EncodedValue;
555
8.62k
}
556
557
/// getMachineOpValue - Return binary encoding of operand. If the machine
558
/// operand requires relocation, record the relocation and return zero.
559
unsigned ARMMCCodeEmitter::
560
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
561
                  SmallVectorImpl<MCFixup> &Fixups,
562
922k
                  const MCSubtargetInfo &STI) const {
563
922k
  if (MO.isReg()) {
564
744k
    unsigned Reg = MO.getReg();
565
744k
    unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
566
744k
567
744k
    // In NEON, Q registers are encoded as 2x their register number,
568
744k
    // because they're using the same indices as the D registers they
569
744k
    // overlap. In MVE, there are no 64-bit vector instructions, so
570
744k
    // the encodings all refer to Q-registers by their literal
571
744k
    // register number.
572
744k
573
744k
    if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
574
7.03k
      return RegNo;
575
737k
576
737k
    switch (Reg) {
577
737k
    default:
578
730k
      return RegNo;
579
737k
    
case ARM::Q0: 7.29k
case ARM::Q1: 7.29k
case ARM::Q2: 7.29k
case ARM::Q3:
580
7.29k
    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
581
7.29k
    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
582
7.29k
    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
583
7.29k
      return 2 * RegNo;
584
177k
    }
585
177k
  } else if (MO.isImm()) {
586
177k
    return static_cast<unsigned>(MO.getImm());
587
177k
  } else 
if (0
MO.isFPImm()0
) {
588
0
    return static_cast<unsigned>(APFloat(MO.getFPImm())
589
0
                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
590
0
  }
591
0
592
0
  llvm_unreachable("Unable to encode MCOperand!");
593
0
}
594
595
/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
596
bool ARMMCCodeEmitter::
597
EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
598
                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
599
41.2k
                       const MCSubtargetInfo &STI) const {
600
41.2k
  const MCOperand &MO  = MI.getOperand(OpIdx);
601
41.2k
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
602
41.2k
603
41.2k
  Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
604
41.2k
605
41.2k
  int32_t SImm = MO1.getImm();
606
41.2k
  bool isAdd = true;
607
41.2k
608
41.2k
  // Special value for #-0
609
41.2k
  if (SImm == INT32_MIN) {
610
41
    SImm = 0;
611
41
    isAdd = false;
612
41
  }
613
41.2k
614
41.2k
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
615
41.2k
  if (SImm < 0) {
616
193
    SImm = -SImm;
617
193
    isAdd = false;
618
193
  }
619
41.2k
620
41.2k
  Imm = SImm;
621
41.2k
  return isAdd;
622
41.2k
}
623
624
/// getBranchTargetOpValue - Helper function to get the branch target operand,
625
/// which is either an immediate or requires a fixup.
626
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
627
                                       unsigned FixupKind,
628
                                       SmallVectorImpl<MCFixup> &Fixups,
629
105k
                                       const MCSubtargetInfo &STI) {
630
105k
  const MCOperand &MO = MI.getOperand(OpIdx);
631
105k
632
105k
  // If the destination is an immediate, we have nothing to do.
633
105k
  if (MO.isImm()) 
return MO.getImm()36
;
634
105k
  assert(MO.isExpr() && "Unexpected branch target type!");
635
105k
  const MCExpr *Expr = MO.getExpr();
636
105k
  MCFixupKind Kind = MCFixupKind(FixupKind);
637
105k
  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
638
105k
639
105k
  // All of the information is in the fixup.
640
105k
  return 0;
641
105k
}
642
643
// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
644
// determined by negating them and XOR'ing them with bit 23.
645
12
static int32_t encodeThumbBLOffset(int32_t offset) {
646
12
  offset >>= 1;
647
12
  uint32_t S  = (offset & 0x800000) >> 23;
648
12
  uint32_t J1 = (offset & 0x400000) >> 22;
649
12
  uint32_t J2 = (offset & 0x200000) >> 21;
650
12
  J1 = (~J1 & 0x1);
651
12
  J2 = (~J2 & 0x1);
652
12
  J1 ^= S;
653
12
  J2 ^= S;
654
12
655
12
  offset &= ~0x600000;
656
12
  offset |= J1 << 22;
657
12
  offset |= J2 << 21;
658
12
659
12
  return offset;
660
12
}
661
662
/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
663
uint32_t ARMMCCodeEmitter::
664
getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
665
                        SmallVectorImpl<MCFixup> &Fixups,
666
46.2k
                        const MCSubtargetInfo &STI) const {
667
46.2k
  const MCOperand MO = MI.getOperand(OpIdx);
668
46.2k
  if (MO.isExpr())
669
46.2k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
670
46.2k
                                    Fixups, STI);
671
3
  return encodeThumbBLOffset(MO.getImm());
672
3
}
673
674
/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
675
/// BLX branch target.
676
uint32_t ARMMCCodeEmitter::
677
getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
678
                         SmallVectorImpl<MCFixup> &Fixups,
679
33
                         const MCSubtargetInfo &STI) const {
680
33
  const MCOperand MO = MI.getOperand(OpIdx);
681
33
  if (MO.isExpr())
682
24
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
683
24
                                    Fixups, STI);
684
9
  return encodeThumbBLOffset(MO.getImm());
685
9
}
686
687
/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
688
uint32_t ARMMCCodeEmitter::
689
getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
690
                        SmallVectorImpl<MCFixup> &Fixups,
691
9.03k
                        const MCSubtargetInfo &STI) const {
692
9.03k
  const MCOperand MO = MI.getOperand(OpIdx);
693
9.03k
  if (MO.isExpr())
694
8.99k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
695
8.99k
                                    Fixups, STI);
696
40
  return (MO.getImm() >> 1);
697
40
}
698
699
/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
700
uint32_t ARMMCCodeEmitter::
701
getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
702
                         SmallVectorImpl<MCFixup> &Fixups,
703
29.2k
                         const MCSubtargetInfo &STI) const {
704
29.2k
  const MCOperand MO = MI.getOperand(OpIdx);
705
29.2k
  if (MO.isExpr())
706
29.2k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
707
29.2k
                                    Fixups, STI);
708
32
  return (MO.getImm() >> 1);
709
32
}
710
711
/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
712
uint32_t ARMMCCodeEmitter::
713
getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
714
                        SmallVectorImpl<MCFixup> &Fixups,
715
11.1k
                        const MCSubtargetInfo &STI) const {
716
11.1k
  const MCOperand MO = MI.getOperand(OpIdx);
717
11.1k
  if (MO.isExpr())
718
11.1k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
719
6
  return (MO.getImm() >> 1);
720
6
}
721
722
/// Return true if this branch has a non-always predication
723
1.04k
static bool HasConditionalBranch(const MCInst &MI) {
724
1.04k
  int NumOp = MI.getNumOperands();
725
1.04k
  if (NumOp >= 2) {
726
880
    for (int i = 0; i < NumOp-1; 
++i550
) {
727
659
      const MCOperand &MCOp1 = MI.getOperand(i);
728
659
      const MCOperand &MCOp2 = MI.getOperand(i + 1);
729
659
      if (MCOp1.isImm() && 
MCOp2.isReg()329
&&
730
659
          
(329
MCOp2.getReg() == 0329
||
MCOp2.getReg() == ARM::CPSR109
)) {
731
329
        if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
732
109
          return true;
733
329
      }
734
659
    }
735
330
  }
736
1.04k
  
return false931
;
737
1.04k
}
738
739
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
740
/// target.
741
uint32_t ARMMCCodeEmitter::
742
getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
743
                       SmallVectorImpl<MCFixup> &Fixups,
744
4.34k
                       const MCSubtargetInfo &STI) const {
745
4.34k
  // FIXME: This really, really shouldn't use TargetMachine. We don't want
746
4.34k
  // coupling between MC and TM anywhere we can help it.
747
4.34k
  if (isThumb2(STI))
748
4.34k
    return
749
4.34k
      ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
750
0
  return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
751
0
}
752
753
/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
754
/// target.
755
uint32_t ARMMCCodeEmitter::
756
getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
757
                          SmallVectorImpl<MCFixup> &Fixups,
758
247
                          const MCSubtargetInfo &STI) const {
759
247
  const MCOperand MO = MI.getOperand(OpIdx);
760
247
  if (MO.isExpr()) {
761
245
    if (HasConditionalBranch(MI))
762
105
      return ::getBranchTargetOpValue(MI, OpIdx,
763
105
                                      ARM::fixup_arm_condbranch, Fixups, STI);
764
140
    return ::getBranchTargetOpValue(MI, OpIdx,
765
140
                                    ARM::fixup_arm_uncondbranch, Fixups, STI);
766
140
  }
767
2
768
2
  return MO.getImm() >> 2;
769
2
}
770
771
uint32_t ARMMCCodeEmitter::
772
getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
773
                          SmallVectorImpl<MCFixup> &Fixups,
774
798
                          const MCSubtargetInfo &STI) const {
775
798
  const MCOperand MO = MI.getOperand(OpIdx);
776
798
  if (MO.isExpr()) {
777
795
    if (HasConditionalBranch(MI))
778
4
      return ::getBranchTargetOpValue(MI, OpIdx,
779
4
                                      ARM::fixup_arm_condbl, Fixups, STI);
780
791
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
781
791
  }
782
3
783
3
  return MO.getImm() >> 2;
784
3
}
785
786
uint32_t ARMMCCodeEmitter::
787
getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
788
                          SmallVectorImpl<MCFixup> &Fixups,
789
20
                          const MCSubtargetInfo &STI) const {
790
20
  const MCOperand MO = MI.getOperand(OpIdx);
791
20
  if (MO.isExpr())
792
15
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
793
5
794
5
  return MO.getImm() >> 1;
795
5
}
796
797
/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
798
/// immediate branch target.
799
uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
800
    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
801
2.45k
    const MCSubtargetInfo &STI) const {
802
2.45k
  unsigned Val = 0;
803
2.45k
  const MCOperand MO = MI.getOperand(OpIdx);
804
2.45k
805
2.45k
  if(MO.isExpr())
806
2.40k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
807
51
  else
808
51
    Val = MO.getImm() >> 1;
809
2.45k
810
2.45k
  bool I  = (Val & 0x800000);
811
51
  bool J1 = (Val & 0x400000);
812
51
  bool J2 = (Val & 0x200000);
813
51
  if (I ^ J1)
814
0
    Val &= ~0x400000;
815
51
  else
816
51
    Val |= 0x400000;
817
51
818
51
  if (I ^ J2)
819
0
    Val &= ~0x200000;
820
51
  else
821
51
    Val |= 0x200000;
822
51
823
51
  return Val;
824
2.45k
}
825
826
/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
827
/// ADR label target.
828
uint32_t ARMMCCodeEmitter::
829
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
830
                   SmallVectorImpl<MCFixup> &Fixups,
831
30
                   const MCSubtargetInfo &STI) const {
832
30
  const MCOperand MO = MI.getOperand(OpIdx);
833
30
  if (MO.isExpr())
834
13
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
835
13
                                    Fixups, STI);
836
17
  int64_t offset = MO.getImm();
837
17
  uint32_t Val = 0x2000;
838
17
839
17
  int SoImmVal;
840
17
  if (offset == INT32_MIN) {
841
2
    Val = 0x1000;
842
2
    SoImmVal = 0;
843
15
  } else if (offset < 0) {
844
6
    Val = 0x1000;
845
6
    offset *= -1;
846
6
    SoImmVal = ARM_AM::getSOImmVal(offset);
847
6
    if(SoImmVal == -1) {
848
2
      Val = 0x2000;
849
2
      offset *= -1;
850
2
      SoImmVal = ARM_AM::getSOImmVal(offset);
851
2
    }
852
9
  } else {
853
9
    SoImmVal = ARM_AM::getSOImmVal(offset);
854
9
    if(SoImmVal == -1) {
855
2
      Val = 0x1000;
856
2
      offset *= -1;
857
2
      SoImmVal = ARM_AM::getSOImmVal(offset);
858
2
    }
859
9
  }
860
17
861
17
  assert(SoImmVal != -1 && "Not a valid so_imm value!");
862
17
863
17
  Val |= SoImmVal;
864
17
  return Val;
865
17
}
866
867
/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
868
/// target.
869
uint32_t ARMMCCodeEmitter::
870
getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
871
                   SmallVectorImpl<MCFixup> &Fixups,
872
30
                   const MCSubtargetInfo &STI) const {
873
30
  const MCOperand MO = MI.getOperand(OpIdx);
874
30
  if (MO.isExpr())
875
22
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
876
22
                                    Fixups, STI);
877
8
  int32_t Val = MO.getImm();
878
8
  if (Val == INT32_MIN)
879
8
    
Val = 0x10002
;
880
6
  else if (Val < 0) {
881
3
    Val *= -1;
882
3
    Val |= 0x1000;
883
3
  }
884
8
  return Val;
885
8
}
886
887
/// getITMaskOpValue - Return the architectural encoding of an IT
888
/// predication mask, given the MCOperand format.
889
uint32_t ARMMCCodeEmitter::
890
getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
891
                 SmallVectorImpl<MCFixup> &Fixups,
892
13.0k
                 const MCSubtargetInfo &STI) const {
893
13.0k
  const MCOperand MaskMO = MI.getOperand(OpIdx);
894
13.0k
  assert(MaskMO.isImm() && "Unexpected operand type!");
895
13.0k
896
13.0k
  unsigned Mask = MaskMO.getImm();
897
13.0k
898
13.0k
  // IT masks are encoded as a sequence of replacement low-order bits
899
13.0k
  // for the condition code. So if the low bit of the starting
900
13.0k
  // condition code is 1, then we have to flip all the bits above the
901
13.0k
  // terminating bit (which is the lowest 1 bit).
902
13.0k
  assert(OpIdx > 0 && "IT mask appears first!");
903
13.0k
  const MCOperand CondMO = MI.getOperand(OpIdx-1);
904
13.0k
  assert(CondMO.isImm() && "Unexpected operand type!");
905
13.0k
  if (CondMO.getImm() & 1) {
906
5.95k
    unsigned LowBit = Mask & -Mask;
907
5.95k
    unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
908
5.95k
    Mask ^= BitsAboveLowBit;
909
5.95k
  }
910
13.0k
911
13.0k
  return Mask;
912
13.0k
}
913
914
/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
915
/// target.
916
uint32_t ARMMCCodeEmitter::
917
getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
918
                   SmallVectorImpl<MCFixup> &Fixups,
919
68
                   const MCSubtargetInfo &STI) const {
920
68
  const MCOperand MO = MI.getOperand(OpIdx);
921
68
  if (MO.isExpr())
922
55
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
923
55
                                    Fixups, STI);
924
13
  return MO.getImm();
925
13
}
926
927
/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
928
/// operand.
929
uint32_t ARMMCCodeEmitter::
930
getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
931
                              SmallVectorImpl<MCFixup> &,
932
2.71k
                              const MCSubtargetInfo &STI) const {
933
2.71k
  // [Rn, Rm]
934
2.71k
  //   {5-3} = Rm
935
2.71k
  //   {2-0} = Rn
936
2.71k
  const MCOperand &MO1 = MI.getOperand(OpIdx);
937
2.71k
  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
938
2.71k
  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
939
2.71k
  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
940
2.71k
  return (Rm << 3) | Rn;
941
2.71k
}
942
943
/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
944
/// operand.
945
uint32_t
946
ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
947
                                        SmallVectorImpl<MCFixup> &Fixups,
948
66
                                        const MCSubtargetInfo &STI) const {
949
66
  // {4-0} = szimm5
950
66
  // The value we are trying to encode is an immediate between either the
951
66
  // range of [1-7] or [1-15] depending on whether we are dealing with the
952
66
  // u8/s8 or the u16/s16 variants respectively.
953
66
  // This value is encoded as follows, if ShiftImm is the value within those
954
66
  // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
955
66
  // or 16.
956
66
957
66
  unsigned Size, ShiftImm;
958
66
  switch(MI.getOpcode()) {
959
66
    case ARM::MVE_VSHLL_imms16bh:
960
58
    case ARM::MVE_VSHLL_imms16th:
961
58
    case ARM::MVE_VSHLL_immu16bh:
962
58
    case ARM::MVE_VSHLL_immu16th:
963
58
      Size = 16;
964
58
      break;
965
58
    case ARM::MVE_VSHLL_imms8bh:
966
8
    case ARM::MVE_VSHLL_imms8th:
967
8
    case ARM::MVE_VSHLL_immu8bh:
968
8
    case ARM::MVE_VSHLL_immu8th:
969
8
      Size = 8;
970
8
      break;
971
8
    default:
972
0
      llvm_unreachable("Use of operand not supported by this instruction");
973
66
  }
974
66
  ShiftImm = MI.getOperand(OpIdx).getImm();
975
66
  return Size + ShiftImm;
976
66
}
977
978
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
979
uint32_t ARMMCCodeEmitter::
980
getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
981
                        SmallVectorImpl<MCFixup> &Fixups,
982
20.1k
                        const MCSubtargetInfo &STI) const {
983
20.1k
  // {17-13} = reg
984
20.1k
  // {12}    = (U)nsigned (add == '1', sub == '0')
985
20.1k
  // {11-0}  = imm12
986
20.1k
  unsigned Reg, Imm12;
987
20.1k
  bool isAdd = true;
988
20.1k
  // If The first operand isn't a register, we have a label reference.
989
20.1k
  const MCOperand &MO = MI.getOperand(OpIdx);
990
20.1k
  if (!MO.isReg()) {
991
110
    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
992
110
    Imm12 = 0;
993
110
994
110
    if (MO.isExpr()) {
995
62
      const MCExpr *Expr = MO.getExpr();
996
62
      isAdd = false ; // 'U' bit is set as part of the fixup.
997
62
998
62
      MCFixupKind Kind;
999
62
      if (isThumb2(STI))
1000
28
        Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
1001
34
      else
1002
34
        Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
1003
62
      Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1004
62
1005
62
      ++MCNumCPRelocations;
1006
62
    } else {
1007
48
      Reg = ARM::PC;
1008
48
      int32_t Offset = MO.getImm();
1009
48
      if (Offset == INT32_MIN) {
1010
16
        Offset = 0;
1011
16
        isAdd = false;
1012
32
      } else if (Offset < 0) {
1013
32
        Offset *= -1;
1014
32
        isAdd = false;
1015
32
      }
1016
48
      Imm12 = Offset;
1017
48
    }
1018
110
  } else
1019
20.0k
    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
1020
20.1k
1021
20.1k
  uint32_t Binary = Imm12 & 0xfff;
1022
20.1k
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1023
20.1k
  if (isAdd)
1024
20.0k
    Binary |= (1 << 12);
1025
20.1k
  Binary |= (Reg << 13);
1026
20.1k
  return Binary;
1027
20.1k
}
1028
1029
template<unsigned Bits, unsigned Shift>
1030
uint32_t ARMMCCodeEmitter::
1031
getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1032
                      SmallVectorImpl<MCFixup> &Fixups,
1033
234
                      const MCSubtargetInfo &STI) const {
1034
234
  // FIXME: The immediate operand should have already been encoded like this
1035
234
  // before ever getting here. The encoder method should just need to combine
1036
234
  // the MI operands for the register and the offset into a single
1037
234
  // representation for the complex operand in the .td file. This isn't just
1038
234
  // style, unfortunately. As-is, we can't represent the distinct encoding
1039
234
  // for #-0.
1040
234
1041
234
  // {Bits}    = (U)nsigned (add == '1', sub == '0')
1042
234
  // {(Bits-1)-0}  = immediate
1043
234
  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044
234
  bool isAdd = Imm >= 0;
1045
234
1046
234
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047
234
  if (Imm < 0)
1048
165
    Imm = -(uint32_t)Imm;
1049
234
1050
234
  Imm >>= Shift;
1051
234
1052
234
  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053
234
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054
234
  if (isAdd)
1055
69
    Binary |= (1U << Bits);
1056
234
  return Binary;
1057
234
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2ScaledImmOpValue<7u, 0u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1033
33
                      const MCSubtargetInfo &STI) const {
1034
33
  // FIXME: The immediate operand should have already been encoded like this
1035
33
  // before ever getting here. The encoder method should just need to combine
1036
33
  // the MI operands for the register and the offset into a single
1037
33
  // representation for the complex operand in the .td file. This isn't just
1038
33
  // style, unfortunately. As-is, we can't represent the distinct encoding
1039
33
  // for #-0.
1040
33
1041
33
  // {Bits}    = (U)nsigned (add == '1', sub == '0')
1042
33
  // {(Bits-1)-0}  = immediate
1043
33
  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044
33
  bool isAdd = Imm >= 0;
1045
33
1046
33
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047
33
  if (Imm < 0)
1048
32
    Imm = -(uint32_t)Imm;
1049
33
1050
33
  Imm >>= Shift;
1051
33
1052
33
  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053
33
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054
33
  if (isAdd)
1055
1
    Binary |= (1U << Bits);
1056
33
  return Binary;
1057
33
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2ScaledImmOpValue<7u, 1u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1033
24
                      const MCSubtargetInfo &STI) const {
1034
24
  // FIXME: The immediate operand should have already been encoded like this
1035
24
  // before ever getting here. The encoder method should just need to combine
1036
24
  // the MI operands for the register and the offset into a single
1037
24
  // representation for the complex operand in the .td file. This isn't just
1038
24
  // style, unfortunately. As-is, we can't represent the distinct encoding
1039
24
  // for #-0.
1040
24
1041
24
  // {Bits}    = (U)nsigned (add == '1', sub == '0')
1042
24
  // {(Bits-1)-0}  = immediate
1043
24
  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044
24
  bool isAdd = Imm >= 0;
1045
24
1046
24
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047
24
  if (Imm < 0)
1048
20
    Imm = -(uint32_t)Imm;
1049
24
1050
24
  Imm >>= Shift;
1051
24
1052
24
  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053
24
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054
24
  if (isAdd)
1055
4
    Binary |= (1U << Bits);
1056
24
  return Binary;
1057
24
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2ScaledImmOpValue<7u, 2u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1033
117
                      const MCSubtargetInfo &STI) const {
1034
117
  // FIXME: The immediate operand should have already been encoded like this
1035
117
  // before ever getting here. The encoder method should just need to combine
1036
117
  // the MI operands for the register and the offset into a single
1037
117
  // representation for the complex operand in the .td file. This isn't just
1038
117
  // style, unfortunately. As-is, we can't represent the distinct encoding
1039
117
  // for #-0.
1040
117
1041
117
  // {Bits}    = (U)nsigned (add == '1', sub == '0')
1042
117
  // {(Bits-1)-0}  = immediate
1043
117
  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044
117
  bool isAdd = Imm >= 0;
1045
117
1046
117
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047
117
  if (Imm < 0)
1048
90
    Imm = -(uint32_t)Imm;
1049
117
1050
117
  Imm >>= Shift;
1051
117
1052
117
  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053
117
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054
117
  if (isAdd)
1055
27
    Binary |= (1U << Bits);
1056
117
  return Binary;
1057
117
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2ScaledImmOpValue<8u, 2u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1033
60
                      const MCSubtargetInfo &STI) const {
1034
60
  // FIXME: The immediate operand should have already been encoded like this
1035
60
  // before ever getting here. The encoder method should just need to combine
1036
60
  // the MI operands for the register and the offset into a single
1037
60
  // representation for the complex operand in the .td file. This isn't just
1038
60
  // style, unfortunately. As-is, we can't represent the distinct encoding
1039
60
  // for #-0.
1040
60
1041
60
  // {Bits}    = (U)nsigned (add == '1', sub == '0')
1042
60
  // {(Bits-1)-0}  = immediate
1043
60
  int32_t Imm = MI.getOperand(OpIdx).getImm();
1044
60
  bool isAdd = Imm >= 0;
1045
60
1046
60
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1047
60
  if (Imm < 0)
1048
23
    Imm = -(uint32_t)Imm;
1049
60
1050
60
  Imm >>= Shift;
1051
60
1052
60
  uint32_t Binary = Imm & ((1U << Bits) - 1);
1053
60
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1054
60
  if (isAdd)
1055
37
    Binary |= (1U << Bits);
1056
60
  return Binary;
1057
60
}
1058
1059
/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1060
/// operand.
1061
uint32_t ARMMCCodeEmitter::
1062
getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1063
                        SmallVectorImpl<MCFixup> &Fixups,
1064
155
                        const MCSubtargetInfo &STI) const {
1065
155
    // {6-3} Rn
1066
155
    // {2-0} Qm
1067
155
    const MCOperand &M0 = MI.getOperand(OpIdx);
1068
155
    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1069
155
1070
155
    unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1071
155
    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1072
155
1073
155
    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1074
155
1075
155
    return (Rn << 3) | Qm;
1076
155
}
1077
1078
/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1079
/// operand.
1080
template<int shift>
1081
uint32_t ARMMCCodeEmitter::
1082
getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1083
                        SmallVectorImpl<MCFixup> &Fixups,
1084
140
                        const MCSubtargetInfo &STI) const {
1085
140
    // {10-8} Qm
1086
140
    // {7-0} Imm
1087
140
    const MCOperand &M0 = MI.getOperand(OpIdx);
1088
140
    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1089
140
1090
140
    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1091
140
    int32_t Imm = M1.getImm();
1092
140
1093
140
    bool isAdd = Imm >= 0;
1094
140
1095
140
    Imm >>= shift;
1096
140
1097
140
    if (!isAdd)
1098
27
      Imm = -(uint32_t)Imm;
1099
140
1100
140
    Imm &= 0x7f;
1101
140
1102
140
    if (isAdd)
1103
113
      Imm |= 0x80;
1104
140
1105
140
    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1106
140
1107
140
    return (Qm << 8) | Imm;
1108
140
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getMveAddrModeQOpValue<2>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1084
66
                        const MCSubtargetInfo &STI) const {
1085
66
    // {10-8} Qm
1086
66
    // {7-0} Imm
1087
66
    const MCOperand &M0 = MI.getOperand(OpIdx);
1088
66
    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1089
66
1090
66
    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1091
66
    int32_t Imm = M1.getImm();
1092
66
1093
66
    bool isAdd = Imm >= 0;
1094
66
1095
66
    Imm >>= shift;
1096
66
1097
66
    if (!isAdd)
1098
10
      Imm = -(uint32_t)Imm;
1099
66
1100
66
    Imm &= 0x7f;
1101
66
1102
66
    if (isAdd)
1103
56
      Imm |= 0x80;
1104
66
1105
66
    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1106
66
1107
66
    return (Qm << 8) | Imm;
1108
66
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getMveAddrModeQOpValue<3>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1084
74
                        const MCSubtargetInfo &STI) const {
1085
74
    // {10-8} Qm
1086
74
    // {7-0} Imm
1087
74
    const MCOperand &M0 = MI.getOperand(OpIdx);
1088
74
    const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1089
74
1090
74
    unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1091
74
    int32_t Imm = M1.getImm();
1092
74
1093
74
    bool isAdd = Imm >= 0;
1094
74
1095
74
    Imm >>= shift;
1096
74
1097
74
    if (!isAdd)
1098
17
      Imm = -(uint32_t)Imm;
1099
74
1100
74
    Imm &= 0x7f;
1101
74
1102
74
    if (isAdd)
1103
57
      Imm |= 0x80;
1104
74
1105
74
    assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1106
74
1107
74
    return (Qm << 8) | Imm;
1108
74
}
1109
1110
/// getT2AddrModeImm8s4OpValue - Return encoding info for
1111
/// 'reg +/- imm8<<2' operand.
1112
uint32_t ARMMCCodeEmitter::
1113
getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1114
                        SmallVectorImpl<MCFixup> &Fixups,
1115
20.2k
                        const MCSubtargetInfo &STI) const {
1116
20.2k
  // {12-9} = reg
1117
20.2k
  // {8}    = (U)nsigned (add == '1', sub == '0')
1118
20.2k
  // {7-0}  = imm8
1119
20.2k
  unsigned Reg, Imm8;
1120
20.2k
  bool isAdd = true;
1121
20.2k
  // If The first operand isn't a register, we have a label reference.
1122
20.2k
  const MCOperand &MO = MI.getOperand(OpIdx);
1123
20.2k
  if (!MO.isReg()) {
1124
0
    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1125
0
    Imm8 = 0;
1126
0
    isAdd = false ; // 'U' bit is set as part of the fixup.
1127
0
1128
0
    assert(MO.isExpr() && "Unexpected machine operand type!");
1129
0
    const MCExpr *Expr = MO.getExpr();
1130
0
    MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1131
0
    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1132
0
1133
0
    ++MCNumCPRelocations;
1134
0
  } else
1135
20.2k
    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1136
20.2k
1137
20.2k
  // FIXME: The immediate operand should have already been encoded like this
1138
20.2k
  // before ever getting here. The encoder method should just need to combine
1139
20.2k
  // the MI operands for the register and the offset into a single
1140
20.2k
  // representation for the complex operand in the .td file. This isn't just
1141
20.2k
  // style, unfortunately. As-is, we can't represent the distinct encoding
1142
20.2k
  // for #-0.
1143
20.2k
  uint32_t Binary = (Imm8 >> 2) & 0xff;
1144
20.2k
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1145
20.2k
  if (isAdd)
1146
20.0k
    Binary |= (1 << 8);
1147
20.2k
  Binary |= (Reg << 9);
1148
20.2k
  return Binary;
1149
20.2k
}
1150
1151
/// getT2AddrModeImm7s4OpValue - Return encoding info for
1152
/// 'reg +/- imm7<<2' operand.
1153
uint32_t
1154
ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1155
                                             SmallVectorImpl<MCFixup> &Fixups,
1156
200
                                             const MCSubtargetInfo &STI) const {
1157
200
  // {11-8} = reg
1158
200
  // {7}    = (A)dd (add == '1', sub == '0')
1159
200
  // {6-0}  = imm7
1160
200
  unsigned Reg, Imm7;
1161
200
  // If The first operand isn't a register, we have a label reference.
1162
200
  bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1163
200
1164
200
  // FIXME: The immediate operand should have already been encoded like this
1165
200
  // before ever getting here. The encoder method should just need to combine
1166
200
  // the MI operands for the register and the offset into a single
1167
200
  // representation for the complex operand in the .td file. This isn't just
1168
200
  // style, unfortunately. As-is, we can't represent the distinct encoding
1169
200
  // for #-0.
1170
200
  uint32_t Binary = (Imm7 >> 2) & 0xff;
1171
200
  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1172
200
  if (isAdd)
1173
120
    Binary |= (1 << 7);
1174
200
  Binary |= (Reg << 8);
1175
200
  return Binary;
1176
200
}
1177
1178
/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1179
/// 'reg + imm8<<2' operand.
1180
uint32_t ARMMCCodeEmitter::
1181
getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1182
                        SmallVectorImpl<MCFixup> &Fixups,
1183
825
                        const MCSubtargetInfo &STI) const {
1184
825
  // {11-8} = reg
1185
825
  // {7-0}  = imm8
1186
825
  const MCOperand &MO = MI.getOperand(OpIdx);
1187
825
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1188
825
  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1189
825
  unsigned Imm8 = MO1.getImm();
1190
825
  return (Reg << 8) | Imm8;
1191
825
}
1192
1193
uint32_t
1194
ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1195
                                      SmallVectorImpl<MCFixup> &Fixups,
1196
58.3k
                                      const MCSubtargetInfo &STI) const {
1197
58.3k
  // {20-16} = imm{15-12}
1198
58.3k
  // {11-0}  = imm{11-0}
1199
58.3k
  const MCOperand &MO = MI.getOperand(OpIdx);
1200
58.3k
  if (MO.isImm())
1201
5.03k
    // Hi / lo 16 bits already extracted during earlier passes.
1202
5.03k
    return static_cast<unsigned>(MO.getImm());
1203
53.3k
1204
53.3k
  // Handle :upper16: and :lower16: assembly prefixes.
1205
53.3k
  const MCExpr *E = MO.getExpr();
1206
53.3k
  MCFixupKind Kind;
1207
53.3k
  if (E->getKind() == MCExpr::Target) {
1208
53.3k
    const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1209
53.3k
    E = ARM16Expr->getSubExpr();
1210
53.3k
1211
53.3k
    if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1212
12
      const int64_t Value = MCE->getValue();
1213
12
      if (Value > UINT32_MAX)
1214
12
        
report_fatal_error("constant value truncated (limited to 32-bit)")0
;
1215
12
1216
12
      switch (ARM16Expr->getKind()) {
1217
12
      case ARMMCExpr::VK_ARM_HI16:
1218
6
        return (int32_t(Value) & 0xffff0000) >> 16;
1219
12
      case ARMMCExpr::VK_ARM_LO16:
1220
6
        return (int32_t(Value) & 0x0000ffff);
1221
12
      
default: 0
llvm_unreachable0
("Unsupported ARMFixup");
1222
53.3k
      }
1223
53.3k
    }
1224
53.3k
1225
53.3k
    switch (ARM16Expr->getKind()) {
1226
53.3k
    
default: 0
llvm_unreachable0
("Unsupported ARMFixup");
1227
53.3k
    case ARMMCExpr::VK_ARM_HI16:
1228
26.6k
      Kind = MCFixupKind(isThumb(STI) ? 
ARM::fixup_t2_movt_hi1626.6k
1229
26.6k
                                      : 
ARM::fixup_arm_movt_hi1638
);
1230
26.6k
      break;
1231
53.3k
    case ARMMCExpr::VK_ARM_LO16:
1232
26.6k
      Kind = MCFixupKind(isThumb(STI) ? 
ARM::fixup_t2_movw_lo1626.6k
1233
26.6k
                                      : 
ARM::fixup_arm_movw_lo1645
);
1234
26.6k
      break;
1235
53.3k
    }
1236
53.3k
1237
53.3k
    Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1238
53.3k
    return 0;
1239
53.3k
  }
1240
0
  // If the expression doesn't have :upper16: or :lower16: on it,
1241
0
  // it's just a plain immediate expression, previously those evaluated to
1242
0
  // the lower 16 bits of the expression regardless of whether
1243
0
  // we have a movt or a movw, but that led to misleadingly results.
1244
0
  // This is disallowed in the AsmParser in validateInstruction()
1245
0
  // so this should never happen.
1246
0
  llvm_unreachable("expression without :upper16: or :lower16:");
1247
0
}
1248
1249
uint32_t ARMMCCodeEmitter::
1250
getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1251
                    SmallVectorImpl<MCFixup> &Fixups,
1252
66
                    const MCSubtargetInfo &STI) const {
1253
66
  const MCOperand &MO = MI.getOperand(OpIdx);
1254
66
  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1255
66
  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1256
66
  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1257
66
  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1258
66
  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1259
66
  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1260
66
  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1261
66
  unsigned SBits = getShiftOp(ShOp);
1262
66
1263
66
  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1264
66
  // amount. However, it would be an easy mistake to make so check here.
1265
66
  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1266
66
1267
66
  // {16-13} = Rn
1268
66
  // {12}    = isAdd
1269
66
  // {11-0}  = shifter
1270
66
  //  {3-0}  = Rm
1271
66
  //  {4}    = 0
1272
66
  //  {6-5}  = type
1273
66
  //  {11-7} = imm
1274
66
  uint32_t Binary = Rm;
1275
66
  Binary |= Rn << 13;
1276
66
  Binary |= SBits << 5;
1277
66
  Binary |= ShImm << 7;
1278
66
  if (isAdd)
1279
54
    Binary |= 1 << 12;
1280
66
  return Binary;
1281
66
}
1282
1283
uint32_t ARMMCCodeEmitter::
1284
getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1285
                          SmallVectorImpl<MCFixup> &Fixups,
1286
1.53k
                          const MCSubtargetInfo &STI) const {
1287
1.53k
  // {13}     1 == imm12, 0 == Rm
1288
1.53k
  // {12}     isAdd
1289
1.53k
  // {11-0}   imm12/Rm
1290
1.53k
  const MCOperand &MO = MI.getOperand(OpIdx);
1291
1.53k
  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1292
1.53k
  unsigned Imm = MO1.getImm();
1293
1.53k
  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1294
1.53k
  bool isReg = MO.getReg() != 0;
1295
1.53k
  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1296
1.53k
  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1297
1.53k
  if (isReg) {
1298
28
    ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1299
28
    Binary <<= 7;                    // Shift amount is bits [11:7]
1300
28
    Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1301
28
    Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1302
28
  }
1303
1.53k
  return Binary | (isAdd << 12) | (isReg << 13);
1304
1.53k
}
1305
1306
uint32_t ARMMCCodeEmitter::
1307
getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1308
                     SmallVectorImpl<MCFixup> &Fixups,
1309
12
                     const MCSubtargetInfo &STI) const {
1310
12
  // {4}      isAdd
1311
12
  // {3-0}    Rm
1312
12
  const MCOperand &MO = MI.getOperand(OpIdx);
1313
12
  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1314
12
  bool isAdd = MO1.getImm() != 0;
1315
12
  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1316
12
}
1317
1318
uint32_t ARMMCCodeEmitter::
1319
getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1320
                          SmallVectorImpl<MCFixup> &Fixups,
1321
358
                          const MCSubtargetInfo &STI) const {
1322
358
  // {9}      1 == imm8, 0 == Rm
1323
358
  // {8}      isAdd
1324
358
  // {7-4}    imm7_4/zero
1325
358
  // {3-0}    imm3_0/Rm
1326
358
  const MCOperand &MO = MI.getOperand(OpIdx);
1327
358
  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1328
358
  unsigned Imm = MO1.getImm();
1329
358
  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1330
358
  bool isImm = MO.getReg() == 0;
1331
358
  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1332
358
  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1333
358
  if (!isImm)
1334
12
    Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1335
358
  return Imm8 | (isAdd << 8) | (isImm << 9);
1336
358
}
1337
1338
uint32_t ARMMCCodeEmitter::
1339
getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1340
                    SmallVectorImpl<MCFixup> &Fixups,
1341
55
                    const MCSubtargetInfo &STI) const {
1342
55
  // {13}     1 == imm8, 0 == Rm
1343
55
  // {12-9}   Rn
1344
55
  // {8}      isAdd
1345
55
  // {7-4}    imm7_4/zero
1346
55
  // {3-0}    imm3_0/Rm
1347
55
  const MCOperand &MO = MI.getOperand(OpIdx);
1348
55
  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1349
55
  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1350
55
1351
55
  // If The first operand isn't a register, we have a label reference.
1352
55
  if (!MO.isReg()) {
1353
2
    unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1354
2
1355
2
    assert(MO.isExpr() && "Unexpected machine operand type!");
1356
2
    const MCExpr *Expr = MO.getExpr();
1357
2
    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1358
2
    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1359
2
1360
2
    ++MCNumCPRelocations;
1361
2
    return (Rn << 9) | (1 << 13);
1362
2
  }
1363
53
  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1364
53
  unsigned Imm = MO2.getImm();
1365
53
  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1366
53
  bool isImm = MO1.getReg() == 0;
1367
53
  uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1368
53
  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1369
53
  if (!isImm)
1370
17
    Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1371
53
  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1372
53
}
1373
1374
/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1375
uint32_t ARMMCCodeEmitter::
1376
getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1377
                          SmallVectorImpl<MCFixup> &Fixups,
1378
22.7k
                          const MCSubtargetInfo &STI) const {
1379
22.7k
  // [SP, #imm]
1380
22.7k
  //   {7-0} = imm8
1381
22.7k
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1382
22.7k
  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1383
22.7k
         "Unexpected base register!");
1384
22.7k
1385
22.7k
  // The immediate is already shifted for the implicit zeroes, so no change
1386
22.7k
  // here.
1387
22.7k
  return MO1.getImm() & 0xff;
1388
22.7k
}
1389
1390
/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1391
uint32_t ARMMCCodeEmitter::
1392
getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1393
                     SmallVectorImpl<MCFixup> &Fixups,
1394
33.8k
                     const MCSubtargetInfo &STI) const {
1395
33.8k
  // [Rn, #imm]
1396
33.8k
  //   {7-3} = imm5
1397
33.8k
  //   {2-0} = Rn
1398
33.8k
  const MCOperand &MO = MI.getOperand(OpIdx);
1399
33.8k
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1400
33.8k
  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1401
33.8k
  unsigned Imm5 = MO1.getImm();
1402
33.8k
  return ((Imm5 & 0x1f) << 3) | Rn;
1403
33.8k
}
1404
1405
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1406
uint32_t ARMMCCodeEmitter::
1407
getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1408
                     SmallVectorImpl<MCFixup> &Fixups,
1409
2.01k
                     const MCSubtargetInfo &STI) const {
1410
2.01k
  const MCOperand MO = MI.getOperand(OpIdx);
1411
2.01k
  if (MO.isExpr())
1412
2.00k
    return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1413
16
  return (MO.getImm() >> 2);
1414
16
}
1415
1416
/// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1417
uint32_t ARMMCCodeEmitter::
1418
getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1419
                    SmallVectorImpl<MCFixup> &Fixups,
1420
1.28k
                    const MCSubtargetInfo &STI) const {
1421
1.28k
  // {12-9} = reg
1422
1.28k
  // {8}    = (U)nsigned (add == '1', sub == '0')
1423
1.28k
  // {7-0}  = imm8
1424
1.28k
  unsigned Reg, Imm8;
1425
1.28k
  bool isAdd;
1426
1.28k
  // If The first operand isn't a register, we have a label reference.
1427
1.28k
  const MCOperand &MO = MI.getOperand(OpIdx);
1428
1.28k
  if (!MO.isReg()) {
1429
497
    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1430
497
    Imm8 = 0;
1431
497
    isAdd = false; // 'U' bit is handled as part of the fixup.
1432
497
1433
497
    assert(MO.isExpr() && "Unexpected machine operand type!");
1434
497
    const MCExpr *Expr = MO.getExpr();
1435
497
    MCFixupKind Kind;
1436
497
    if (isThumb2(STI))
1437
424
      Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1438
73
    else
1439
73
      Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1440
497
    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1441
497
1442
497
    ++MCNumCPRelocations;
1443
789
  } else {
1444
789
    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1445
789
    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1446
789
  }
1447
1.28k
1448
1.28k
  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1449
1.28k
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1450
1.28k
  if (isAdd)
1451
571
    Binary |= (1 << 8);
1452
1.28k
  Binary |= (Reg << 9);
1453
1.28k
  return Binary;
1454
1.28k
}
1455
1456
/// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1457
uint32_t ARMMCCodeEmitter::
1458
getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1459
                    SmallVectorImpl<MCFixup> &Fixups,
1460
60
                    const MCSubtargetInfo &STI) const {
1461
60
  // {12-9} = reg
1462
60
  // {8}    = (U)nsigned (add == '1', sub == '0')
1463
60
  // {7-0}  = imm8
1464
60
  unsigned Reg, Imm8;
1465
60
  bool isAdd;
1466
60
  // If The first operand isn't a register, we have a label reference.
1467
60
  const MCOperand &MO = MI.getOperand(OpIdx);
1468
60
  if (!MO.isReg()) {
1469
2
    Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1470
2
    Imm8 = 0;
1471
2
    isAdd = false; // 'U' bit is handled as part of the fixup.
1472
2
1473
2
    assert(MO.isExpr() && "Unexpected machine operand type!");
1474
2
    const MCExpr *Expr = MO.getExpr();
1475
2
    MCFixupKind Kind;
1476
2
    if (isThumb2(STI))
1477
0
      Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1478
2
    else
1479
2
      Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1480
2
    Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1481
2
1482
2
    ++MCNumCPRelocations;
1483
58
  } else {
1484
58
    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1485
58
    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1486
58
  }
1487
60
1488
60
  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1489
60
  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1490
60
  if (isAdd)
1491
34
    Binary |= (1 << 8);
1492
60
  Binary |= (Reg << 9);
1493
60
  return Binary;
1494
60
}
1495
1496
unsigned ARMMCCodeEmitter::
1497
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1498
                SmallVectorImpl<MCFixup> &Fixups,
1499
211
                const MCSubtargetInfo &STI) const {
1500
211
  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1501
211
  // shifted. The second is Rs, the amount to shift by, and the third specifies
1502
211
  // the type of the shift.
1503
211
  //
1504
211
  // {3-0} = Rm.
1505
211
  // {4}   = 1
1506
211
  // {6-5} = type
1507
211
  // {11-8} = Rs
1508
211
  // {7}    = 0
1509
211
1510
211
  const MCOperand &MO  = MI.getOperand(OpIdx);
1511
211
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1512
211
  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1513
211
  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1514
211
1515
211
  // Encode Rm.
1516
211
  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1517
211
1518
211
  // Encode the shift opcode.
1519
211
  unsigned SBits = 0;
1520
211
  unsigned Rs = MO1.getReg();
1521
211
  if (Rs) {
1522
211
    // Set shift operand (bit[7:4]).
1523
211
    // LSL - 0001
1524
211
    // LSR - 0011
1525
211
    // ASR - 0101
1526
211
    // ROR - 0111
1527
211
    switch (SOpc) {
1528
211
    
default: 0
llvm_unreachable0
("Unknown shift opc!");
1529
211
    
case ARM_AM::lsl: SBits = 0x1; break55
;
1530
211
    
case ARM_AM::lsr: SBits = 0x3; break50
;
1531
211
    
case ARM_AM::asr: SBits = 0x5; break52
;
1532
211
    
case ARM_AM::ror: SBits = 0x7; break54
;
1533
211
    }
1534
211
  }
1535
211
1536
211
  Binary |= SBits << 4;
1537
211
1538
211
  // Encode the shift operation Rs.
1539
211
  // Encode Rs bit[11:8].
1540
211
  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1541
211
  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1542
211
}
1543
1544
unsigned ARMMCCodeEmitter::
1545
getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1546
                SmallVectorImpl<MCFixup> &Fixups,
1547
398
                const MCSubtargetInfo &STI) const {
1548
398
  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1549
398
  // shifted. The second is the amount to shift by.
1550
398
  //
1551
398
  // {3-0} = Rm.
1552
398
  // {4}   = 0
1553
398
  // {6-5} = type
1554
398
  // {11-7} = imm
1555
398
1556
398
  const MCOperand &MO  = MI.getOperand(OpIdx);
1557
398
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1558
398
  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1559
398
1560
398
  // Encode Rm.
1561
398
  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1562
398
1563
398
  // Encode the shift opcode.
1564
398
  unsigned SBits = 0;
1565
398
1566
398
  // Set shift operand (bit[6:4]).
1567
398
  // LSL - 000
1568
398
  // LSR - 010
1569
398
  // ASR - 100
1570
398
  // ROR - 110
1571
398
  // RRX - 110 and bit[11:8] clear.
1572
398
  switch (SOpc) {
1573
398
  
default: 0
llvm_unreachable0
("Unknown shift opc!");
1574
398
  
case ARM_AM::lsl: SBits = 0x0; break73
;
1575
398
  
case ARM_AM::lsr: SBits = 0x2; break124
;
1576
398
  
case ARM_AM::asr: SBits = 0x4; break80
;
1577
398
  
case ARM_AM::ror: SBits = 0x6; break63
;
1578
398
  case ARM_AM::rrx:
1579
58
    Binary |= 0x60;
1580
58
    return Binary;
1581
340
  }
1582
340
1583
340
  // Encode shift_imm bit[11:7].
1584
340
  Binary |= SBits << 4;
1585
340
  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1586
340
  assert(Offset < 32 && "Offset must be in range 0-31!");
1587
340
  return Binary | (Offset << 7);
1588
340
}
1589
1590
1591
unsigned ARMMCCodeEmitter::
1592
getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1593
                SmallVectorImpl<MCFixup> &Fixups,
1594
2.47k
                const MCSubtargetInfo &STI) const {
1595
2.47k
  const MCOperand &MO1 = MI.getOperand(OpNum);
1596
2.47k
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1597
2.47k
  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1598
2.47k
1599
2.47k
  // Encoded as [Rn, Rm, imm].
1600
2.47k
  // FIXME: Needs fixup support.
1601
2.47k
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1602
2.47k
  Value <<= 4;
1603
2.47k
  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1604
2.47k
  Value <<= 2;
1605
2.47k
  Value |= MO3.getImm();
1606
2.47k
1607
2.47k
  return Value;
1608
2.47k
}
1609
1610
template<unsigned Bits, unsigned Shift>
1611
unsigned ARMMCCodeEmitter::
1612
getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1613
                        SmallVectorImpl<MCFixup> &Fixups,
1614
3.39k
                        const MCSubtargetInfo &STI) const {
1615
3.39k
  const MCOperand &MO1 = MI.getOperand(OpNum);
1616
3.39k
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617
3.39k
1618
3.39k
  // FIXME: Needs fixup support.
1619
3.39k
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620
3.39k
1621
3.39k
  // If the immediate is B bits long, we need B+1 bits in order
1622
3.39k
  // to represent the (inverse of the) sign bit.
1623
3.39k
  Value <<= (Bits + 1);
1624
3.39k
  int32_t tmp = (int32_t)MO2.getImm();
1625
3.39k
  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626
19
    tmp = 0;
1627
3.37k
  } else if (tmp < 0) {
1628
2.36k
    tmp = abs(tmp);
1629
2.36k
  } else {
1630
1.01k
    Value |= (1U << Bits); // Set the ADD bit
1631
1.01k
  }
1632
3.39k
  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633
3.39k
  return Value;
1634
3.39k
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2AddrModeImmOpValue<7u, 0u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1614
204
                        const MCSubtargetInfo &STI) const {
1615
204
  const MCOperand &MO1 = MI.getOperand(OpNum);
1616
204
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617
204
1618
204
  // FIXME: Needs fixup support.
1619
204
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620
204
1621
204
  // If the immediate is B bits long, we need B+1 bits in order
1622
204
  // to represent the (inverse of the) sign bit.
1623
204
  Value <<= (Bits + 1);
1624
204
  int32_t tmp = (int32_t)MO2.getImm();
1625
204
  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626
8
    tmp = 0;
1627
196
  } else if (tmp < 0) {
1628
31
    tmp = abs(tmp);
1629
165
  } else {
1630
165
    Value |= (1U << Bits); // Set the ADD bit
1631
165
  }
1632
204
  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633
204
  return Value;
1634
204
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2AddrModeImmOpValue<7u, 1u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1614
154
                        const MCSubtargetInfo &STI) const {
1615
154
  const MCOperand &MO1 = MI.getOperand(OpNum);
1616
154
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617
154
1618
154
  // FIXME: Needs fixup support.
1619
154
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620
154
1621
154
  // If the immediate is B bits long, we need B+1 bits in order
1622
154
  // to represent the (inverse of the) sign bit.
1623
154
  Value <<= (Bits + 1);
1624
154
  int32_t tmp = (int32_t)MO2.getImm();
1625
154
  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626
5
    tmp = 0;
1627
149
  } else if (tmp < 0) {
1628
30
    tmp = abs(tmp);
1629
119
  } else {
1630
119
    Value |= (1U << Bits); // Set the ADD bit
1631
119
  }
1632
154
  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633
154
  return Value;
1634
154
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2AddrModeImmOpValue<7u, 2u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1614
76
                        const MCSubtargetInfo &STI) const {
1615
76
  const MCOperand &MO1 = MI.getOperand(OpNum);
1616
76
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617
76
1618
76
  // FIXME: Needs fixup support.
1619
76
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620
76
1621
76
  // If the immediate is B bits long, we need B+1 bits in order
1622
76
  // to represent the (inverse of the) sign bit.
1623
76
  Value <<= (Bits + 1);
1624
76
  int32_t tmp = (int32_t)MO2.getImm();
1625
76
  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626
2
    tmp = 0;
1627
74
  } else if (tmp < 0) {
1628
12
    tmp = abs(tmp);
1629
62
  } else {
1630
62
    Value |= (1U << Bits); // Set the ADD bit
1631
62
  }
1632
76
  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633
76
  return Value;
1634
76
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getT2AddrModeImmOpValue<8u, 0u>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1614
2.96k
                        const MCSubtargetInfo &STI) const {
1615
2.96k
  const MCOperand &MO1 = MI.getOperand(OpNum);
1616
2.96k
  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1617
2.96k
1618
2.96k
  // FIXME: Needs fixup support.
1619
2.96k
  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1620
2.96k
1621
2.96k
  // If the immediate is B bits long, we need B+1 bits in order
1622
2.96k
  // to represent the (inverse of the) sign bit.
1623
2.96k
  Value <<= (Bits + 1);
1624
2.96k
  int32_t tmp = (int32_t)MO2.getImm();
1625
2.96k
  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1626
4
    tmp = 0;
1627
2.95k
  } else if (tmp < 0) {
1628
2.28k
    tmp = abs(tmp);
1629
2.28k
  } else {
1630
672
    Value |= (1U << Bits); // Set the ADD bit
1631
672
  }
1632
2.96k
  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1633
2.96k
  return Value;
1634
2.96k
}
1635
1636
unsigned ARMMCCodeEmitter::
1637
getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1638
                         SmallVectorImpl<MCFixup> &Fixups,
1639
3.41k
                         const MCSubtargetInfo &STI) const {
1640
3.41k
  const MCOperand &MO1 = MI.getOperand(OpNum);
1641
3.41k
1642
3.41k
  // FIXME: Needs fixup support.
1643
3.41k
  unsigned Value = 0;
1644
3.41k
  int32_t tmp = (int32_t)MO1.getImm();
1645
3.41k
  if (tmp < 0)
1646
18
    tmp = abs(tmp);
1647
3.39k
  else
1648
3.39k
    Value |= 256; // Set the ADD bit
1649
3.41k
  Value |= tmp & 255;
1650
3.41k
  return Value;
1651
3.41k
}
1652
1653
unsigned ARMMCCodeEmitter::
1654
getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1655
                SmallVectorImpl<MCFixup> &Fixups,
1656
8.33k
                const MCSubtargetInfo &STI) const {
1657
8.33k
  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1658
8.33k
  // shifted. The second is the amount to shift by.
1659
8.33k
  //
1660
8.33k
  // {3-0} = Rm.
1661
8.33k
  // {4}   = 0
1662
8.33k
  // {6-5} = type
1663
8.33k
  // {11-7} = imm
1664
8.33k
1665
8.33k
  const MCOperand &MO  = MI.getOperand(OpIdx);
1666
8.33k
  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1667
8.33k
  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1668
8.33k
1669
8.33k
  // Encode Rm.
1670
8.33k
  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1671
8.33k
1672
8.33k
  // Encode the shift opcode.
1673
8.33k
  unsigned SBits = 0;
1674
8.33k
  // Set shift operand (bit[6:4]).
1675
8.33k
  // LSL - 000
1676
8.33k
  // LSR - 010
1677
8.33k
  // ASR - 100
1678
8.33k
  // ROR - 110
1679
8.33k
  switch (SOpc) {
1680
8.33k
  
default: 0
llvm_unreachable0
("Unknown shift opc!");
1681
8.33k
  
case ARM_AM::lsl: SBits = 0x0; break4.83k
;
1682
8.33k
  
case ARM_AM::lsr: SBits = 0x2; break2.54k
;
1683
8.33k
  
case ARM_AM::asr: SBits = 0x4; break919
;
1684
8.33k
  
case ARM_AM::rrx: 6
LLVM_FALLTHROUGH6
;
1685
39
  case ARM_AM::ror: SBits = 0x6; break;
1686
8.33k
  }
1687
8.33k
1688
8.33k
  Binary |= SBits << 4;
1689
8.33k
  if (SOpc == ARM_AM::rrx)
1690
6
    return Binary;
1691
8.32k
1692
8.32k
  // Encode shift_imm bit[11:7].
1693
8.32k
  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1694
8.32k
}
1695
1696
unsigned ARMMCCodeEmitter::
1697
getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1698
                               SmallVectorImpl<MCFixup> &Fixups,
1699
1.02k
                               const MCSubtargetInfo &STI) const {
1700
1.02k
  // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1701
1.02k
  // msb of the mask.
1702
1.02k
  const MCOperand &MO = MI.getOperand(Op);
1703
1.02k
  uint32_t v = ~MO.getImm();
1704
1.02k
  uint32_t lsb = countTrailingZeros(v);
1705
1.02k
  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1706
1.02k
  assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1707
1.02k
  return lsb | (msb << 5);
1708
1.02k
}
1709
1710
unsigned ARMMCCodeEmitter::
1711
getRegisterListOpValue(const MCInst &MI, unsigned Op,
1712
                       SmallVectorImpl<MCFixup> &Fixups,
1713
25.1k
                       const MCSubtargetInfo &STI) const {
1714
25.1k
  // VLDM/VSTM/VSCCLRM:
1715
25.1k
  //   {12-8} = Vd
1716
25.1k
  //   {7-0}  = Number of registers
1717
25.1k
  //
1718
25.1k
  // LDM/STM:
1719
25.1k
  //   {15-0}  = Bitfield of GPRs.
1720
25.1k
  unsigned Reg = MI.getOperand(Op).getReg();
1721
25.1k
  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1722
25.1k
  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1723
25.1k
  bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
1724
25.1k
1725
25.1k
  unsigned Binary = 0;
1726
25.1k
1727
25.1k
  if (SPRRegs || 
DPRRegs25.1k
) {
1728
332
    // VLDM/VSTM/VSCCLRM
1729
332
    unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1730
332
    unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1731
332
    Binary |= (RegNo & 0x1f) << 8;
1732
332
1733
332
    // Ignore VPR
1734
332
    if (MI.getOpcode() == ARM::VSCCLRMD || 
MI.getOpcode() == ARM::VSCCLRMS328
)
1735
14
      --NumRegs;
1736
332
    if (SPRRegs)
1737
76
      Binary |= NumRegs;
1738
256
    else
1739
256
      Binary |= NumRegs * 2;
1740
24.8k
  } else {
1741
24.8k
    const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1742
24.8k
    if (!CLRMRegs) {
1743
24.8k
      assert(std::is_sorted(MI.begin() + Op, MI.end(),
1744
24.8k
                            [&](const MCOperand &LHS, const MCOperand &RHS) {
1745
24.8k
                              return MRI.getEncodingValue(LHS.getReg()) <
1746
24.8k
                                     MRI.getEncodingValue(RHS.getReg());
1747
24.8k
                            }));
1748
24.8k
    }
1749
24.8k
1750
119k
    for (unsigned I = Op, E = MI.getNumOperands(); I < E; 
++I94.9k
) {
1751
94.9k
      unsigned RegNo;
1752
94.9k
      if (CLRMRegs && 
MI.getOperand(I).getReg() == ARM::APSR54
) {
1753
5
        RegNo = 15;
1754
94.9k
      } else {
1755
94.9k
        RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1756
94.9k
      }
1757
94.9k
      Binary |= 1 << RegNo;
1758
94.9k
    }
1759
24.8k
  }
1760
25.1k
1761
25.1k
  return Binary;
1762
25.1k
}
1763
1764
/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1765
/// with the alignment operand.
1766
unsigned ARMMCCodeEmitter::
1767
getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1768
                           SmallVectorImpl<MCFixup> &Fixups,
1769
3.51k
                           const MCSubtargetInfo &STI) const {
1770
3.51k
  const MCOperand &Reg = MI.getOperand(Op);
1771
3.51k
  const MCOperand &Imm = MI.getOperand(Op + 1);
1772
3.51k
1773
3.51k
  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1774
3.51k
  unsigned Align = 0;
1775
3.51k
1776
3.51k
  switch (Imm.getImm()) {
1777
3.51k
  
default: break2.45k
;
1778
3.51k
  case 2:
1779
398
  case 4:
1780
398
  case 8:  Align = 0x01; break;
1781
568
  case 16: Align = 0x02; break;
1782
398
  
case 32: Align = 0x03; break97
;
1783
3.51k
  }
1784
3.51k
1785
3.51k
  return RegNo | (Align << 4);
1786
3.51k
}
1787
1788
/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1789
/// along  with the alignment operand for use in VST1 and VLD1 with size 32.
1790
unsigned ARMMCCodeEmitter::
1791
getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1792
                                    SmallVectorImpl<MCFixup> &Fixups,
1793
59
                                    const MCSubtargetInfo &STI) const {
1794
59
  const MCOperand &Reg = MI.getOperand(Op);
1795
59
  const MCOperand &Imm = MI.getOperand(Op + 1);
1796
59
1797
59
  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1798
59
  unsigned Align = 0;
1799
59
1800
59
  switch (Imm.getImm()) {
1801
59
  
default: break7
;
1802
59
  case 8:
1803
0
  case 16:
1804
0
  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1805
0
  case 2: Align = 0x00; break;
1806
52
  case 4: Align = 0x03; break;
1807
59
  }
1808
59
1809
59
  return RegNo | (Align << 4);
1810
59
}
1811
1812
1813
/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1814
/// alignment operand for use in VLD-dup instructions.  This is the same as
1815
/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1816
/// different for VLD4-dup.
1817
unsigned ARMMCCodeEmitter::
1818
getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1819
                              SmallVectorImpl<MCFixup> &Fixups,
1820
174
                              const MCSubtargetInfo &STI) const {
1821
174
  const MCOperand &Reg = MI.getOperand(Op);
1822
174
  const MCOperand &Imm = MI.getOperand(Op + 1);
1823
174
1824
174
  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1825
174
  unsigned Align = 0;
1826
174
1827
174
  switch (Imm.getImm()) {
1828
174
  
default: break120
;
1829
174
  case 2:
1830
48
  case 4:
1831
48
  case 8:  Align = 0x01; break;
1832
48
  
case 16: Align = 0x03; break6
;
1833
174
  }
1834
174
1835
174
  return RegNo | (Align << 4);
1836
174
}
1837
1838
unsigned ARMMCCodeEmitter::
1839
getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1840
                          SmallVectorImpl<MCFixup> &Fixups,
1841
529
                          const MCSubtargetInfo &STI) const {
1842
529
  const MCOperand &MO = MI.getOperand(Op);
1843
529
  if (MO.getReg() == 0) 
return 0x0D252
;
1844
277
  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1845
277
}
1846
1847
unsigned ARMMCCodeEmitter::
1848
getShiftRight8Imm(const MCInst &MI, unsigned Op,
1849
                  SmallVectorImpl<MCFixup> &Fixups,
1850
155
                  const MCSubtargetInfo &STI) const {
1851
155
  return 8 - MI.getOperand(Op).getImm();
1852
155
}
1853
1854
unsigned ARMMCCodeEmitter::
1855
getShiftRight16Imm(const MCInst &MI, unsigned Op,
1856
                   SmallVectorImpl<MCFixup> &Fixups,
1857
149
                   const MCSubtargetInfo &STI) const {
1858
149
  return 16 - MI.getOperand(Op).getImm();
1859
149
}
1860
1861
unsigned ARMMCCodeEmitter::
1862
getShiftRight32Imm(const MCInst &MI, unsigned Op,
1863
                   SmallVectorImpl<MCFixup> &Fixups,
1864
113
                   const MCSubtargetInfo &STI) const {
1865
113
  return 32 - MI.getOperand(Op).getImm();
1866
113
}
1867
1868
unsigned ARMMCCodeEmitter::
1869
getShiftRight64Imm(const MCInst &MI, unsigned Op,
1870
                   SmallVectorImpl<MCFixup> &Fixups,
1871
80
                   const MCSubtargetInfo &STI) const {
1872
80
  return 64 - MI.getOperand(Op).getImm();
1873
80
}
1874
1875
void ARMMCCodeEmitter::
1876
encodeInstruction(const MCInst &MI, raw_ostream &OS,
1877
                  SmallVectorImpl<MCFixup> &Fixups,
1878
635k
                  const MCSubtargetInfo &STI) const {
1879
635k
  // Pseudo instructions don't get encoded.
1880
635k
  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1881
635k
  uint64_t TSFlags = Desc.TSFlags;
1882
635k
  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1883
73
    return;
1884
635k
1885
635k
  int Size;
1886
635k
  if (Desc.getSize() == 2 || 
Desc.getSize() == 4269k
)
1887
635k
    Size = Desc.getSize();
1888
635k
  else
1889
635k
    
llvm_unreachable0
("Unexpected instruction size!");
1890
635k
1891
635k
  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1892
635k
  // Thumb 32-bit wide instructions need to emit the high order halfword
1893
635k
  // first.
1894
635k
  if (isThumb(STI) && 
Size == 4619k
) {
1895
253k
    EmitConstant(Binary >> 16, 2, OS);
1896
253k
    EmitConstant(Binary & 0xffff, 2, OS);
1897
253k
  } else
1898
382k
    EmitConstant(Binary, Size, OS);
1899
635k
  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
1900
635k
}
1901
1902
template <bool isNeg, ARM::Fixups fixup>
1903
uint32_t
1904
ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1905
                                     SmallVectorImpl<MCFixup> &Fixups,
1906
878
                                     const MCSubtargetInfo &STI) const {
1907
878
  const MCOperand MO = MI.getOperand(OpIdx);
1908
878
  if (MO.isExpr())
1909
32
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
846
  return isNeg ? 
-(MO.getImm() >> 1)308
:
(MO.getImm() >> 1)538
;
1911
846
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<false, (llvm::ARM::Fixups)162>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
179
                                     const MCSubtargetInfo &STI) const {
1907
179
  const MCOperand MO = MI.getOperand(OpIdx);
1908
179
  if (MO.isExpr())
1909
10
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
169
  return isNeg ? 
-(MO.getImm() >> 1)0
: (MO.getImm() >> 1);
1911
169
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<false, (llvm::ARM::Fixups)157>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
233
                                     const MCSubtargetInfo &STI) const {
1907
233
  const MCOperand MO = MI.getOperand(OpIdx);
1908
233
  if (MO.isExpr())
1909
10
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
223
  return isNeg ? 
-(MO.getImm() >> 1)0
: (MO.getImm() >> 1);
1911
223
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<false, (llvm::ARM::Fixups)158>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
51
                                     const MCSubtargetInfo &STI) const {
1907
51
  const MCOperand MO = MI.getOperand(OpIdx);
1908
51
  if (MO.isExpr())
1909
2
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
49
  return isNeg ? 
-(MO.getImm() >> 1)0
: (MO.getImm() >> 1);
1911
49
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<false, (llvm::ARM::Fixups)159>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
55
                                     const MCSubtargetInfo &STI) const {
1907
55
  const MCOperand MO = MI.getOperand(OpIdx);
1908
55
  if (MO.isExpr())
1909
2
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
53
  return isNeg ? 
-(MO.getImm() >> 1)0
: (MO.getImm() >> 1);
1911
53
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<false, (llvm::ARM::Fixups)160>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
46
                                     const MCSubtargetInfo &STI) const {
1907
46
  const MCOperand MO = MI.getOperand(OpIdx);
1908
46
  if (MO.isExpr())
1909
2
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
44
  return isNeg ? 
-(MO.getImm() >> 1)0
: (MO.getImm() >> 1);
1911
44
}
ARMMCCodeEmitter.cpp:unsigned int (anonymous namespace)::ARMMCCodeEmitter::getBFTargetOpValue<true, (llvm::ARM::Fixups)163>(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
Line
Count
Source
1906
314
                                     const MCSubtargetInfo &STI) const {
1907
314
  const MCOperand MO = MI.getOperand(OpIdx);
1908
314
  if (MO.isExpr())
1909
6
    return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1910
308
  return isNeg ? -(MO.getImm() >> 1) : 
(MO.getImm() >> 1)0
;
1911
308
}
1912
1913
uint32_t
1914
ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1915
                                          SmallVectorImpl<MCFixup> &Fixups,
1916
46
                                          const MCSubtargetInfo &STI) const {
1917
46
  const MCOperand MO = MI.getOperand(OpIdx);
1918
46
  const MCOperand BranchMO = MI.getOperand(0);
1919
46
1920
46
  if (MO.isExpr()) {
1921
2
    assert(BranchMO.isExpr());
1922
2
    const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1923
2
        MO.getExpr(), BranchMO.getExpr(), CTX);
1924
2
    MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1925
2
    Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1926
2
    return 0;
1927
2
  }
1928
44
1929
44
  assert(MO.isImm() && BranchMO.isImm());
1930
44
  int Diff = MO.getImm() - BranchMO.getImm();
1931
44
  assert(Diff == 4 || Diff == 2);
1932
44
1933
44
  return Diff == 4;
1934
44
}
1935
1936
uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1937
                                             SmallVectorImpl<MCFixup> &Fixups,
1938
80
                                             const MCSubtargetInfo &STI)const {
1939
80
  const MCOperand MO = MI.getOperand(OpIdx);
1940
80
  assert(MO.isImm() && "Unexpected operand type!");
1941
80
1942
80
  int Value = MO.getImm();
1943
80
  int Imm = 0;
1944
80
1945
80
  // VPT Masks are actually encoded as a series of invert/don't invert bits,
1946
80
  // rather than true/false bits.
1947
80
  unsigned PrevBit = 0;
1948
182
  for (int i = 3; i >= 0; 
--i102
) {
1949
182
    unsigned Bit = (Value >> i) & 1;
1950
182
1951
182
    // Check if we are at the end of the mask.
1952
182
    if ((Value & ~(~0U << i)) == 0) {
1953
80
      Imm |= (1 << i);
1954
80
      break;
1955
80
    }
1956
102
1957
102
    // Convert the bit in the mask based on the previous bit.
1958
102
    if (Bit != PrevBit)
1959
76
      Imm |= (1 << i);
1960
102
1961
102
    PrevBit = Bit;
1962
102
  }
1963
80
1964
80
  return Imm;
1965
80
}
1966
1967
uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1968
    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1969
156
    const MCSubtargetInfo &STI) const {
1970
156
1971
156
  const MCOperand MO = MI.getOperand(OpIdx);
1972
156
  assert(MO.isImm() && "Unexpected operand type!");
1973
156
1974
156
  switch (MO.getImm()) {
1975
156
  default:
1976
0
    assert(0 && "Unexpected Condition!");
1977
0
    return 0;
1978
156
  case ARMCC::HS:
1979
61
  case ARMCC::EQ:
1980
61
    return 0;
1981
61
  case ARMCC::HI:
1982
31
  case ARMCC::NE:
1983
31
    return 1;
1984
31
  case ARMCC::GE:
1985
13
    return 4;
1986
31
  case ARMCC::LT:
1987
16
    return 5;
1988
31
  case ARMCC::GT:
1989
17
    return 6;
1990
31
  case ARMCC::LE:
1991
18
    return 7;
1992
156
  }
1993
156
}
1994
1995
uint32_t ARMMCCodeEmitter::
1996
getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1997
                   SmallVectorImpl<MCFixup> &Fixups,
1998
36
                   const MCSubtargetInfo &STI) const {
1999
36
  const MCOperand &MO = MI.getOperand(OpIdx);
2000
36
  assert(MO.isImm() && "Unexpected operand type!");
2001
36
  return countTrailingZeros((uint64_t)MO.getImm());
2002
36
}
2003
2004
template <unsigned start>
2005
uint32_t ARMMCCodeEmitter::
2006
getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2007
                             SmallVectorImpl<MCFixup> &Fixups,
2008
8
                             const MCSubtargetInfo &STI) const {
2009
8
  const MCOperand MO = MI.getOperand(OpIdx);
2010
8
  assert(MO.isImm() && "Unexpected operand type!");
2011
8
2012
8
  int Value = MO.getImm();
2013
8
  return Value - start;
2014
8
}
2015
2016
#include "ARMGenMCCodeEmitter.inc"
2017
2018
MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
2019
                                              const MCRegisterInfo &MRI,
2020
3.88k
                                              MCContext &Ctx) {
2021
3.88k
  return new ARMMCCodeEmitter(MCII, Ctx, true);
2022
3.88k
}
2023
2024
MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
2025
                                              const MCRegisterInfo &MRI,
2026
21
                                              MCContext &Ctx) {
2027
21
  return new ARMMCCodeEmitter(MCII, Ctx, false);
2028
21
}