Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
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//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
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#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include <memory>
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#include <string>
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namespace llvm {
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class formatted_raw_ostream;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCInstPrinter;
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class MCObjectTargetWriter;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCStreamer;
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class MCTargetOptions;
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class MCRelocationInfo;
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class MCTargetStreamer;
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class StringRef;
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class Target;
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class Triple;
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class raw_ostream;
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class raw_pwrite_stream;
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namespace ARM_MC {
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std::string ParseARMTriple(const Triple &TT, StringRef CPU);
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/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
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/// do not need to go through TargetRegistry.
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MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
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                                          StringRef FS);
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}
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MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
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MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
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                                             formatted_raw_ostream &OS,
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                                             MCInstPrinter *InstPrint,
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                                             bool isVerboseAsm);
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MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
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                                                const MCSubtargetInfo &STI);
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MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
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                                        const MCRegisterInfo &MRI,
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                                        MCContext &Ctx);
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MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
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                                        const MCRegisterInfo &MRI,
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                                        MCContext &Ctx);
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MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
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                                    const MCRegisterInfo &MRI,
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                                    const MCTargetOptions &Options);
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MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
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                                    const MCRegisterInfo &MRI,
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                                    const MCTargetOptions &Options);
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// Construct a PE/COFF machine code streamer which will generate a PE/COFF
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// object file.
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MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
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                                     std::unique_ptr<MCAsmBackend> &&MAB,
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                                     std::unique_ptr<MCObjectWriter> &&OW,
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                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
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                                     bool RelaxAll,
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                                     bool IncrementalLinkerCompatible);
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/// Construct an ELF Mach-O object writer.
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std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
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/// Construct an ARM Mach-O object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
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                          uint32_t CPUSubtype);
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/// Construct an ARM PE/COFF object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createARMWinCOFFObjectWriter(bool Is64Bit);
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/// Construct ARM Mach-O relocation info.
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MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
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namespace ARM {
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enum OperandType {
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  OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
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  OPERAND_VPRED_N,
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};
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inline bool isVpred(OperandType op) {
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  return op == OPERAND_VPRED_R || 
op == OPERAND_VPRED_N444k
;
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}
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inline bool isVpred(uint8_t op) {
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  return isVpred(static_cast<OperandType>(op));
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}
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} // end namespace ARM
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} // End llvm namespace
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// Defines symbolic names for ARM registers.  This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "ARMGenRegisterInfo.inc"
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// Defines symbolic names for the ARM instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "ARMGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "ARMGenSubtargetInfo.inc"
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#endif