Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp
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//===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the unwind opcode assmebler for ARM exception handling
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// table.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMUnwindOpAsm.h"
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#include "llvm/Support/ARMEHABI.h"
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#include "llvm/Support/LEB128.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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using namespace llvm;
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namespace {
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  /// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
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  /// with MSB to LSB per uint32_t ordering.  For example, the first byte will
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  /// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
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  /// 7, 6, 5, 4, 11, 10, 9, 8, and so on.
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  class UnwindOpcodeStreamer {
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  private:
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    SmallVectorImpl<uint8_t> &Vec;
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    size_t Pos = 3;
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  public:
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    UnwindOpcodeStreamer(SmallVectorImpl<uint8_t> &V) : Vec(V) {}
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    /// Emit the byte in MSB to LSB per uint32_t order.
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    void EmitByte(uint8_t elem) {
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      Vec[Pos] = elem;
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      Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
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    }
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    /// Emit the size prefix.
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    void EmitSize(size_t Size) {
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      size_t SizeInWords = (Size + 3) / 4;
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      assert(SizeInWords <= 0x100u &&
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             "Only 256 additional words are allowed for unwind opcodes");
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      EmitByte(static_cast<uint8_t>(SizeInWords - 1));
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    }
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    /// Emit the personality index prefix.
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    void EmitPersonalityIndex(unsigned PI) {
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      assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX &&
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             "Invalid personality prefix");
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      EmitByte(ARM::EHABI::EHT_COMPACT | PI);
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    }
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    /// Fill the rest of bytes with FINISH opcode.
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    void FillFinishOpcode() {
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      while (Pos < Vec.size())
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        EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH);
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    }
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  };
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} // end anonymous namespace
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void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
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  if (RegSave == 0u)
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    return;
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  // One byte opcode to save register r14 and r11-r4
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  if (RegSave & (1u << 4)) {
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    // The one byte opcode will always save r4, thus we can't use the one byte
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    // opcode when r4 is not in .save directive.
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    // Compute the consecutive registers from r4 to r11.
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    uint32_t Mask = RegSave & 0xff0u;
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    uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4.
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    // Mask off non-consecutive registers. Keep r4.
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    Mask &= ~(0xffffffe0u << Range);
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    // Emit this opcode when the mask covers every registers.
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    uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
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    if (UnmaskedReg == 0u) {
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      // Pop r[4 : (4 + n)]
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      EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
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      RegSave &= 0x000fu;
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    } else if (UnmaskedReg == (1u << 14)) {
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      // Pop r[14] + r[4 : (4 + n)]
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      EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
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      RegSave &= 0x000fu;
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    }
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  }
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  // Two bytes opcode to save register r15-r4
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  if ((RegSave & 0xfff0u) != 0)
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    EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
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  // Opcode to save register r3-r0
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  if ((RegSave & 0x000fu) != 0)
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    EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
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}
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/// Emit unwind opcodes for .vsave directives
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void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
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  // We only have 4 bits to save the offset in the opcode so look at the lower
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  // and upper 16 bits separately.
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  for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
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    while (Regs) {
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      // Now look for a run of set bits. Remember the MSB and LSB of the run.
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      auto RangeMSB = 32 - countLeadingZeros(Regs);
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      auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
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      auto RangeLSB = RangeMSB - RangeLen;
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      int Opcode = RangeLSB >= 16
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                       ? 
ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D163
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                       : 
ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD8
;
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      EmitInt16(Opcode | ((RangeLSB % 16) << 4) | (RangeLen - 1));
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      // Zero out bits we're done with.
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      Regs &= ~(-1u << RangeLSB);
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    }
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  }
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}
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/// Emit unwind opcodes to copy address from source register to $sp.
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void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
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  EmitInt8(ARM::EHABI::UNWIND_OPCODE_SET_VSP | Reg);
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}
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/// Emit unwind opcodes to add $sp with an offset.
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void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) {
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  if (Offset > 0x200) {
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    uint8_t Buff[16];
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    Buff[0] = ARM::EHABI::UNWIND_OPCODE_INC_VSP_ULEB128;
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    size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1);
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    EmitBytes(Buff, ULEBSize + 1);
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  } else if (Offset > 0) {
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    if (Offset > 0x100) {
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      EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | 0x3fu);
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      Offset -= 0x100;
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    }
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    EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP |
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             static_cast<uint8_t>((Offset - 4) >> 2));
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  } else 
if (96
Offset < 096
) {
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    while (Offset < -0x100) {
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      EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP | 0x3fu);
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      Offset += 0x100;
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    }
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    EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP |
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             static_cast<uint8_t>(((-Offset) - 4) >> 2));
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  }
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}
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void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
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                                     SmallVectorImpl<uint8_t> &Result) {
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  UnwindOpcodeStreamer OpStreamer(Result);
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  if (HasPersonality) {
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    // User-specifed personality routine: [ SIZE , OP1 , OP2 , ... ]
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    PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX;
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    size_t TotalSize = Ops.size() + 1;
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    size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
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    Result.resize(RoundUpSize);
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    OpStreamer.EmitSize(RoundUpSize);
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  } else {
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    // If no personalityindex is specified, select ane
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    if (PersonalityIndex == ARM::EHABI::NUM_PERSONALITY_INDEX)
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      PersonalityIndex = (Ops.size() <= 3) ? 
ARM::EHABI::AEABI_UNWIND_CPP_PR0306
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                                           : 
ARM::EHABI::AEABI_UNWIND_CPP_PR1145
;
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    if (PersonalityIndex == ARM::EHABI::AEABI_UNWIND_CPP_PR0) {
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      // __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
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      assert(Ops.size() <= 3 && "too many opcodes for __aeabi_unwind_cpp_pr0");
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      Result.resize(4);
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      OpStreamer.EmitPersonalityIndex(PersonalityIndex);
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    } else {
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      // __aeabi_unwind_cpp_pr{1,2}: [ {0x81,0x82} , SIZE , OP1 , OP2 , ... ]
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      size_t TotalSize = Ops.size() + 2;
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      size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
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      Result.resize(RoundUpSize);
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      OpStreamer.EmitPersonalityIndex(PersonalityIndex);
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      OpStreamer.EmitSize(RoundUpSize);
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    }
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  }
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  // Copy the unwind opcodes
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  for (size_t i = OpBegins.size() - 1; i > 0; 
--i952
)
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for (size_t j = OpBegins[i - 1], end = OpBegins[i]; 952
j < end;
++j1.41k
)
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      OpStreamer.EmitByte(Ops[j]);
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  // Emit the padding finish opcodes if the size is not multiple of 4.
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  OpStreamer.FillFinishOpcode();
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  // Reset the assembler state
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  Reset();
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}