Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp
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//===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/BinaryFormat/COFF.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/MC/MCWinCOFFObjectWriter.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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using namespace llvm;
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namespace {
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class ARMWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter {
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public:
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  ARMWinCOFFObjectWriter(bool Is64Bit)
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    : MCWinCOFFObjectTargetWriter(COFF::IMAGE_FILE_MACHINE_ARMNT) {
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    assert(!Is64Bit && "AArch64 support not yet implemented");
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  }
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  ~ARMWinCOFFObjectWriter() override = default;
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  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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                        const MCFixup &Fixup, bool IsCrossSection,
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                        const MCAsmBackend &MAB) const override;
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  bool recordRelocation(const MCFixup &) const override;
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};
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} // end anonymous namespace
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unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
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                                              const MCValue &Target,
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                                              const MCFixup &Fixup,
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                                              bool IsCrossSection,
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                                              const MCAsmBackend &MAB) const {
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  assert(getMachine() == COFF::IMAGE_FILE_MACHINE_ARMNT &&
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         "AArch64 support not yet implemented");
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  MCSymbolRefExpr::VariantKind Modifier =
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    Target.isAbsolute() ? 
MCSymbolRefExpr::VK_None0
: Target.getSymA()->getKind();
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  switch (static_cast<unsigned>(Fixup.getKind())) {
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  default: {
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    const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
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    report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
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  }
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  case FK_Data_4:
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    switch (Modifier) {
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    case MCSymbolRefExpr::VK_COFF_IMGREL32:
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      return COFF::IMAGE_REL_ARM_ADDR32NB;
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    case MCSymbolRefExpr::VK_SECREL:
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      return COFF::IMAGE_REL_ARM_SECREL;
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    default:
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      return COFF::IMAGE_REL_ARM_ADDR32;
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    }
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  case FK_SecRel_2:
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    return COFF::IMAGE_REL_ARM_SECTION;
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  case FK_SecRel_4:
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    return COFF::IMAGE_REL_ARM_SECREL;
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  case ARM::fixup_t2_condbranch:
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    return COFF::IMAGE_REL_ARM_BRANCH20T;
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  case ARM::fixup_t2_uncondbranch:
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  case ARM::fixup_arm_thumb_bl:
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    return COFF::IMAGE_REL_ARM_BRANCH24T;
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  case ARM::fixup_arm_thumb_blx:
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    return COFF::IMAGE_REL_ARM_BLX23T;
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  case ARM::fixup_t2_movw_lo16:
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  case ARM::fixup_t2_movt_hi16:
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    return COFF::IMAGE_REL_ARM_MOV32T;
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  }
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}
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bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
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  return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
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}
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namespace llvm {
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std::unique_ptr<MCObjectTargetWriter>
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createARMWinCOFFObjectWriter(bool Is64Bit) {
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  return llvm::make_unique<ARMWinCOFFObjectWriter>(Is64Bit);
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}
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} // end namespace llvm