Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
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//===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
9
#include "ARM.h"
10
#include "ARMMachineFunctionInfo.h"
11
#include "ARMSubtarget.h"
12
#include "MCTargetDesc/ARMBaseInfo.h"
13
#include "Thumb2InstrInfo.h"
14
#include "llvm/ADT/SmallSet.h"
15
#include "llvm/ADT/SmallVector.h"
16
#include "llvm/ADT/Statistic.h"
17
#include "llvm/ADT/StringRef.h"
18
#include "llvm/CodeGen/MachineBasicBlock.h"
19
#include "llvm/CodeGen/MachineFunction.h"
20
#include "llvm/CodeGen/MachineFunctionPass.h"
21
#include "llvm/CodeGen/MachineInstr.h"
22
#include "llvm/CodeGen/MachineInstrBuilder.h"
23
#include "llvm/CodeGen/MachineInstrBundle.h"
24
#include "llvm/CodeGen/MachineOperand.h"
25
#include "llvm/IR/DebugLoc.h"
26
#include "llvm/MC/MCInstrDesc.h"
27
#include "llvm/MC/MCRegisterInfo.h"
28
#include <cassert>
29
#include <new>
30
31
using namespace llvm;
32
33
#define DEBUG_TYPE "thumb2-it"
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31.6k
#define PASS_NAME "Thumb IT blocks insertion pass"
35
36
STATISTIC(NumITs,        "Number of IT blocks inserted");
37
STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
38
39
using RegisterSet = SmallSet<unsigned, 4>;
40
41
namespace {
42
43
  class Thumb2ITBlock : public MachineFunctionPass {
44
  public:
45
    static char ID;
46
47
    bool restrictIT;
48
    const Thumb2InstrInfo *TII;
49
    const TargetRegisterInfo *TRI;
50
    ARMFunctionInfo *AFI;
51
52
5.19k
    Thumb2ITBlock() : MachineFunctionPass(ID) {}
53
54
    bool runOnMachineFunction(MachineFunction &Fn) override;
55
56
5.17k
    MachineFunctionProperties getRequiredProperties() const override {
57
5.17k
      return MachineFunctionProperties().set(
58
5.17k
          MachineFunctionProperties::Property::NoVRegs);
59
5.17k
    }
60
61
31.6k
    StringRef getPassName() const override {
62
31.6k
      return PASS_NAME;
63
31.6k
    }
64
65
  private:
66
    bool MoveCopyOutOfITBlock(MachineInstr *MI,
67
                              ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
68
                              RegisterSet &Defs, RegisterSet &Uses);
69
    bool InsertITInstructions(MachineBasicBlock &Block);
70
  };
71
72
  char Thumb2ITBlock::ID = 0;
73
74
} // end anonymous namespace
75
76
INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
77
78
/// TrackDefUses - Tracking what registers are being defined and used by
79
/// instructions in the IT block. This also tracks "dependencies", i.e. uses
80
/// in the IT block that are defined before the IT instruction.
81
static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
82
14.9k
                         const TargetRegisterInfo *TRI) {
83
14.9k
  using RegList = SmallVector<unsigned, 4>;
84
14.9k
  RegList LocalDefs;
85
14.9k
  RegList LocalUses;
86
14.9k
87
94.1k
  for (auto &MO : MI->operands()) {
88
94.1k
    if (!MO.isReg())
89
24.6k
      continue;
90
69.5k
    unsigned Reg = MO.getReg();
91
69.5k
    if (!Reg || 
Reg == ARM::ITSTATE61.7k
||
Reg == ARM::SP57.2k
)
92
17.2k
      continue;
93
52.2k
    if (MO.isUse())
94
36.8k
      LocalUses.push_back(Reg);
95
15.4k
    else
96
15.4k
      LocalDefs.push_back(Reg);
97
52.2k
  }
98
14.9k
99
29.9k
  auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100
29.9k
    for (unsigned Reg : Regs)
101
52.2k
      for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
102
104k
           Subreg.isValid(); 
++Subreg52.5k
)
103
52.5k
        UsesDefs.insert(*Subreg);
104
29.9k
  };
105
14.9k
106
14.9k
  InsertUsesDefs(LocalDefs, Defs);
107
14.9k
  InsertUsesDefs(LocalUses, Uses);
108
14.9k
}
109
110
/// Clear kill flags for any uses in the given set.  This will likely
111
/// conservatively remove more kill flags than are necessary, but removing them
112
/// is safer than incorrect kill flags remaining on instructions.
113
30
static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
114
120
  for (MachineOperand &MO : MI->operands()) {
115
120
    if (!MO.isReg() || 
MO.isDef()90
||
!MO.isKill()60
)
116
120
      continue;
117
0
    if (!Uses.count(MO.getReg()))
118
0
      continue;
119
0
    MO.setIsKill(false);
120
0
  }
121
30
}
122
123
7.99k
static bool isCopy(MachineInstr *MI) {
124
7.99k
  switch (MI->getOpcode()) {
125
7.99k
  default:
126
7.15k
    return false;
127
7.99k
  case ARM::MOVr:
128
837
  case ARM::MOVr_TC:
129
837
  case ARM::tMOVr:
130
837
  case ARM::t2MOVr:
131
837
    return true;
132
7.99k
  }
133
7.99k
}
134
135
bool
136
Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
137
                                    ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
138
7.99k
                                    RegisterSet &Defs, RegisterSet &Uses) {
139
7.99k
  if (!isCopy(MI))
140
7.15k
    return false;
141
837
  // llvm models select's as two-address instructions. That means a copy
142
837
  // is inserted before a t2MOVccr, etc. If the copy is scheduled in
143
837
  // between selects we would end up creating multiple IT blocks.
144
837
  assert(MI->getOperand(0).getSubReg() == 0 &&
145
837
         MI->getOperand(1).getSubReg() == 0 &&
146
837
         "Sub-register indices still around?");
147
837
148
837
  unsigned DstReg = MI->getOperand(0).getReg();
149
837
  unsigned SrcReg = MI->getOperand(1).getReg();
150
837
151
837
  // First check if it's safe to move it.
152
837
  if (Uses.count(DstReg) || 
Defs.count(SrcReg)545
)
153
534
    return false;
154
303
155
303
  // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
156
303
  // if we have:
157
303
  //
158
303
  //   movs  r1, r1
159
303
  //   rsb   r1, 0
160
303
  //   movs  r2, r2
161
303
  //   rsb   r2, 0
162
303
  //
163
303
  // we don't want this to be converted to:
164
303
  //
165
303
  //   movs  r1, r1
166
303
  //   movs  r2, r2
167
303
  //   itt   mi
168
303
  //   rsb   r1, 0
169
303
  //   rsb   r2, 0
170
303
  //
171
303
  const MCInstrDesc &MCID = MI->getDesc();
172
303
  if (MI->hasOptionalDef() &&
173
303
      
MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR0
)
174
0
    return false;
175
303
176
303
  // Then peek at the next instruction to see if it's predicated on CC or OCC.
177
303
  // If not, then there is nothing to be gained by moving the copy.
178
303
  MachineBasicBlock::iterator I = MI;
179
303
  ++I;
180
303
  MachineBasicBlock::iterator E = MI->getParent()->end();
181
303
182
303
  while (I != E && I->isDebugInstr())
183
0
    ++I;
184
303
185
303
  if (I != E) {
186
303
    unsigned NPredReg = 0;
187
303
    ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
188
303
    if (NCC == CC || 
NCC == OCC273
)
189
30
      return true;
190
273
  }
191
273
  return false;
192
273
}
193
194
90.0k
bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
195
90.0k
  bool Modified = false;
196
90.0k
  RegisterSet Defs, Uses;
197
90.0k
  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
198
90.0k
199
774k
  while (MBBI != E) {
200
684k
    MachineInstr *MI = &*MBBI;
201
684k
    DebugLoc dl = MI->getDebugLoc();
202
684k
    unsigned PredReg = 0;
203
684k
    ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
204
684k
    if (CC == ARMCC::AL) {
205
674k
      ++MBBI;
206
674k
      continue;
207
674k
    }
208
10.4k
209
10.4k
    Defs.clear();
210
10.4k
    Uses.clear();
211
10.4k
    TrackDefUses(MI, Defs, Uses, TRI);
212
10.4k
213
10.4k
    // Insert an IT instruction.
214
10.4k
    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
215
10.4k
      .addImm(CC);
216
10.4k
217
10.4k
    // Add implicit use of ITSTATE to IT block instructions.
218
10.4k
    MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
219
10.4k
                                             true/*isImp*/, false/*isKill*/));
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10.4k
221
10.4k
    MachineInstr *LastITMI = MI;
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10.4k
    MachineBasicBlock::iterator InsertPos = MIB.getInstr();
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10.4k
    ++MBBI;
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10.4k
225
10.4k
    // Form IT block.
226
10.4k
    ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
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10.4k
    unsigned Mask = 0, Pos = 3;
228
10.4k
229
10.4k
    // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
230
10.4k
    // is set: skip the loop
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10.4k
    if (!restrictIT) {
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10.2k
      // Branches, including tricky ones like LDM_RET, need to end an IT
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10.2k
      // block so check the instruction we just put in the block.
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14.8k
      for (; MBBI != E && 
Pos14.0k
&&
235
14.8k
             
(13.6k
!MI->isBranch()13.6k
&&
!MI->isReturn()13.6k
) ;
++MBBI4.52k
) {
236
12.5k
        if (MBBI->isDebugInstr())
237
1
          continue;
238
12.5k
239
12.5k
        MachineInstr *NMI = &*MBBI;
240
12.5k
        MI = NMI;
241
12.5k
242
12.5k
        unsigned NPredReg = 0;
243
12.5k
        ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
244
12.5k
        if (NCC == CC || 
NCC == OCC8.41k
) {
245
4.49k
          Mask |= ((NCC ^ CC) & 1) << Pos;
246
4.49k
          // Add implicit use of ITSTATE.
247
4.49k
          NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
248
4.49k
                                                 true/*isImp*/, false/*isKill*/));
249
4.49k
          LastITMI = NMI;
250
8.01k
        } else {
251
8.01k
          if (NCC == ARMCC::AL &&
252
8.01k
              
MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)7.99k
) {
253
30
            --MBBI;
254
30
            MBB.remove(NMI);
255
30
            MBB.insert(InsertPos, NMI);
256
30
            ClearKillFlags(MI, Uses);
257
30
            ++NumMovedInsts;
258
30
            continue;
259
30
          }
260
7.98k
          break;
261
7.98k
        }
262
4.49k
        TrackDefUses(NMI, Defs, Uses, TRI);
263
4.49k
        --Pos;
264
4.49k
      }
265
10.2k
    }
266
10.4k
267
10.4k
    // Finalize IT mask.
268
10.4k
    Mask |= (1 << Pos);
269
10.4k
    MIB.addImm(Mask);
270
10.4k
271
10.4k
    // Last instruction in IT block kills ITSTATE.
272
10.4k
    LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
273
10.4k
274
10.4k
    // Finalize the bundle.
275
10.4k
    finalizeBundle(MBB, InsertPos.getInstrIterator(),
276
10.4k
                   ++LastITMI->getIterator());
277
10.4k
278
10.4k
    Modified = true;
279
10.4k
    ++NumITs;
280
10.4k
  }
281
90.0k
282
90.0k
  return Modified;
283
90.0k
}
284
285
26.5k
bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
286
26.5k
  const ARMSubtarget &STI =
287
26.5k
      static_cast<const ARMSubtarget &>(Fn.getSubtarget());
288
26.5k
  if (!STI.isThumb2())
289
10.5k
    return false;
290
15.9k
  AFI = Fn.getInfo<ARMFunctionInfo>();
291
15.9k
  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
292
15.9k
  TRI = STI.getRegisterInfo();
293
15.9k
  restrictIT = STI.restrictIT();
294
15.9k
295
15.9k
  if (!AFI->isThumbFunction())
296
0
    return false;
297
15.9k
298
15.9k
  bool Modified = false;
299
15.9k
  for (auto &MBB : Fn )
300
90.0k
    Modified |= InsertITInstructions(MBB);
301
15.9k
302
15.9k
  if (Modified)
303
4.78k
    AFI->setHasITBlocks(true);
304
15.9k
305
15.9k
  return Modified;
306
15.9k
}
307
308
/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
309
/// insertion pass.
310
5.19k
FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
311
312
#undef DEBUG_TYPE
313
#define DEBUG_TYPE "arm-mve-vpt"
314
315
namespace {
316
  class MVEVPTBlock : public MachineFunctionPass {
317
  public:
318
    static char ID;
319
    const Thumb2InstrInfo *TII;
320
    const TargetRegisterInfo *TRI;
321
322
5.19k
    MVEVPTBlock() : MachineFunctionPass(ID) {}
323
324
    bool runOnMachineFunction(MachineFunction &Fn) override;
325
326
5.17k
    MachineFunctionProperties getRequiredProperties() const override {
327
5.17k
      return MachineFunctionProperties().set(
328
5.17k
          MachineFunctionProperties::Property::NoVRegs);
329
5.17k
    }
330
331
31.7k
    StringRef getPassName() const override {
332
31.7k
      return "MVE VPT block insertion pass";
333
31.7k
    }
334
335
  private:
336
    bool InsertVPTBlocks(MachineBasicBlock &MBB);
337
  };
338
339
  char MVEVPTBlock::ID = 0;
340
341
} // end anonymous namespace
342
343
INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
344
345
enum VPTMaskValue {
346
  T     =  8, // 0b1000
347
  TT    =  4, // 0b0100
348
  TE    = 12, // 0b1100
349
  TTT   =  2, // 0b0010
350
  TTE   =  6, // 0b0110
351
  TEE   = 10, // 0b1010
352
  TET   = 14, // 0b1110
353
  TTTT  =  1, // 0b0001
354
  TTTE  =  3, // 0b0011
355
  TTEE  =  5, // 0b0101
356
  TTET  =  7, // 0b0111
357
  TEEE  =  9, // 0b1001
358
  TEET  = 11, // 0b1011
359
  TETT  = 13, // 0b1101
360
  TETE  = 15  // 0b1111
361
};
362
363
1.05k
bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
364
1.05k
  bool Modified = false;
365
1.05k
  MachineBasicBlock::iterator MBIter = Block.begin();
366
1.05k
  MachineBasicBlock::iterator EndIter = Block.end();
367
1.05k
368
12.4k
  while (MBIter != EndIter) {
369
11.4k
    MachineInstr *MI = &*MBIter;
370
11.4k
    unsigned PredReg = 0;
371
11.4k
    DebugLoc dl = MI->getDebugLoc();
372
11.4k
373
11.4k
    ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
374
11.4k
375
11.4k
    // The idea of the predicate is that None, Then and Else are for use when
376
11.4k
    // handling assembly language: they correspond to the three possible
377
11.4k
    // suffixes "", "t" and "e" on the mnemonic. So when instructions are read
378
11.4k
    // from assembly source or disassembled from object code, you expect to see
379
11.4k
    // a mixture whenever there's a long VPT block. But in code generation, we
380
11.4k
    // hope we'll never generate an Else as input to this pass.
381
11.4k
382
11.4k
    assert(Pred != ARMVCC::Else && "VPT block pass does not expect Else preds");
383
11.4k
384
11.4k
    if (Pred == ARMVCC::None) {
385
11.4k
      ++MBIter;
386
11.4k
      continue;
387
11.4k
    }
388
9
389
9
    MachineInstrBuilder MIBuilder =
390
9
        BuildMI(Block, MBIter, dl, TII->get(ARM::MVE_VPST));
391
9
392
9
    MachineBasicBlock::iterator VPSTInsertPos = MIBuilder.getInstr();
393
9
    int VPTInstCnt = 1;
394
9
    ARMVCC::VPTCodes NextPred;
395
9
396
16
    do {
397
16
      ++MBIter;
398
16
      NextPred = getVPTInstrPredicate(*MBIter, PredReg);
399
16
    } while (NextPred != ARMVCC::None && 
NextPred == Pred9
&&
++VPTInstCnt < 49
);
400
9
401
9
    switch (VPTInstCnt) {
402
9
    case 1:
403
4
      MIBuilder.addImm(VPTMaskValue::T);
404
4
      break;
405
9
    case 2:
406
3
      MIBuilder.addImm(VPTMaskValue::TT);
407
3
      break;
408
9
    case 3:
409
0
      MIBuilder.addImm(VPTMaskValue::TTT);
410
0
      break;
411
9
    case 4:
412
2
      MIBuilder.addImm(VPTMaskValue::TTTT);
413
2
      break;
414
9
    default:
415
0
      llvm_unreachable("Unexpected number of instruction in a VPT block");
416
9
    };
417
9
418
9
    MachineInstr *LastMI = &*MBIter;
419
9
    finalizeBundle(Block, VPSTInsertPos.getInstrIterator(),
420
9
                   ++LastMI->getIterator());
421
9
422
9
    Modified = true;
423
9
    LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump());
424
9
425
9
    ++MBIter;
426
9
  }
427
1.05k
  return Modified;
428
1.05k
}
429
430
26.5k
bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
431
26.5k
  const ARMSubtarget &STI =
432
26.5k
      static_cast<const ARMSubtarget &>(Fn.getSubtarget());
433
26.5k
434
26.5k
  if (!STI.isThumb2() || 
!STI.hasMVEIntegerOps()15.9k
)
435
25.4k
    return false;
436
1.05k
437
1.05k
  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
438
1.05k
  TRI = STI.getRegisterInfo();
439
1.05k
440
1.05k
  LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
441
1.05k
                    << "********** Function: " << Fn.getName() << '\n');
442
1.05k
443
1.05k
  bool Modified = false;
444
1.05k
  for (MachineBasicBlock &MBB : Fn)
445
1.05k
    Modified |= InsertVPTBlocks(MBB);
446
1.05k
447
1.05k
  LLVM_DEBUG(dbgs() << "**************************************\n");
448
1.05k
  return Modified;
449
1.05k
}
450
451
/// createMVEVPTBlock - Returns an instance of the MVE VPT block
452
/// insertion pass.
453
5.19k
FunctionPass *llvm::createMVEVPTBlockPass() { return new MVEVPTBlock(); }