Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/Thumb2InstrInfo.h
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//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "ThumbRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ScheduleHazardRecognizer;
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class Thumb2InstrInfo : public ARMBaseInstrInfo {
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  ThumbRegisterInfo RI;
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public:
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  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
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  /// Return the noop instruction to use for a noop.
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  void getNoop(MCInst &NopInst) const override;
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  // Return the non-pre/post incrementing version of 'Opc'. Return 0
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  // if there is not such an opcode.
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  unsigned getUnindexedOpcode(unsigned Opc) const override;
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  void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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                               MachineBasicBlock *NewDest) const override;
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  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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                           MachineBasicBlock::iterator MBBI) const override;
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  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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                   bool KillSrc) const override;
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  void storeRegToStackSlot(MachineBasicBlock &MBB,
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                           MachineBasicBlock::iterator MBBI,
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                           unsigned SrcReg, bool isKill, int FrameIndex,
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                           const TargetRegisterClass *RC,
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                           const TargetRegisterInfo *TRI) const override;
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  void loadRegFromStackSlot(MachineBasicBlock &MBB,
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                            MachineBasicBlock::iterator MBBI,
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                            unsigned DestReg, int FrameIndex,
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                            const TargetRegisterClass *RC,
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                            const TargetRegisterInfo *TRI) const override;
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  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
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  /// such, whenever a client has an instance of instruction info, it should
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  /// always be able to get register info as well (through this method).
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  ///
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  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
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private:
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  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
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};
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/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
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/// to llvm::getInstrPredicate except it returns AL for conditional branch
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/// instructions which are "predicated", but are not in IT blocks.
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ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
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// getVPTInstrPredicate: VPT analogue of that, plus a helper function
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// corresponding to MachineInstr::findFirstPredOperandIdx.
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int findFirstVPTPredOperandIdx(const MachineInstr &MI);
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ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
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                                      unsigned &PredReg);
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}
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#endif