Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- ThumbRegisterInfo.cpp - Thumb-1 Register Information -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains the Thumb-1 implementation of the TargetRegisterInfo
10
// class.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "ThumbRegisterInfo.h"
15
#include "ARMBaseInstrInfo.h"
16
#include "ARMMachineFunctionInfo.h"
17
#include "ARMSubtarget.h"
18
#include "MCTargetDesc/ARMAddressingModes.h"
19
#include "llvm/CodeGen/MachineConstantPool.h"
20
#include "llvm/CodeGen/MachineFrameInfo.h"
21
#include "llvm/CodeGen/MachineFunction.h"
22
#include "llvm/CodeGen/MachineInstrBuilder.h"
23
#include "llvm/CodeGen/MachineRegisterInfo.h"
24
#include "llvm/CodeGen/RegisterScavenging.h"
25
#include "llvm/IR/Constants.h"
26
#include "llvm/IR/DerivedTypes.h"
27
#include "llvm/IR/Function.h"
28
#include "llvm/IR/LLVMContext.h"
29
#include "llvm/Support/CommandLine.h"
30
#include "llvm/Support/ErrorHandling.h"
31
#include "llvm/CodeGen/TargetFrameLowering.h"
32
#include "llvm/Target/TargetMachine.h"
33
34
namespace llvm {
35
extern cl::opt<bool> ReuseFrameIndexVals;
36
}
37
38
using namespace llvm;
39
40
4.26k
ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}
41
42
const TargetRegisterClass *
43
ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
44
59.0k
                                              const MachineFunction &MF) const {
45
59.0k
  if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
46
54.8k
    return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
47
4.26k
48
4.26k
  if (ARM::tGPRRegClass.hasSubClassEq(RC))
49
4.26k
    return &ARM::tGPRRegClass;
50
2
  return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
51
2
}
52
53
const TargetRegisterClass *
54
ThumbRegisterInfo::getPointerRegClass(const MachineFunction &MF,
55
224
                                      unsigned Kind) const {
56
224
  if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
57
213
    return ARMBaseRegisterInfo::getPointerRegClass(MF, Kind);
58
11
  return &ARM::tGPRRegClass;
59
11
}
60
61
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB,
62
                                    MachineBasicBlock::iterator &MBBI,
63
                                    const DebugLoc &dl, unsigned DestReg,
64
                                    unsigned SubIdx, int Val,
65
                                    ARMCC::CondCodes Pred, unsigned PredReg,
66
83
                                    unsigned MIFlags) {
67
83
  MachineFunction &MF = *MBB.getParent();
68
83
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
69
83
  const TargetInstrInfo &TII = *STI.getInstrInfo();
70
83
  MachineConstantPool *ConstantPool = MF.getConstantPool();
71
83
  const Constant *C = ConstantInt::get(
72
83
          Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Val);
73
83
  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
74
83
75
83
  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
76
83
    .addReg(DestReg, getDefRegState(true), SubIdx)
77
83
    .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
78
83
    .setMIFlags(MIFlags);
79
83
}
80
81
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB,
82
                                    MachineBasicBlock::iterator &MBBI,
83
                                    const DebugLoc &dl, unsigned DestReg,
84
                                    unsigned SubIdx, int Val,
85
                                    ARMCC::CondCodes Pred, unsigned PredReg,
86
0
                                    unsigned MIFlags) {
87
0
  MachineFunction &MF = *MBB.getParent();
88
0
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
89
0
  MachineConstantPool *ConstantPool = MF.getConstantPool();
90
0
  const Constant *C = ConstantInt::get(
91
0
           Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Val);
92
0
  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
93
0
94
0
  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
95
0
      .addReg(DestReg, getDefRegState(true), SubIdx)
96
0
      .addConstantPoolIndex(Idx)
97
0
      .add(predOps(ARMCC::AL))
98
0
      .setMIFlags(MIFlags);
99
0
}
100
101
/// emitLoadConstPool - Emits a load from constpool to materialize the
102
/// specified immediate.
103
void ThumbRegisterInfo::emitLoadConstPool(
104
    MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
105
    const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
106
83
    ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
107
83
  MachineFunction &MF = *MBB.getParent();
108
83
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
109
83
  if (STI.isThumb1Only()) {
110
83
    assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) &&
111
83
           "Thumb1 does not have ldr to high register");
112
83
    return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
113
83
                                   PredReg, MIFlags);
114
83
  }
115
0
  return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
116
0
                                 PredReg, MIFlags);
117
0
}
118
119
/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
120
/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
121
/// in a register using mov / mvn sequences or load the immediate from a
122
/// constpool entry.
123
static void emitThumbRegPlusImmInReg(
124
    MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
125
    const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes,
126
    bool CanChangeCC, const TargetInstrInfo &TII,
127
28
    const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) {
128
28
  MachineFunction &MF = *MBB.getParent();
129
28
  const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
130
28
  bool isHigh = !isARMLowRegister(DestReg) ||
131
28
                
(10
BaseReg != 010
&&
!isARMLowRegister(BaseReg)10
);
132
28
  bool isSub = false;
133
28
  // Subtract doesn't have high register version. Load the negative value
134
28
  // if either base or dest register is a high register. Also, if do not
135
28
  // issue sub as part of the sequence if condition register is to be
136
28
  // preserved.
137
28
  if (NumBytes < 0 && 
!isHigh2
&&
CanChangeCC0
) {
138
0
    isSub = true;
139
0
    NumBytes = -NumBytes;
140
0
  }
141
28
  unsigned LdReg = DestReg;
142
28
  if (DestReg == ARM::SP)
143
28
    assert(BaseReg == ARM::SP && "Unexpected!");
144
28
  if (!isARMLowRegister(DestReg) && 
!MRI.isVirtualRegister(DestReg)18
)
145
4
    LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
146
28
147
28
  if (NumBytes <= 255 && 
NumBytes >= 02
&&
CanChangeCC0
) {
148
0
    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
149
0
        .add(t1CondCodeOp())
150
0
        .addImm(NumBytes)
151
0
        .setMIFlags(MIFlags);
152
28
  } else if (NumBytes < 0 && 
NumBytes >= -2552
&&
CanChangeCC0
) {
153
0
    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
154
0
        .add(t1CondCodeOp())
155
0
        .addImm(NumBytes)
156
0
        .setMIFlags(MIFlags);
157
0
    BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
158
0
        .add(t1CondCodeOp())
159
0
        .addReg(LdReg, RegState::Kill)
160
0
        .setMIFlags(MIFlags);
161
28
  } else if (ST.genExecuteOnly()) {
162
4
    BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)
163
4
      .addImm(NumBytes).setMIFlags(MIFlags);
164
4
  } else
165
24
    MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, ARMCC::AL, 0,
166
24
                          MIFlags);
167
28
168
28
  // Emit add / sub.
169
28
  int Opc = (isSub) ? 
ARM::tSUBrr0
170
28
                    : ((isHigh || 
!CanChangeCC4
) ?
ARM::tADDhirr24
:
ARM::tADDrr4
);
171
28
  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
172
28
  if (Opc != ARM::tADDhirr)
173
4
    MIB = MIB.add(t1CondCodeOp());
174
28
  if (DestReg == ARM::SP || 
isSub24
)
175
4
    MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
176
24
  else
177
24
    MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
178
28
  MIB.add(predOps(ARMCC::AL));
179
28
}
180
181
/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
182
/// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
183
/// SUBs first, and uses a constant pool value if the instruction sequence would
184
/// be too long. This is allowed to modify the condition flags.
185
void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
186
                                     MachineBasicBlock::iterator &MBBI,
187
                                     const DebugLoc &dl, unsigned DestReg,
188
                                     unsigned BaseReg, int NumBytes,
189
                                     const TargetInstrInfo &TII,
190
                                     const ARMBaseRegisterInfo &MRI,
191
1.74k
                                     unsigned MIFlags) {
192
1.74k
  bool isSub = NumBytes < 0;
193
1.74k
  unsigned Bytes = (unsigned)NumBytes;
194
1.74k
  if (isSub) 
Bytes = -NumBytes457
;
195
1.74k
196
1.74k
  int CopyOpc = 0;
197
1.74k
  unsigned CopyBits = 0;
198
1.74k
  unsigned CopyScale = 1;
199
1.74k
  bool CopyNeedsCC = false;
200
1.74k
  int ExtraOpc = 0;
201
1.74k
  unsigned ExtraBits = 0;
202
1.74k
  unsigned ExtraScale = 1;
203
1.74k
  bool ExtraNeedsCC = false;
204
1.74k
205
1.74k
  // Strategy:
206
1.74k
  // We need to select two types of instruction, maximizing the available
207
1.74k
  // immediate range of each. The instructions we use will depend on whether
208
1.74k
  // DestReg and BaseReg are low, high or the stack pointer.
209
1.74k
  // * CopyOpc  - DestReg = BaseReg + imm
210
1.74k
  //              This will be emitted once if DestReg != BaseReg, and never if
211
1.74k
  //              DestReg == BaseReg.
212
1.74k
  // * ExtraOpc - DestReg = DestReg + imm
213
1.74k
  //              This will be emitted as many times as necessary to add the
214
1.74k
  //              full immediate.
215
1.74k
  // If the immediate ranges of these instructions are not large enough to cover
216
1.74k
  // NumBytes with a reasonable number of instructions, we fall back to using a
217
1.74k
  // value loaded from a constant pool.
218
1.74k
  if (DestReg == ARM::SP) {
219
1.32k
    if (BaseReg == ARM::SP) {
220
1.32k
      // sp -> sp
221
1.32k
      // Already in right reg, no copy needed
222
1.32k
    } else {
223
0
      // low -> sp or high -> sp
224
0
      CopyOpc = ARM::tMOVr;
225
0
      CopyBits = 0;
226
0
    }
227
1.32k
    ExtraOpc = isSub ? 
ARM::tSUBspi377
:
ARM::tADDspi952
;
228
1.32k
    ExtraBits = 7;
229
1.32k
    ExtraScale = 4;
230
1.32k
  } else 
if (420
isARMLowRegister(DestReg)420
) {
231
420
    if (BaseReg == ARM::SP) {
232
308
      // sp -> low
233
308
      assert(!isSub && "Thumb1 does not have tSUBrSPi");
234
308
      CopyOpc = ARM::tADDrSPi;
235
308
      CopyBits = 8;
236
308
      CopyScale = 4;
237
308
    } else 
if (112
DestReg == BaseReg112
) {
238
0
      // low -> same low
239
0
      // Already in right reg, no copy needed
240
112
    } else if (isARMLowRegister(BaseReg)) {
241
112
      // low -> different low
242
112
      CopyOpc = isSub ? 
ARM::tSUBi380
:
ARM::tADDi332
;
243
112
      CopyBits = 3;
244
112
      CopyNeedsCC = true;
245
112
    } else {
246
0
      // high -> low
247
0
      CopyOpc = ARM::tMOVr;
248
0
      CopyBits = 0;
249
0
    }
250
420
    ExtraOpc = isSub ? 
ARM::tSUBi880
:
ARM::tADDi8340
;
251
420
    ExtraBits = 8;
252
420
    ExtraNeedsCC = true;
253
420
  } else /* DestReg is high */ {
254
0
    if (DestReg == BaseReg) {
255
0
      // high -> same high
256
0
      // Already in right reg, no copy needed
257
0
    } else {
258
0
      // {low,high,sp} -> high
259
0
      CopyOpc = ARM::tMOVr;
260
0
      CopyBits = 0;
261
0
    }
262
0
    ExtraOpc = 0;
263
0
  }
264
1.74k
265
1.74k
  // We could handle an unaligned immediate with an unaligned copy instruction
266
1.74k
  // and an aligned extra instruction, but this case is not currently needed.
267
1.74k
  assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
268
1.74k
         "Unaligned offset, but all instructions require alignment");
269
1.74k
270
1.74k
  unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
271
1.74k
  // If we would emit the copy with an immediate of 0, just use tMOVr.
272
1.74k
  if (CopyOpc && 
Bytes < CopyScale420
) {
273
65
    CopyOpc = ARM::tMOVr;
274
65
    CopyScale = 1;
275
65
    CopyNeedsCC = false;
276
65
    CopyRange = 0;
277
65
  }
278
1.74k
  unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale; // per instruction
279
1.74k
  unsigned RequiredCopyInstrs = CopyOpc ? 
1420
:
01.32k
;
280
1.74k
  unsigned RangeAfterCopy = (CopyRange > Bytes) ? 
0232
:
(Bytes - CopyRange)1.51k
;
281
1.74k
282
1.74k
  // We could handle this case when the copy instruction does not require an
283
1.74k
  // aligned immediate, but we do not currently do this.
284
1.74k
  assert(RangeAfterCopy % ExtraScale == 0 &&
285
1.74k
         "Extra instruction requires immediate to be aligned");
286
1.74k
287
1.74k
  unsigned RequiredExtraInstrs;
288
1.74k
  if (ExtraRange)
289
1.74k
    RequiredExtraInstrs = alignTo(RangeAfterCopy, ExtraRange) / ExtraRange;
290
0
  else if (RangeAfterCopy > 0)
291
0
    // We need an extra instruction but none is available
292
0
    RequiredExtraInstrs = 1000000;
293
0
  else
294
0
    RequiredExtraInstrs = 0;
295
1.74k
  unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
296
1.74k
  unsigned Threshold = (DestReg == ARM::SP) ? 
31.32k
:
2420
;
297
1.74k
298
1.74k
  // Use a constant pool, if the sequence of ADDs/SUBs is too expensive.
299
1.74k
  if (RequiredInstrs > Threshold) {
300
12
    emitThumbRegPlusImmInReg(MBB, MBBI, dl,
301
12
                             DestReg, BaseReg, NumBytes, true,
302
12
                             TII, MRI, MIFlags);
303
12
    return;
304
12
  }
305
1.73k
306
1.73k
  // Emit zero or one copy instructions
307
1.73k
  if (CopyOpc) {
308
412
    unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
309
412
    Bytes -= CopyImm * CopyScale;
310
412
311
412
    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
312
412
    if (CopyNeedsCC)
313
103
      MIB = MIB.add(t1CondCodeOp());
314
412
    MIB.addReg(BaseReg, RegState::Kill);
315
412
    if (CopyOpc != ARM::tMOVr) {
316
347
      MIB.addImm(CopyImm);
317
347
    }
318
412
    MIB.setMIFlags(MIFlags).add(predOps(ARMCC::AL));
319
412
320
412
    BaseReg = DestReg;
321
412
  }
322
1.73k
323
1.73k
  // Emit zero or more in-place add/sub instructions
324
2.79k
  while (Bytes) {
325
1.05k
    unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
326
1.05k
    Bytes -= ExtraImm * ExtraScale;
327
1.05k
328
1.05k
    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
329
1.05k
    if (ExtraNeedsCC)
330
112
      MIB = MIB.add(t1CondCodeOp());
331
1.05k
    MIB.addReg(BaseReg)
332
1.05k
       .addImm(ExtraImm)
333
1.05k
       .add(predOps(ARMCC::AL))
334
1.05k
       .setMIFlags(MIFlags);
335
1.05k
  }
336
1.73k
}
337
338
18
static void removeOperands(MachineInstr &MI, unsigned i) {
339
18
  unsigned Op = i;
340
54
  for (unsigned e = MI.getNumOperands(); i != e; 
++i36
)
341
36
    MI.RemoveOperand(Op);
342
18
}
343
344
/// convertToNonSPOpcode - Change the opcode to the non-SP version, because
345
/// we're replacing the frame index with a non-SP register.
346
3.66k
static unsigned convertToNonSPOpcode(unsigned Opcode) {
347
3.66k
  switch (Opcode) {
348
3.66k
  case ARM::tLDRspi:
349
2.42k
    return ARM::tLDRi;
350
3.66k
351
3.66k
  case ARM::tSTRspi:
352
1.23k
    return ARM::tSTRi;
353
0
  }
354
0
355
0
  return Opcode;
356
0
}
357
358
bool ThumbRegisterInfo::rewriteFrameIndex(MachineBasicBlock::iterator II,
359
                                          unsigned FrameRegIdx,
360
                                          unsigned FrameReg, int &Offset,
361
4.02k
                                          const ARMBaseInstrInfo &TII) const {
362
4.02k
  MachineInstr &MI = *II;
363
4.02k
  MachineBasicBlock &MBB = *MI.getParent();
364
4.02k
  assert(MBB.getParent()->getSubtarget<ARMSubtarget>().isThumb1Only() &&
365
4.02k
         "This isn't needed for thumb2!");
366
4.02k
  DebugLoc dl = MI.getDebugLoc();
367
4.02k
  MachineInstrBuilder MIB(*MBB.getParent(), &MI);
368
4.02k
  unsigned Opcode = MI.getOpcode();
369
4.02k
  const MCInstrDesc &Desc = MI.getDesc();
370
4.02k
  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
371
4.02k
372
4.02k
  if (Opcode == ARM::tADDframe) {
373
340
    Offset += MI.getOperand(FrameRegIdx+1).getImm();
374
340
    unsigned DestReg = MI.getOperand(0).getReg();
375
340
376
340
    emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
377
340
                              *this);
378
340
    MBB.erase(II);
379
340
    return true;
380
3.68k
  } else {
381
3.68k
    if (AddrMode != ARMII::AddrModeT1_s)
382
3.68k
      
llvm_unreachable0
("Unsupported addressing mode!");
383
3.68k
384
3.68k
    unsigned ImmIdx = FrameRegIdx + 1;
385
3.68k
    int InstrOffs = MI.getOperand(ImmIdx).getImm();
386
3.68k
    unsigned NumBits = (FrameReg == ARM::SP) ? 
83.54k
:
5131
;
387
3.68k
    unsigned Scale = 4;
388
3.68k
389
3.68k
    Offset += InstrOffs * Scale;
390
3.68k
    assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
391
3.68k
392
3.68k
    // Common case: small offset, fits into instruction.
393
3.68k
    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
394
3.68k
    int ImmedOffset = Offset / Scale;
395
3.68k
    unsigned Mask = (1 << NumBits) - 1;
396
3.68k
397
3.68k
    if ((unsigned)Offset <= Mask * Scale) {
398
3.66k
      // Replace the FrameIndex with the frame register (e.g., sp).
399
3.66k
      MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
400
3.66k
      ImmOp.ChangeToImmediate(ImmedOffset);
401
3.66k
402
3.66k
      // If we're using a register where sp was stored, convert the instruction
403
3.66k
      // to the non-SP version.
404
3.66k
      unsigned NewOpc = convertToNonSPOpcode(Opcode);
405
3.66k
      if (NewOpc != Opcode && FrameReg != ARM::SP)
406
129
        MI.setDesc(TII.get(NewOpc));
407
3.66k
408
3.66k
      return true;
409
3.66k
    }
410
18
411
18
    NumBits = 5;
412
18
    Mask = (1 << NumBits) - 1;
413
18
414
18
    // If this is a thumb spill / restore, we will be using a constpool load to
415
18
    // materialize the offset.
416
18
    if (Opcode == ARM::tLDRspi || 
Opcode == ARM::tSTRspi16
) {
417
18
      ImmOp.ChangeToImmediate(0);
418
18
    } else {
419
0
      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
420
0
      ImmedOffset = ImmedOffset & Mask;
421
0
      ImmOp.ChangeToImmediate(ImmedOffset);
422
0
      Offset &= ~(Mask * Scale);
423
0
    }
424
18
  }
425
4.02k
426
4.02k
  
return Offset == 018
;
427
4.02k
}
428
429
void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
430
28
                                           int64_t Offset) const {
431
28
  const MachineFunction &MF = *MI.getParent()->getParent();
432
28
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
433
28
  if (!STI.isThumb1Only())
434
15
    return ARMBaseRegisterInfo::resolveFrameIndex(MI, BaseReg, Offset);
435
13
436
13
  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
437
13
  int Off = Offset; // ARM doesn't need the general 64-bit offsets
438
13
  unsigned i = 0;
439
13
440
26
  while (!MI.getOperand(i).isFI()) {
441
13
    ++i;
442
13
    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
443
13
  }
444
13
  bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
445
13
  assert (Done && "Unable to resolve frame index!");
446
13
  (void)Done;
447
13
}
448
449
void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
450
                                            int SPAdj, unsigned FIOperandNum,
451
54.5k
                                            RegScavenger *RS) const {
452
54.5k
  MachineInstr &MI = *II;
453
54.5k
  MachineBasicBlock &MBB = *MI.getParent();
454
54.5k
  MachineFunction &MF = *MBB.getParent();
455
54.5k
  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
456
54.5k
  if (!STI.isThumb1Only())
457
50.5k
    return ARMBaseRegisterInfo::eliminateFrameIndex(II, SPAdj, FIOperandNum,
458
50.5k
                                                    RS);
459
4.00k
460
4.00k
  unsigned VReg = 0;
461
4.00k
  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
462
4.00k
  DebugLoc dl = MI.getDebugLoc();
463
4.00k
  MachineInstrBuilder MIB(*MBB.getParent(), &MI);
464
4.00k
465
4.00k
  unsigned FrameReg;
466
4.00k
  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
467
4.00k
  const ARMFrameLowering *TFI = getFrameLowering(MF);
468
4.00k
  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
469
4.00k
470
4.00k
  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
471
4.00k
  // call frame setup/destroy instructions have already been eliminated.  That
472
4.00k
  // means the stack pointer cannot be used to access the emergency spill slot
473
4.00k
  // when !hasReservedCallFrame().
474
#ifndef NDEBUG
475
  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
476
    assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
477
           "Cannot use SP to access the emergency spill slot in "
478
           "functions without a reserved call frame");
479
    assert(!MF.getFrameInfo().hasVarSizedObjects() &&
480
           "Cannot use SP to access the emergency spill slot in "
481
           "functions with variable sized frame objects");
482
  }
483
#endif // NDEBUG
484
485
4.00k
  // Special handling of dbg_value instructions.
486
4.00k
  if (MI.isDebugValue()) {
487
0
    MI.getOperand(FIOperandNum).  ChangeToRegister(FrameReg, false /*isDef*/);
488
0
    MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
489
0
    return;
490
0
  }
491
4.00k
492
4.00k
  // Modify MI as necessary to handle as much of 'Offset' as possible
493
4.00k
  assert(MF.getInfo<ARMFunctionInfo>()->isThumbFunction() &&
494
4.00k
         "This eliminateFrameIndex only supports Thumb1!");
495
4.00k
  if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
496
3.98k
    return;
497
18
498
18
  // If we get here, the immediate doesn't fit into the instruction.  We folded
499
18
  // as much as possible above, handle the rest, providing a register that is
500
18
  // SP+LargeImm.
501
18
  assert(Offset && "This code isn't needed if offset already handled!");
502
18
503
18
  unsigned Opcode = MI.getOpcode();
504
18
505
18
  // Remove predicate first.
506
18
  int PIdx = MI.findFirstPredOperandIdx();
507
18
  if (PIdx != -1)
508
18
    removeOperands(MI, PIdx);
509
18
510
18
  if (MI.mayLoad()) {
511
2
    // Use the destination register to materialize sp + offset.
512
2
    unsigned TmpReg = MI.getOperand(0).getReg();
513
2
    bool UseRR = false;
514
2
    if (Opcode == ARM::tLDRspi) {
515
2
      if (FrameReg == ARM::SP || 
STI.genExecuteOnly()0
)
516
2
        emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
517
2
                                 Offset, false, TII, *this);
518
0
      else {
519
0
        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
520
0
        UseRR = true;
521
0
      }
522
2
    } else {
523
0
      emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
524
0
                                *this);
525
0
    }
526
2
527
2
    MI.setDesc(TII.get(UseRR ? 
ARM::tLDRr0
: ARM::tLDRi));
528
2
    MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
529
2
    if (UseRR)
530
0
      // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
531
0
      // register. The offset is already handled in the vreg value.
532
0
      MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
533
0
                                                     false);
534
16
  } else if (MI.mayStore()) {
535
16
      VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
536
16
      bool UseRR = false;
537
16
538
16
      if (Opcode == ARM::tSTRspi) {
539
16
        if (FrameReg == ARM::SP || 
STI.genExecuteOnly()2
)
540
14
          emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
541
14
                                   Offset, false, TII, *this);
542
2
        else {
543
2
          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
544
2
          UseRR = true;
545
2
        }
546
16
      } else
547
0
        emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
548
0
                                  *this);
549
16
      MI.setDesc(TII.get(UseRR ? 
ARM::tSTRr2
:
ARM::tSTRi14
));
550
16
      MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
551
16
      if (UseRR)
552
2
        // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
553
2
        // register. The offset is already handled in the vreg value.
554
2
        MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
555
2
                                                       false);
556
16
  } else {
557
0
    llvm_unreachable("Unexpected opcode!");
558
0
  }
559
18
560
18
  // Add predicate back if it's needed.
561
18
  if (MI.isPredicable())
562
18
    MIB.add(predOps(ARMCC::AL));
563
18
}
564
565
bool
566
9.77k
ThumbRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
567
9.77k
  if (MF.getSubtarget<ARMSubtarget>().isThumb1Only()) {
568
189
    // For Thumb1, the emergency spill slot must be some small positive
569
189
    // offset from the base/stack pointer.
570
189
    return false;
571
189
  }
572
9.58k
  // For Thumb2, put the emergency spill slot next to FP.
573
9.58k
  return true;
574
9.58k
}