Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
Line
Count
Source (jump to first uncovered line)
1
//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
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//===----------------------------------------------------------------------===//
8
//
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// This file contains small standalone helper functions and enum definitions for
10
// the ARM target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
12
// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#define LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H
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#include "llvm/ADT/StringSwitch.h"
20
#include "llvm/Support/ErrorHandling.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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24
namespace llvm {
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// Enums corresponding to ARM condition codes
27
namespace ARMCC {
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// The CondCodes constants map directly to the 4-bit encoding of the
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// condition field for predicated instructions.
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enum CondCodes { // Meaning (integer)          Meaning (floating-point)
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  EQ,            // Equal                      Equal
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  NE,            // Not equal                  Not equal, or unordered
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  HS,            // Carry set                  >, ==, or unordered
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  LO,            // Carry clear                Less than
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  MI,            // Minus, negative            Less than
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  PL,            // Plus, positive or zero     >, ==, or unordered
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  VS,            // Overflow                   Unordered
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  VC,            // No overflow                Not unordered
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  HI,            // Unsigned higher            Greater than, or unordered
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  LS,            // Unsigned lower or same     Less than or equal
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  GE,            // Greater than or equal      Greater than or equal
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  LT,            // Less than                  Less than, or unordered
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  GT,            // Greater than               Greater than
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  LE,            // Less than or equal         <, ==, or unordered
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  AL             // Always (unconditional)     Always (unconditional)
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};
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48
402k
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
402k
  switch (CC) {
50
402k
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
402k
  
case EQ: return NE136k
;
52
402k
  
case NE: return EQ143k
;
53
402k
  
case HS: return LO22.0k
;
54
402k
  
case LO: return HS23.4k
;
55
402k
  
case MI: return PL2.68k
;
56
402k
  
case PL: return MI3.10k
;
57
402k
  
case VS: return VC884
;
58
402k
  
case VC: return VS701
;
59
402k
  
case HI: return LS19.9k
;
60
402k
  
case LS: return HI18.2k
;
61
402k
  
case GE: return LT12.9k
;
62
402k
  
case LT: return GE12.8k
;
63
402k
  
case GT: return LE3.34k
;
64
402k
  
case LE: return GT2.40k
;
65
402k
  }
66
402k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
ARMBaseInstrInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
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Count
Source
48
391k
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
391k
  switch (CC) {
50
391k
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
391k
  
case EQ: return NE133k
;
52
391k
  
case NE: return EQ139k
;
53
391k
  
case HS: return LO21.5k
;
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391k
  
case LO: return HS22.4k
;
55
391k
  
case MI: return PL2.36k
;
56
391k
  
case PL: return MI2.50k
;
57
391k
  
case VS: return VC698
;
58
391k
  
case VC: return VS688
;
59
391k
  
case HI: return LS19.3k
;
60
391k
  
case LS: return HI17.8k
;
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391k
  
case GE: return LT12.8k
;
62
391k
  
case LT: return GE12.6k
;
63
391k
  
case GT: return LE3.13k
;
64
391k
  
case LE: return GT2.28k
;
65
391k
  }
66
391k
}
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
ARMConstantIslandPass.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
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Count
Source
48
51
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
51
  switch (CC) {
50
51
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
51
  
case EQ: return NE28
;
52
51
  
case NE: return EQ13
;
53
51
  
case HS: return LO2
;
54
51
  
case LO: return HS0
;
55
51
  
case MI: return PL0
;
56
51
  
case PL: return MI0
;
57
51
  
case VS: return VC0
;
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51
  
case VC: return VS0
;
59
51
  
case HI: return LS6
;
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51
  
case LS: return HI0
;
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51
  
case GE: return LT0
;
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51
  
case LT: return GE2
;
63
51
  
case GT: return LE0
;
64
51
  
case LE: return GT0
;
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  }
66
51
}
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
ARMISelLowering.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
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Source
48
83
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
83
  switch (CC) {
50
83
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
83
  
case EQ: return NE0
;
52
83
  
case NE: return EQ0
;
53
83
  
case HS: return LO27
;
54
83
  
case LO: return HS0
;
55
83
  
case MI: return PL50
;
56
83
  
case PL: return MI0
;
57
83
  
case VS: return VC0
;
58
83
  
case VC: return VS6
;
59
83
  
case HI: return LS0
;
60
83
  
case LS: return HI0
;
61
83
  
case GE: return LT0
;
62
83
  
case LT: return GE0
;
63
83
  
case GT: return LE0
;
64
83
  
case LE: return GT0
;
65
83
  }
66
83
}
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Thumb2ITBlockPass.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
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Count
Source
48
10.4k
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
10.4k
  switch (CC) {
50
10.4k
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
10.4k
  
case EQ: return NE2.64k
;
52
10.4k
  
case NE: return EQ4.11k
;
53
10.4k
  
case HS: return LO414
;
54
10.4k
  
case LO: return HS835
;
55
10.4k
  
case MI: return PL249
;
56
10.4k
  
case PL: return MI588
;
57
10.4k
  
case VS: return VC178
;
58
10.4k
  
case VC: return VS7
;
59
10.4k
  
case HI: return LS599
;
60
10.4k
  
case LS: return HI338
;
61
10.4k
  
case GE: return LT102
;
62
10.4k
  
case LT: return GE153
;
63
10.4k
  
case GT: return LE154
;
64
10.4k
  
case LE: return GT117
;
65
10.4k
  }
66
10.4k
}
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
ARMAsmParser.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
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Count
Source
48
380
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
380
  switch (CC) {
50
380
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
380
  
case EQ: return NE76
;
52
380
  
case NE: return EQ40
;
53
380
  
case HS: return LO16
;
54
380
  
case LO: return HS72
;
55
380
  
case MI: return PL8
;
56
380
  
case PL: return MI6
;
57
380
  
case VS: return VC8
;
58
380
  
case VC: return VS0
;
59
380
  
case HI: return LS6
;
60
380
  
case LS: return HI56
;
61
380
  
case GE: return LT27
;
62
380
  
case LT: return GE9
;
63
380
  
case GT: return LE50
;
64
380
  
case LE: return GT6
;
65
380
  }
66
380
}
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
ARMInstPrinter.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Line
Count
Source
48
56
inline static CondCodes getOppositeCondition(CondCodes CC) {
49
56
  switch (CC) {
50
56
  
default: 0
llvm_unreachable0
("Unknown condition code");
51
56
  
case EQ: return NE0
;
52
56
  
case NE: return EQ8
;
53
56
  
case HS: return LO8
;
54
56
  
case LO: return HS24
;
55
56
  
case MI: return PL16
;
56
56
  
case PL: return MI0
;
57
56
  
case VS: return VC0
;
58
56
  
case VC: return VS0
;
59
56
  
case HI: return LS0
;
60
56
  
case LS: return HI0
;
61
56
  
case GE: return LT0
;
62
56
  
case LT: return GE0
;
63
56
  
case GT: return LE0
;
64
56
  
case LE: return GT0
;
65
56
  }
66
56
}
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBaseInfo.cpp:llvm::ARMCC::getOppositeCondition(llvm::ARMCC::CondCodes)
67
} // end namespace ARMCC
68
69
namespace ARMVCC {
70
  enum VPTCodes {
71
    None = 0,
72
    Then,
73
    Else
74
  };
75
}
76
77
170
inline static const char *ARMVPTPredToString(ARMVCC::VPTCodes CC) {
78
170
  switch (CC) {
79
170
  
case ARMVCC::None: return "none"0
;
80
170
  
case ARMVCC::Then: return "t"97
;
81
170
  
case ARMVCC::Else: return "e"73
;
82
0
  }
83
0
  llvm_unreachable("Unknown VPT code");
84
0
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMAsmParser.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
ARMInstPrinter.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Line
Count
Source
77
170
inline static const char *ARMVPTPredToString(ARMVCC::VPTCodes CC) {
78
170
  switch (CC) {
79
170
  
case ARMVCC::None: return "none"0
;
80
170
  
case ARMVCC::Then: return "t"97
;
81
170
  
case ARMVCC::Else: return "e"73
;
82
0
  }
83
0
  llvm_unreachable("Unknown VPT code");
84
0
}
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
Unexecuted instantiation: ARMBaseInfo.cpp:llvm::ARMVPTPredToString(llvm::ARMVCC::VPTCodes)
85
86
2.08k
inline static unsigned ARMVectorCondCodeFromString(StringRef CC) {
87
2.08k
  return StringSwitch<unsigned>(CC.lower())
88
2.08k
    .Case("t", ARMVCC::Then)
89
2.08k
    .Case("e", ARMVCC::Else)
90
2.08k
    .Default(~0U);
91
2.08k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
ARMAsmParser.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Line
Count
Source
86
2.08k
inline static unsigned ARMVectorCondCodeFromString(StringRef CC) {
87
2.08k
  return StringSwitch<unsigned>(CC.lower())
88
2.08k
    .Case("t", ARMVCC::Then)
89
2.08k
    .Case("e", ARMVCC::Else)
90
2.08k
    .Default(~0U);
91
2.08k
}
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseInfo.cpp:llvm::ARMVectorCondCodeFromString(llvm::StringRef)
92
93
14.2k
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
94
14.2k
  switch (CC) {
95
14.2k
  
case ARMCC::EQ: return "eq"2.86k
;
96
14.2k
  
case ARMCC::NE: return "ne"2.83k
;
97
14.2k
  
case ARMCC::HS: return "hs"318
;
98
14.2k
  
case ARMCC::LO: return "lo"458
;
99
14.2k
  
case ARMCC::MI: return "mi"291
;
100
14.2k
  
case ARMCC::PL: return "pl"202
;
101
14.2k
  
case ARMCC::VS: return "vs"84
;
102
14.2k
  
case ARMCC::VC: return "vc"57
;
103
14.2k
  
case ARMCC::HI: return "hi"470
;
104
14.2k
  
case ARMCC::LS: return "ls"217
;
105
14.2k
  
case ARMCC::GE: return "ge"4.77k
;
106
14.2k
  
case ARMCC::LT: return "lt"544
;
107
14.2k
  
case ARMCC::GT: return "gt"695
;
108
14.2k
  
case ARMCC::LE: return "le"378
;
109
14.2k
  
case ARMCC::AL: return "al"16
;
110
0
  }
111
0
  llvm_unreachable("Unknown condition code");
112
0
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
ARMAsmParser.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Line
Count
Source
93
48
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
94
48
  switch (CC) {
95
48
  
case ARMCC::EQ: return "eq"22
;
96
48
  
case ARMCC::NE: return "ne"12
;
97
48
  
case ARMCC::HS: return "hs"0
;
98
48
  
case ARMCC::LO: return "lo"0
;
99
48
  
case ARMCC::MI: return "mi"0
;
100
48
  
case ARMCC::PL: return "pl"0
;
101
48
  
case ARMCC::VS: return "vs"0
;
102
48
  
case ARMCC::VC: return "vc"0
;
103
48
  
case ARMCC::HI: return "hi"0
;
104
48
  
case ARMCC::LS: return "ls"0
;
105
48
  
case ARMCC::GE: return "ge"0
;
106
48
  
case ARMCC::LT: return "lt"0
;
107
48
  
case ARMCC::GT: return "gt"10
;
108
48
  
case ARMCC::LE: return "le"2
;
109
48
  
case ARMCC::AL: return "al"2
;
110
0
  }
111
0
  llvm_unreachable("Unknown condition code");
112
0
}
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
ARMInstPrinter.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Line
Count
Source
93
14.1k
inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
94
14.1k
  switch (CC) {
95
14.1k
  
case ARMCC::EQ: return "eq"2.84k
;
96
14.1k
  
case ARMCC::NE: return "ne"2.82k
;
97
14.1k
  
case ARMCC::HS: return "hs"318
;
98
14.1k
  
case ARMCC::LO: return "lo"458
;
99
14.1k
  
case ARMCC::MI: return "mi"291
;
100
14.1k
  
case ARMCC::PL: return "pl"202
;
101
14.1k
  
case ARMCC::VS: return "vs"84
;
102
14.1k
  
case ARMCC::VC: return "vc"57
;
103
14.1k
  
case ARMCC::HI: return "hi"470
;
104
14.1k
  
case ARMCC::LS: return "ls"217
;
105
14.1k
  
case ARMCC::GE: return "ge"4.77k
;
106
14.1k
  
case ARMCC::LT: return "lt"544
;
107
14.1k
  
case ARMCC::GT: return "gt"685
;
108
14.1k
  
case ARMCC::LE: return "le"376
;
109
14.1k
  
case ARMCC::AL: return "al"14
;
110
0
  }
111
0
  llvm_unreachable("Unknown condition code");
112
0
}
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
Unexecuted instantiation: ARMBaseInfo.cpp:llvm::ARMCondCodeToString(llvm::ARMCC::CondCodes)
113
114
40.5k
inline static unsigned ARMCondCodeFromString(StringRef CC) {
115
40.5k
  return StringSwitch<unsigned>(CC.lower())
116
40.5k
    .Case("eq", ARMCC::EQ)
117
40.5k
    .Case("ne", ARMCC::NE)
118
40.5k
    .Case("hs", ARMCC::HS)
119
40.5k
    .Case("cs", ARMCC::HS)
120
40.5k
    .Case("lo", ARMCC::LO)
121
40.5k
    .Case("cc", ARMCC::LO)
122
40.5k
    .Case("mi", ARMCC::MI)
123
40.5k
    .Case("pl", ARMCC::PL)
124
40.5k
    .Case("vs", ARMCC::VS)
125
40.5k
    .Case("vc", ARMCC::VC)
126
40.5k
    .Case("hi", ARMCC::HI)
127
40.5k
    .Case("ls", ARMCC::LS)
128
40.5k
    .Case("ge", ARMCC::GE)
129
40.5k
    .Case("lt", ARMCC::LT)
130
40.5k
    .Case("gt", ARMCC::GT)
131
40.5k
    .Case("le", ARMCC::LE)
132
40.5k
    .Case("al", ARMCC::AL)
133
40.5k
    .Default(~0U);
134
40.5k
}
Unexecuted instantiation: A15SDOptimizer.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMAsmPrinter.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseInstrInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseRegisterInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBasicBlockInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCallingConv.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCallLowering.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMCodeGenPrepare.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMConstantIslandPass.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMExpandPseudoInsts.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMFastISel.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMFrameLowering.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMHazardRecognizer.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstructionSelector.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMISelDAGToDAG.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMISelLowering.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstrInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLegalizerInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMParallelDSP.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLoadStoreOptimizer.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMLowOverheadLoops.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCInstLower.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMachineFunctionInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMacroFusion.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMRegisterInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMOptimizeBarriersPass.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMRegisterBankInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMSelectionDAGInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMSubtarget.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetMachine.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetObjectFile.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMTargetTransformInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: MLxExpansionPass.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb1FrameLowering.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb1InstrInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ThumbRegisterInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2ITBlockPass.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2InstrInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: Thumb2SizeReduction.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
ARMAsmParser.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Line
Count
Source
114
40.5k
inline static unsigned ARMCondCodeFromString(StringRef CC) {
115
40.5k
  return StringSwitch<unsigned>(CC.lower())
116
40.5k
    .Case("eq", ARMCC::EQ)
117
40.5k
    .Case("ne", ARMCC::NE)
118
40.5k
    .Case("hs", ARMCC::HS)
119
40.5k
    .Case("cs", ARMCC::HS)
120
40.5k
    .Case("lo", ARMCC::LO)
121
40.5k
    .Case("cc", ARMCC::LO)
122
40.5k
    .Case("mi", ARMCC::MI)
123
40.5k
    .Case("pl", ARMCC::PL)
124
40.5k
    .Case("vs", ARMCC::VS)
125
40.5k
    .Case("vc", ARMCC::VC)
126
40.5k
    .Case("hi", ARMCC::HI)
127
40.5k
    .Case("ls", ARMCC::LS)
128
40.5k
    .Case("ge", ARMCC::GE)
129
40.5k
    .Case("lt", ARMCC::LT)
130
40.5k
    .Case("gt", ARMCC::GT)
131
40.5k
    .Case("le", ARMCC::LE)
132
40.5k
    .Case("al", ARMCC::AL)
133
40.5k
    .Default(~0U);
134
40.5k
}
Unexecuted instantiation: ARMELFStreamer.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMInstPrinter.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMachObjectWriter.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCCodeEmitter.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMMCTargetDesc.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
Unexecuted instantiation: ARMBaseInfo.cpp:llvm::ARMCondCodeFromString(llvm::StringRef)
135
136
// System Registers
137
namespace ARMSysReg {
138
  struct MClassSysReg {
139
    const char *Name;
140
    uint16_t M1Encoding12;
141
    uint16_t M2M3Encoding8;
142
    uint16_t Encoding;
143
    FeatureBitset FeaturesRequired;
144
145
    // return true if FeaturesRequired are all present in ActiveFeatures
146
296
    bool hasRequiredFeatures(FeatureBitset ActiveFeatures) const {
147
296
      return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
148
296
    }
149
150
    // returns true if TestFeatures are all present in FeaturesRequired
151
102
    bool isInRequiredFeatures(FeatureBitset TestFeatures) const {
152
102
      return (FeaturesRequired & TestFeatures) == TestFeatures;
153
102
    }
154
  };
155
156
  #define GET_MCLASSSYSREG_DECL
157
  #include "ARMGenSystemRegister.inc"
158
159
  // lookup system register using 12-bit SYSm value.
160
  // Note: the search is uniqued using M1 mask
161
  const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
162
163
  // returns APSR with _<bits> qualifier.
164
  // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
165
  const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
166
167
  // lookup system registers using 8-bit SYSm value
168
  const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
169
170
} // end namespace ARMSysReg
171
172
// Banked Registers
173
namespace ARMBankedReg {
174
  struct BankedReg {
175
    const char *Name;
176
    uint16_t Encoding;
177
  };
178
  #define GET_BANKEDREG_DECL
179
  #include "ARMGenSystemRegister.inc"
180
} // end namespace ARMBankedReg
181
182
} // end namespace llvm
183
184
#endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H