Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
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1
//===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
// This pass replaces transfer instructions by combine instructions.
9
// We walk along a basic block and look for two combinable instructions and try
10
// to move them together. If we can move them next to each other we do so and
11
// replace them with a combine instruction.
12
//===----------------------------------------------------------------------===//
13
#include "HexagonInstrInfo.h"
14
#include "HexagonSubtarget.h"
15
#include "llvm/ADT/DenseMap.h"
16
#include "llvm/ADT/DenseSet.h"
17
#include "llvm/CodeGen/MachineBasicBlock.h"
18
#include "llvm/CodeGen/MachineFunction.h"
19
#include "llvm/CodeGen/MachineFunctionPass.h"
20
#include "llvm/CodeGen/MachineInstr.h"
21
#include "llvm/CodeGen/MachineInstrBuilder.h"
22
#include "llvm/CodeGen/Passes.h"
23
#include "llvm/CodeGen/TargetRegisterInfo.h"
24
#include "llvm/PassSupport.h"
25
#include "llvm/Support/CodeGen.h"
26
#include "llvm/Support/CommandLine.h"
27
#include "llvm/Support/Debug.h"
28
#include "llvm/Support/raw_ostream.h"
29
30
using namespace llvm;
31
32
#define DEBUG_TYPE "hexagon-copy-combine"
33
34
static
35
cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
36
                                 cl::Hidden, cl::ZeroOrMore,
37
                                 cl::init(false),
38
                                 cl::desc("Disable merging into combines"));
39
static
40
cl::opt<bool> IsConst64Disabled("disable-const64",
41
                                 cl::Hidden, cl::ZeroOrMore,
42
                                 cl::init(false),
43
                                 cl::desc("Disable generation of const64"));
44
static
45
cl::opt<unsigned>
46
MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
47
                   cl::Hidden, cl::init(4),
48
                   cl::desc("Maximum distance between a tfr feeding a store we "
49
                            "consider the store still to be newifiable"));
50
51
namespace llvm {
52
  FunctionPass *createHexagonCopyToCombine();
53
  void initializeHexagonCopyToCombinePass(PassRegistry&);
54
}
55
56
57
namespace {
58
59
class HexagonCopyToCombine : public MachineFunctionPass  {
60
  const HexagonInstrInfo *TII;
61
  const TargetRegisterInfo *TRI;
62
  const HexagonSubtarget *ST;
63
  bool ShouldCombineAggressively;
64
65
  DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
66
  SmallVector<MachineInstr *, 8> DbgMItoMove;
67
68
public:
69
  static char ID;
70
71
919
  HexagonCopyToCombine() : MachineFunctionPass(ID) {
72
919
    initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
73
919
  }
74
75
912
  void getAnalysisUsage(AnalysisUsage &AU) const override {
76
912
    MachineFunctionPass::getAnalysisUsage(AU);
77
912
  }
78
79
5.88k
  StringRef getPassName() const override {
80
5.88k
    return "Hexagon Copy-To-Combine Pass";
81
5.88k
  }
82
83
  bool runOnMachineFunction(MachineFunction &Fn) override;
84
85
912
  MachineFunctionProperties getRequiredProperties() const override {
86
912
    return MachineFunctionProperties().set(
87
912
        MachineFunctionProperties::Property::NoVRegs);
88
912
  }
89
90
private:
91
  MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
92
                             bool AllowC64);
93
94
  void findPotentialNewifiableTFRs(MachineBasicBlock &);
95
96
  void combine(MachineInstr &I1, MachineInstr &I2,
97
               MachineBasicBlock::iterator &MI, bool DoInsertAtI1,
98
               bool OptForSize);
99
100
  bool isSafeToMoveTogether(MachineInstr &I1, MachineInstr &I2,
101
                            unsigned I1DestReg, unsigned I2DestReg,
102
                            bool &DoInsertAtI1);
103
104
  void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
105
                     MachineOperand &HiOperand, MachineOperand &LoOperand);
106
107
  void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
108
                     MachineOperand &HiOperand, MachineOperand &LoOperand);
109
110
  void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
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                     MachineOperand &HiOperand, MachineOperand &LoOperand);
112
113
  void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
114
                     MachineOperand &HiOperand, MachineOperand &LoOperand);
115
116
  void emitConst64(MachineBasicBlock::iterator &Before, unsigned DestReg,
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                   MachineOperand &HiOperand, MachineOperand &LoOperand);
118
};
119
120
} // End anonymous namespace.
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122
char HexagonCopyToCombine::ID = 0;
123
124
INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
125
                "Hexagon Copy-To-Combine Pass", false, false)
126
127
static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
128
54.9k
                                 bool ShouldCombineAggressively) {
129
54.9k
  switch (MI.getOpcode()) {
130
54.9k
  case Hexagon::A2_tfr: {
131
1.48k
    // A COPY instruction can be combined if its arguments are IntRegs (32bit).
132
1.48k
    const MachineOperand &Op0 = MI.getOperand(0);
133
1.48k
    const MachineOperand &Op1 = MI.getOperand(1);
134
1.48k
    assert(Op0.isReg() && Op1.isReg());
135
1.48k
136
1.48k
    unsigned DestReg = Op0.getReg();
137
1.48k
    unsigned SrcReg = Op1.getReg();
138
1.48k
    return Hexagon::IntRegsRegClass.contains(DestReg) &&
139
1.48k
           Hexagon::IntRegsRegClass.contains(SrcReg);
140
54.9k
  }
141
54.9k
142
54.9k
  case Hexagon::A2_tfrsi: {
143
4.48k
    // A transfer-immediate can be combined if its argument is a signed 8bit
144
4.48k
    // value.
145
4.48k
    const MachineOperand &Op0 = MI.getOperand(0);
146
4.48k
    const MachineOperand &Op1 = MI.getOperand(1);
147
4.48k
    assert(Op0.isReg());
148
4.48k
149
4.48k
    unsigned DestReg = Op0.getReg();
150
4.48k
    // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
151
4.48k
    // workaround for an ABI bug that prevents GOT relocations on combine
152
4.48k
    // instructions
153
4.48k
    if (!Op1.isImm() && 
Op1.getTargetFlags() != HexagonII::MO_NO_FLAG1.97k
)
154
0
      return false;
155
4.48k
156
4.48k
    // Only combine constant extended A2_tfrsi if we are in aggressive mode.
157
4.48k
    bool NotExt = Op1.isImm() && 
isInt<8>(Op1.getImm())2.51k
;
158
4.48k
    return Hexagon::IntRegsRegClass.contains(DestReg) &&
159
4.48k
           (ShouldCombineAggressively || 
NotExt205
);
160
4.48k
  }
161
4.48k
162
4.48k
  case Hexagon::V6_vassign:
163
780
    return true;
164
4.48k
165
48.1k
  default:
166
48.1k
    break;
167
48.1k
  }
168
48.1k
169
48.1k
  return false;
170
48.1k
}
171
172
1.23k
template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
173
1.23k
  if (I.getOpcode() == Hexagon::TFRI64_V4 ||
174
1.23k
      I.getOpcode() == Hexagon::A2_tfrsi) {
175
818
    const MachineOperand &Op = I.getOperand(1);
176
818
    return !Op.isImm() || 
!isInt<N>(Op.getImm())511
;
177
818
  }
178
415
  return false;
179
415
}
HexagonCopyToCombine.cpp:bool isGreaterThanNBitTFRI<8u>(llvm::MachineInstr const&)
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Source
172
715
template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
173
715
  if (I.getOpcode() == Hexagon::TFRI64_V4 ||
174
715
      I.getOpcode() == Hexagon::A2_tfrsi) {
175
450
    const MachineOperand &Op = I.getOperand(1);
176
450
    return !Op.isImm() || 
!isInt<N>(Op.getImm())313
;
177
450
  }
178
265
  return false;
179
265
}
HexagonCopyToCombine.cpp:bool isGreaterThanNBitTFRI<6u>(llvm::MachineInstr const&)
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Count
Source
172
194
template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
173
194
  if (I.getOpcode() == Hexagon::TFRI64_V4 ||
174
194
      I.getOpcode() == Hexagon::A2_tfrsi) {
175
186
    const MachineOperand &Op = I.getOperand(1);
176
186
    return !Op.isImm() || 
!isInt<N>(Op.getImm())38
;
177
186
  }
178
8
  return false;
179
8
}
HexagonCopyToCombine.cpp:bool isGreaterThanNBitTFRI<16u>(llvm::MachineInstr const&)
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Count
Source
172
324
template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
173
324
  if (I.getOpcode() == Hexagon::TFRI64_V4 ||
174
324
      I.getOpcode() == Hexagon::A2_tfrsi) {
175
182
    const MachineOperand &Op = I.getOperand(1);
176
182
    return !Op.isImm() || 
!isInt<N>(Op.getImm())160
;
177
182
  }
178
142
  return false;
179
142
}
180
181
/// areCombinableOperations - Returns true if the two instruction can be merge
182
/// into a combine (ignoring register constraints).
183
static bool areCombinableOperations(const TargetRegisterInfo *TRI,
184
                                    MachineInstr &HighRegInst,
185
470
                                    MachineInstr &LowRegInst, bool AllowC64) {
186
470
  unsigned HiOpc = HighRegInst.getOpcode();
187
470
  unsigned LoOpc = LowRegInst.getOpcode();
188
470
189
940
  auto verifyOpc = [](unsigned Opc) -> void {
190
940
    switch (Opc) {
191
940
      case Hexagon::A2_tfr:
192
940
      case Hexagon::A2_tfrsi:
193
940
      case Hexagon::V6_vassign:
194
940
        break;
195
940
      default:
196
0
        llvm_unreachable("Unexpected opcode");
197
940
    }
198
940
  };
199
470
  verifyOpc(HiOpc);
200
470
  verifyOpc(LoOpc);
201
470
202
470
  if (HiOpc == Hexagon::V6_vassign || 
LoOpc == Hexagon::V6_vassign437
)
203
33
    return HiOpc == LoOpc;
204
437
205
437
  if (!AllowC64) {
206
408
    // There is no combine of two constant extended values.
207
408
    if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
208
408
        
isGreaterThanNBitTFRI<6>(LowRegInst)194
)
209
161
      return false;
210
276
  }
211
276
212
276
  // There is a combine of two constant extended values into CONST64,
213
276
  // provided both constants are true immediates.
214
276
  if (isGreaterThanNBitTFRI<16>(HighRegInst) &&
215
276
      
isGreaterThanNBitTFRI<16>(LowRegInst)36
)
216
6
    return (HighRegInst.getOperand(1).isImm() &&
217
6
            
LowRegInst.getOperand(1).isImm()3
);
218
270
219
270
  // There is no combine of two constant extended values, unless handled above
220
270
  // Make both 8-bit size checks to allow both combine (#,##) and combine(##,#)
221
270
  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
222
270
      
isGreaterThanNBitTFRI<8>(LowRegInst)37
)
223
0
    return false;
224
270
225
270
  return true;
226
270
}
227
228
653
static bool isEvenReg(unsigned Reg) {
229
653
  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
230
653
  if (Hexagon::IntRegsRegClass.contains(Reg))
231
607
    return (Reg - Hexagon::R0) % 2 == 0;
232
46
  if (Hexagon::HvxVRRegClass.contains(Reg))
233
46
    return (Reg - Hexagon::V0) % 2 == 0;
234
0
  llvm_unreachable("Invalid register");
235
0
}
236
237
3
static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
238
12
  for (unsigned I = 0, E = MI.getNumOperands(); I != E; 
++I9
) {
239
9
    MachineOperand &Op = MI.getOperand(I);
240
9
    if (!Op.isReg() || 
Op.getReg() != RegNotKilled7
||
!Op.isKill()3
)
241
6
      continue;
242
3
    Op.setIsKill(false);
243
3
  }
244
3
}
245
246
/// Returns true if it is unsafe to move a copy instruction from \p UseReg to
247
/// \p DestReg over the instruction \p MI.
248
static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
249
                                 unsigned DestReg,
250
262
                                 const TargetRegisterInfo *TRI) {
251
262
  return (UseReg && 
(MI.modifiesRegister(UseReg, TRI))135
) ||
252
262
         
MI.modifiesRegister(DestReg, TRI)234
||
MI.readsRegister(DestReg, TRI)141
||
253
262
         
MI.hasUnmodeledSideEffects()129
||
MI.isInlineAsm()125
||
254
262
         
MI.isMetaInstruction()125
;
255
262
}
256
257
398
static Register UseReg(const MachineOperand& MO) {
258
398
  return MO.isReg() ? 
MO.getReg()227
:
Register()171
;
259
398
}
260
261
/// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
262
/// that the two instructions can be paired in a combine.
263
bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
264
                                                MachineInstr &I2,
265
                                                unsigned I1DestReg,
266
                                                unsigned I2DestReg,
267
305
                                                bool &DoInsertAtI1) {
268
305
  unsigned I2UseReg = UseReg(I2.getOperand(1));
269
305
270
305
  // It is not safe to move I1 and I2 into one combine if I2 has a true
271
305
  // dependence on I1.
272
305
  if (I2UseReg && 
I1.modifiesRegister(I2UseReg, TRI)175
)
273
15
    return false;
274
290
275
290
  bool isSafe = true;
276
290
277
290
  // First try to move I2 towards I1.
278
290
  {
279
290
    // A reverse_iterator instantiated like below starts before I2, and I1
280
290
    // respectively.
281
290
    // Look at instructions I in between I2 and (excluding) I1.
282
290
    MachineBasicBlock::reverse_iterator I(I2),
283
290
      End = --(MachineBasicBlock::reverse_iterator(I1));
284
290
    // At 03 we got better results (dhrystone!) by being more conservative.
285
290
    if (!ShouldCombineAggressively)
286
22
      End = MachineBasicBlock::reverse_iterator(I1);
287
290
    // If I2 kills its operand and we move I2 over an instruction that also
288
290
    // uses I2's use reg we need to modify that (first) instruction to now kill
289
290
    // this reg.
290
290
    unsigned KilledOperand = 0;
291
290
    if (I2.killsRegister(I2UseReg))
292
71
      KilledOperand = I2UseReg;
293
290
    MachineInstr *KillingInstr = nullptr;
294
290
295
290
    for (; I != End; 
++I0
) {
296
93
      // If the intervening instruction I:
297
93
      //   * modifies I2's use reg
298
93
      //   * modifies I2's def reg
299
93
      //   * reads I2's def reg
300
93
      //   * or has unmodelled side effects
301
93
      // we can't move I2 across it.
302
93
      if (I->isDebugInstr())
303
0
        continue;
304
93
305
93
      if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
306
93
        isSafe = false;
307
93
        break;
308
93
      }
309
0
310
0
      // Update first use of the killed operand.
311
0
      if (!KillingInstr && KilledOperand &&
312
0
          I->readsRegister(KilledOperand, TRI))
313
0
        KillingInstr = &*I;
314
0
    }
315
290
    if (isSafe) {
316
197
      // Update the intermediate instruction to with the kill flag.
317
197
      if (KillingInstr) {
318
0
        bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
319
0
        (void)Added; // suppress compiler warning
320
0
        assert(Added && "Must successfully update kill flag");
321
0
        removeKillInfo(I2, KilledOperand);
322
0
      }
323
197
      DoInsertAtI1 = true;
324
197
      return true;
325
197
    }
326
93
  }
327
93
328
93
  // Try to move I1 towards I2.
329
93
  {
330
93
    // Look at instructions I in between I1 and (excluding) I2.
331
93
    MachineBasicBlock::iterator I(I1), End(I2);
332
93
    // At O3 we got better results (dhrystone) by being more conservative here.
333
93
    if (!ShouldCombineAggressively)
334
22
      End = std::next(MachineBasicBlock::iterator(I2));
335
93
    unsigned I1UseReg = UseReg(I1.getOperand(1));
336
93
    // Track killed operands. If we move across an instruction that kills our
337
93
    // operand, we need to update the kill information on the moved I1. It kills
338
93
    // the operand now.
339
93
    MachineInstr *KillingInstr = nullptr;
340
93
    unsigned KilledOperand = 0;
341
93
342
218
    while(++I != End) {
343
169
      MachineInstr &MI = *I;
344
169
      // If the intervening instruction MI:
345
169
      //   * modifies I1's use reg
346
169
      //   * modifies I1's def reg
347
169
      //   * reads I1's def reg
348
169
      //   * or has unmodelled side effects
349
169
      //   We introduce this special case because llvm has no api to remove a
350
169
      //   kill flag for a register (a removeRegisterKilled() analogous to
351
169
      //   addRegisterKilled) that handles aliased register correctly.
352
169
      //   * or has a killed aliased register use of I1's use reg
353
169
      //           %d4 = A2_tfrpi 16
354
169
      //           %r6 = A2_tfr %r9
355
169
      //           %r8 = KILL %r8, implicit killed %d4
356
169
      //      If we want to move R6 = across the KILL instruction we would have
357
169
      //      to remove the implicit killed %d4 operand. For now, we are
358
169
      //      conservative and disallow the move.
359
169
      // we can't move I1 across it.
360
169
      if (MI.isDebugInstr()) {
361
0
        if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
362
0
          DbgMItoMove.push_back(&MI);
363
0
        continue;
364
0
      }
365
169
366
169
      if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) ||
367
169
          // Check for an aliased register kill. Bail out if we see one.
368
169
          
(125
!MI.killsRegister(I1UseReg)125
&&
MI.killsRegister(I1UseReg, TRI)122
))
369
44
        return false;
370
125
371
125
      // Check for an exact kill (registers match).
372
125
      if (I1UseReg && 
MI.killsRegister(I1UseReg)49
) {
373
3
        assert(!KillingInstr && "Should only see one killing instruction");
374
3
        KilledOperand = I1UseReg;
375
3
        KillingInstr = &MI;
376
3
      }
377
125
    }
378
93
    
if (49
KillingInstr49
) {
379
3
      removeKillInfo(*KillingInstr, KilledOperand);
380
3
      // Update I1 to set the kill flag. This flag will later be picked up by
381
3
      // the new COMBINE instruction.
382
3
      bool Added = I1.addRegisterKilled(KilledOperand, TRI);
383
3
      (void)Added; // suppress compiler warning
384
3
      assert(Added && "Must successfully update kill flag");
385
3
    }
386
49
    DoInsertAtI1 = false;
387
49
  }
388
49
389
49
  return true;
390
93
}
391
392
/// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
393
/// newified. (A use of a 64 bit register define can not be newified)
394
void
395
6.79k
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
396
6.79k
  DenseMap<unsigned, MachineInstr *> LastDef;
397
34.2k
  for (MachineInstr &MI : BB) {
398
34.2k
    if (MI.isDebugInstr())
399
21
      continue;
400
34.2k
401
34.2k
    // Mark TFRs that feed a potential new value store as such.
402
34.2k
    if (TII->mayBeNewStore(MI)) {
403
2.13k
      // Look for uses of TFR instructions.
404
8.73k
      for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;
405
6.60k
           ++OpdIdx) {
406
6.60k
        MachineOperand &Op = MI.getOperand(OpdIdx);
407
6.60k
408
6.60k
        // Skip over anything except register uses.
409
6.60k
        if (!Op.isReg() || 
!Op.isUse()4.47k
||
!Op.getReg()4.31k
)
410
2.29k
          continue;
411
4.31k
412
4.31k
        // Look for the defining instruction.
413
4.31k
        unsigned Reg = Op.getReg();
414
4.31k
        MachineInstr *DefInst = LastDef[Reg];
415
4.31k
        if (!DefInst)
416
1.94k
          continue;
417
2.37k
        if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
418
1.40k
          continue;
419
966
420
966
        // Only close newifiable stores should influence the decision.
421
966
        // Ignore the debug instructions in between.
422
966
        MachineBasicBlock::iterator It(DefInst);
423
966
        unsigned NumInstsToDef = 0;
424
135k
        while (&*It != &MI) {
425
134k
          if (!It->isDebugInstr())
426
134k
            ++NumInstsToDef;
427
134k
          ++It;
428
134k
        }
429
966
430
966
        if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
431
692
          continue;
432
274
433
274
        PotentiallyNewifiableTFR.insert(DefInst);
434
274
      }
435
2.13k
      // Skip to next instruction.
436
2.13k
      continue;
437
2.13k
    }
438
32.0k
439
32.0k
    // Put instructions that last defined integer or double registers into the
440
32.0k
    // map.
441
115k
    
for (MachineOperand &Op : MI.operands())32.0k
{
442
115k
      if (Op.isReg()) {
443
97.4k
        if (!Op.isDef() || 
!Op.getReg()41.6k
)
444
55.7k
          continue;
445
41.6k
        unsigned Reg = Op.getReg();
446
41.6k
        if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
447
14.5k
          for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); 
++SubRegs9.71k
)
448
9.71k
            LastDef[*SubRegs] = &MI;
449
36.8k
        } else if (Hexagon::IntRegsRegClass.contains(Reg))
450
18.8k
          LastDef[Reg] = &MI;
451
41.6k
      } else 
if (18.3k
Op.isRegMask()18.3k
) {
452
740
        for (unsigned Reg : Hexagon::IntRegsRegClass)
453
23.6k
          if (Op.clobbersPhysReg(Reg))
454
14.8k
            LastDef[Reg] = &MI;
455
740
      }
456
115k
    }
457
32.0k
  }
458
6.79k
}
459
460
4.96k
bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
461
4.96k
  if (skipFunction(MF.getFunction()))
462
10
    return false;
463
4.95k
464
4.95k
  if (IsCombinesDisabled) 
return false0
;
465
4.95k
466
4.95k
  bool HasChanged = false;
467
4.95k
468
4.95k
  // Get target info.
469
4.95k
  ST = &MF.getSubtarget<HexagonSubtarget>();
470
4.95k
  TRI = ST->getRegisterInfo();
471
4.95k
  TII = ST->getInstrInfo();
472
4.95k
473
4.95k
  const Function &F = MF.getFunction();
474
4.95k
  bool OptForSize = F.hasFnAttribute(Attribute::OptimizeForSize);
475
4.95k
476
4.95k
  // Combine aggressively (for code size)
477
4.95k
  ShouldCombineAggressively =
478
4.95k
    MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
479
4.95k
480
4.95k
  // Traverse basic blocks.
481
11.7k
  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
482
6.79k
       ++BI) {
483
6.79k
    PotentiallyNewifiableTFR.clear();
484
6.79k
    findPotentialNewifiableTFRs(*BI);
485
6.79k
486
6.79k
    // Traverse instructions in basic block.
487
6.79k
    for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
488
40.8k
        MI != End;) {
489
34.0k
      MachineInstr &I1 = *MI++;
490
34.0k
491
34.0k
      if (I1.isDebugInstr())
492
21
        continue;
493
33.9k
494
33.9k
      // Don't combine a TFR whose user could be newified (instructions that
495
33.9k
      // define double registers can not be newified - Programmer's Ref Manual
496
33.9k
      // 5.4.2 New-value stores).
497
33.9k
      if (ShouldCombineAggressively && 
PotentiallyNewifiableTFR.count(&I1)31.9k
)
498
269
        continue;
499
33.7k
500
33.7k
      // Ignore instructions that are not combinable.
501
33.7k
      if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
502
30.0k
        continue;
503
3.66k
504
3.66k
      // Find a second instruction that can be merged into a combine
505
3.66k
      // instruction. In addition, also find all the debug instructions that
506
3.66k
      // need to be moved along with it.
507
3.66k
      bool DoInsertAtI1 = false;
508
3.66k
      DbgMItoMove.clear();
509
3.66k
      MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize);
510
3.66k
      if (I2) {
511
246
        HasChanged = true;
512
246
        combine(I1, *I2, MI, DoInsertAtI1, OptForSize);
513
246
      }
514
3.66k
    }
515
6.79k
  }
516
4.95k
517
4.95k
  return HasChanged;
518
4.95k
}
519
520
/// findPairable - Returns an instruction that can be merged with \p I1 into a
521
/// COMBINE instruction or 0 if no such instruction can be found. Returns true
522
/// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
523
/// false if the combine must be inserted at the returned instruction.
524
MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
525
                                                 bool &DoInsertAtI1,
526
3.66k
                                                 bool AllowC64) {
527
3.66k
  MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
528
3.66k
  while (I2 != I1.getParent()->end() && 
I2->isDebugInstr()3.53k
)
529
1
    ++I2;
530
3.66k
531
3.66k
  unsigned I1DestReg = I1.getOperand(0).getReg();
532
3.66k
533
21.9k
  for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
534
19.5k
       
++I218.3k
) {
535
19.5k
    // Bail out early if we see a second definition of I1DestReg.
536
19.5k
    if (I2->modifiesRegister(I1DestReg, TRI))
537
730
      break;
538
18.8k
539
18.8k
    // Ignore non-combinable instructions.
540
18.8k
    if (!isCombinableInstType(*I2, TII, ShouldCombineAggressively))
541
16.8k
      continue;
542
2.00k
543
2.00k
    // Don't combine a TFR whose user could be newified.
544
2.00k
    if (ShouldCombineAggressively && 
PotentiallyNewifiableTFR.count(&*I2)1.87k
)
545
65
      continue;
546
1.94k
547
1.94k
    unsigned I2DestReg = I2->getOperand(0).getReg();
548
1.94k
549
1.94k
    // Check that registers are adjacent and that the first destination register
550
1.94k
    // is even.
551
1.94k
    bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
552
1.94k
    bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
553
1.94k
    unsigned FirstRegIndex = IsI1LowReg ? 
I1DestReg459
:
I2DestReg1.48k
;
554
1.94k
    if ((!IsI1LowReg && 
!IsI2LowReg1.48k
) ||
!isEvenReg(FirstRegIndex)653
)
555
1.47k
      continue;
556
470
557
470
    // Check that the two instructions are combinable.
558
470
    // The order matters because in a A2_tfrsi we might can encode a int8 as
559
470
    // the hi reg operand but only a uint6 as the low reg operand.
560
470
    if ((IsI2LowReg && 
!areCombinableOperations(TRI, I1, *I2, AllowC64)132
) ||
561
470
        
(423
IsI1LowReg423
&&
!areCombinableOperations(TRI, *I2, I1, AllowC64)338
))
562
165
      break;
563
305
564
305
    if (isSafeToMoveTogether(I1, *I2, I1DestReg, I2DestReg, DoInsertAtI1))
565
246
      return &*I2;
566
59
567
59
    // Not safe. Stop searching.
568
59
    break;
569
59
  }
570
3.66k
  
return nullptr3.41k
;
571
3.66k
}
572
573
void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
574
                                   MachineBasicBlock::iterator &MI,
575
246
                                   bool DoInsertAtI1, bool OptForSize) {
576
246
  // We are going to delete I2. If MI points to I2 advance it to the next
577
246
  // instruction.
578
246
  if (MI == I2.getIterator())
579
207
    ++MI;
580
246
581
246
  // Figure out whether I1 or I2 goes into the lowreg part.
582
246
  unsigned I1DestReg = I1.getOperand(0).getReg();
583
246
  unsigned I2DestReg = I2.getOperand(0).getReg();
584
246
  bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
585
246
  unsigned LoRegDef = IsI1Loreg ? 
I1DestReg192
:
I2DestReg54
;
586
246
  unsigned SubLo;
587
246
588
246
  const TargetRegisterClass *SuperRC = nullptr;
589
246
  if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
590
218
    SuperRC = &Hexagon::DoubleRegsRegClass;
591
218
    SubLo = Hexagon::isub_lo;
592
218
  } else 
if (28
Hexagon::HvxVRRegClass.contains(LoRegDef)28
) {
593
28
    assert(ST->useHVXOps());
594
28
    SuperRC = &Hexagon::HvxWRRegClass;
595
28
    SubLo = Hexagon::vsub_lo;
596
28
  } else
597
28
    
llvm_unreachable0
("Unexpected register class");
598
246
599
246
  // Get the double word register.
600
246
  unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
601
246
  assert(DoubleRegDest != 0 && "Expect a valid register");
602
246
603
246
  // Setup source operands.
604
246
  MachineOperand &LoOperand = IsI1Loreg ? 
I1.getOperand(1)192
:
I2.getOperand(1)54
;
605
246
  MachineOperand &HiOperand = IsI1Loreg ? 
I2.getOperand(1)192
:
I1.getOperand(1)54
;
606
246
607
246
  // Figure out which source is a register and which a constant.
608
246
  bool IsHiReg = HiOperand.isReg();
609
246
  bool IsLoReg = LoOperand.isReg();
610
246
611
246
  // There is a combine of two constant extended values into CONST64.
612
246
  bool IsC64 = OptForSize && 
LoOperand.isImm()19
&&
HiOperand.isImm()12
&&
613
246
               
isGreaterThanNBitTFRI<16>(I1)10
&&
isGreaterThanNBitTFRI<16>(I2)2
;
614
246
615
246
  MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? 
I1197
:
I249
);
616
246
  // Emit combine.
617
246
  if (IsHiReg && 
IsLoReg131
)
618
119
    emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
619
127
  else if (IsHiReg)
620
12
    emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
621
115
  else if (IsLoReg)
622
14
    emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
623
101
  else if (IsC64 && 
!IsConst64Disabled2
)
624
1
    emitConst64(InsertPt, DoubleRegDest, HiOperand, LoOperand);
625
100
  else
626
100
    emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
627
246
628
246
  // Move debug instructions along with I1 if it's being
629
246
  // moved towards I2.
630
246
  if (!DoInsertAtI1 && 
DbgMItoMove.size() != 049
) {
631
0
    // Insert debug instructions at the new location before I2.
632
0
    MachineBasicBlock *BB = InsertPt->getParent();
633
0
    for (auto NewMI : DbgMItoMove) {
634
0
      // If iterator MI is pointing to DEBUG_VAL, make sure
635
0
      // MI now points to next relevant instruction.
636
0
      if (NewMI == MI)
637
0
        ++MI;
638
0
      BB->splice(InsertPt, BB, NewMI);
639
0
    }
640
0
  }
641
246
642
246
  I1.eraseFromParent();
643
246
  I2.eraseFromParent();
644
246
}
645
646
void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt,
647
                                       unsigned DoubleDestReg,
648
                                       MachineOperand &HiOperand,
649
1
                                       MachineOperand &LoOperand) {
650
1
  LLVM_DEBUG(dbgs() << "Found a CONST64\n");
651
1
652
1
  DebugLoc DL = InsertPt->getDebugLoc();
653
1
  MachineBasicBlock *BB = InsertPt->getParent();
654
1
  assert(LoOperand.isImm() && HiOperand.isImm() &&
655
1
         "Both operands must be immediate");
656
1
657
1
  int64_t V = HiOperand.getImm();
658
1
  V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm());
659
1
  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
660
1
    .addImm(V);
661
1
}
662
663
void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
664
                                         unsigned DoubleDestReg,
665
                                         MachineOperand &HiOperand,
666
100
                                         MachineOperand &LoOperand) {
667
100
  DebugLoc DL = InsertPt->getDebugLoc();
668
100
  MachineBasicBlock *BB = InsertPt->getParent();
669
100
670
100
  // Handle globals.
671
100
  if (HiOperand.isGlobal()) {
672
9
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
673
9
      .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
674
9
                        HiOperand.getTargetFlags())
675
9
      .addImm(LoOperand.getImm());
676
9
    return;
677
9
  }
678
91
  if (LoOperand.isGlobal()) {
679
10
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
680
10
      .addImm(HiOperand.getImm())
681
10
      .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
682
10
                        LoOperand.getTargetFlags());
683
10
    return;
684
10
  }
685
81
686
81
  // Handle block addresses.
687
81
  if (HiOperand.isBlockAddress()) {
688
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
689
0
      .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
690
0
                       HiOperand.getTargetFlags())
691
0
      .addImm(LoOperand.getImm());
692
0
    return;
693
0
  }
694
81
  if (LoOperand.isBlockAddress()) {
695
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
696
0
      .addImm(HiOperand.getImm())
697
0
      .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
698
0
                       LoOperand.getTargetFlags());
699
0
    return;
700
0
  }
701
81
702
81
  // Handle jump tables.
703
81
  if (HiOperand.isJTI()) {
704
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
705
0
      .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
706
0
      .addImm(LoOperand.getImm());
707
0
    return;
708
0
  }
709
81
  if (LoOperand.isJTI()) {
710
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
711
0
      .addImm(HiOperand.getImm())
712
0
      .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
713
0
    return;
714
0
  }
715
81
716
81
  // Handle constant pools.
717
81
  if (HiOperand.isCPI()) {
718
1
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
719
1
      .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
720
1
                            HiOperand.getTargetFlags())
721
1
      .addImm(LoOperand.getImm());
722
1
    return;
723
1
  }
724
80
  if (LoOperand.isCPI()) {
725
2
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
726
2
      .addImm(HiOperand.getImm())
727
2
      .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
728
2
                            LoOperand.getTargetFlags());
729
2
    return;
730
2
  }
731
78
732
78
  // First preference should be given to Hexagon::A2_combineii instruction
733
78
  // as it can include U6 (in Hexagon::A4_combineii) as well.
734
78
  // In this instruction, HiOperand is const extended, if required.
735
78
  if (isInt<8>(LoOperand.getImm())) {
736
74
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
737
74
      .addImm(HiOperand.getImm())
738
74
      .addImm(LoOperand.getImm());
739
74
      return;
740
74
  }
741
4
742
4
  // In this instruction, LoOperand is const extended, if required.
743
4
  if (isInt<8>(HiOperand.getImm())) {
744
3
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
745
3
      .addImm(HiOperand.getImm())
746
3
      .addImm(LoOperand.getImm());
747
3
    return;
748
3
  }
749
1
750
1
  // Insert new combine instruction.
751
1
  //  DoubleRegDest = combine #HiImm, #LoImm
752
1
  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
753
1
    .addImm(HiOperand.getImm())
754
1
    .addImm(LoOperand.getImm());
755
1
}
756
757
void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
758
                                         unsigned DoubleDestReg,
759
                                         MachineOperand &HiOperand,
760
14
                                         MachineOperand &LoOperand) {
761
14
  unsigned LoReg = LoOperand.getReg();
762
14
  unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
763
14
764
14
  DebugLoc DL = InsertPt->getDebugLoc();
765
14
  MachineBasicBlock *BB = InsertPt->getParent();
766
14
767
14
  // Handle globals.
768
14
  if (HiOperand.isGlobal()) {
769
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
770
0
      .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
771
0
                        HiOperand.getTargetFlags())
772
0
      .addReg(LoReg, LoRegKillFlag);
773
0
    return;
774
0
  }
775
14
  // Handle block addresses.
776
14
  if (HiOperand.isBlockAddress()) {
777
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
778
0
      .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
779
0
                       HiOperand.getTargetFlags())
780
0
      .addReg(LoReg, LoRegKillFlag);
781
0
    return;
782
0
  }
783
14
  // Handle jump tables.
784
14
  if (HiOperand.isJTI()) {
785
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
786
0
      .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
787
0
      .addReg(LoReg, LoRegKillFlag);
788
0
    return;
789
0
  }
790
14
  // Handle constant pools.
791
14
  if (HiOperand.isCPI()) {
792
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
793
0
      .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
794
0
                            HiOperand.getTargetFlags())
795
0
      .addReg(LoReg, LoRegKillFlag);
796
0
    return;
797
0
  }
798
14
  // Insert new combine instruction.
799
14
  //  DoubleRegDest = combine #HiImm, LoReg
800
14
  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
801
14
    .addImm(HiOperand.getImm())
802
14
    .addReg(LoReg, LoRegKillFlag);
803
14
}
804
805
void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
806
                                         unsigned DoubleDestReg,
807
                                         MachineOperand &HiOperand,
808
12
                                         MachineOperand &LoOperand) {
809
12
  unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
810
12
  unsigned HiReg = HiOperand.getReg();
811
12
812
12
  DebugLoc DL = InsertPt->getDebugLoc();
813
12
  MachineBasicBlock *BB = InsertPt->getParent();
814
12
815
12
  // Handle global.
816
12
  if (LoOperand.isGlobal()) {
817
5
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
818
5
      .addReg(HiReg, HiRegKillFlag)
819
5
      .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
820
5
                        LoOperand.getTargetFlags());
821
5
    return;
822
5
  }
823
7
  // Handle block addresses.
824
7
  if (LoOperand.isBlockAddress()) {
825
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
826
0
      .addReg(HiReg, HiRegKillFlag)
827
0
      .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
828
0
                       LoOperand.getTargetFlags());
829
0
    return;
830
0
  }
831
7
  // Handle jump tables.
832
7
  if (LoOperand.isJTI()) {
833
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
834
0
      .addReg(HiOperand.getReg(), HiRegKillFlag)
835
0
      .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
836
0
    return;
837
0
  }
838
7
  // Handle constant pools.
839
7
  if (LoOperand.isCPI()) {
840
0
    BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
841
0
      .addReg(HiOperand.getReg(), HiRegKillFlag)
842
0
      .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
843
0
                            LoOperand.getTargetFlags());
844
0
    return;
845
0
  }
846
7
847
7
  // Insert new combine instruction.
848
7
  //  DoubleRegDest = combine HiReg, #LoImm
849
7
  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
850
7
    .addReg(HiReg, HiRegKillFlag)
851
7
    .addImm(LoOperand.getImm());
852
7
}
853
854
void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
855
                                         unsigned DoubleDestReg,
856
                                         MachineOperand &HiOperand,
857
119
                                         MachineOperand &LoOperand) {
858
119
  unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
859
119
  unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
860
119
  unsigned LoReg = LoOperand.getReg();
861
119
  unsigned HiReg = HiOperand.getReg();
862
119
863
119
  DebugLoc DL = InsertPt->getDebugLoc();
864
119
  MachineBasicBlock *BB = InsertPt->getParent();
865
119
866
119
  // Insert new combine instruction.
867
119
  //  DoubleRegDest = combine HiReg, LoReg
868
119
  unsigned NewOpc;
869
119
  if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
870
91
    NewOpc = Hexagon::A2_combinew;
871
91
  } else 
if (28
Hexagon::HvxWRRegClass.contains(DoubleDestReg)28
) {
872
28
    assert(ST->useHVXOps());
873
28
    NewOpc = Hexagon::V6_vcombine;
874
28
  } else
875
28
    
llvm_unreachable0
("Unexpected register");
876
119
877
119
  BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
878
119
    .addReg(HiReg, HiRegKillFlag)
879
119
    .addReg(LoReg, LoRegKillFlag);
880
119
}
881
882
919
FunctionPass *llvm::createHexagonCopyToCombine() {
883
919
  return new HexagonCopyToCombine();
884
919
}