Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
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//===-- HexagonHazardRecognizer.cpp - Hexagon Post RA Hazard Recognizer ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the hazard recognizer for scheduling on Hexagon.
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// Use a DFA based hazard recognizer.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonHazardRecognizer.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "post-RA-sched"
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void HexagonHazardRecognizer::Reset() {
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  LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n");
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  Resources->clearResources();
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  PacketNum = 0;
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  UsesDotCur = nullptr;
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  DotCurPNum = -1;
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  UsesLoad = false;
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  PrefVectorStoreNew = nullptr;
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  RegDefs.clear();
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}
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ScheduleHazardRecognizer::HazardType
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HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) {
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  MachineInstr *MI = SU->getInstr();
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  if (!MI || TII->isZeroCost(MI->getOpcode()))
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    return NoHazard;
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  if (!Resources->canReserveResources(*MI)) {
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    LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
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    HazardType RetVal = Hazard;
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    if (TII->mayBeNewStore(*MI)) {
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      // Make sure the register to be stored is defined by an instruction in the
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      // packet.
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      MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
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      if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
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        return Hazard;
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      // The .new store version uses different resources so check if it
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      // causes a hazard.
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      MachineFunction *MF = MI->getParent()->getParent();
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      MachineInstr *NewMI =
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        MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
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                               MI->getDebugLoc());
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      if (Resources->canReserveResources(*NewMI))
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        RetVal = NoHazard;
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      LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard)
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                        << "\n");
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      MF->DeleteMachineInstr(NewMI);
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    }
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return RetVal5.19k
;
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  }
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  if (SU == UsesDotCur && 
DotCurPNum != (int)PacketNum3
) {
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    LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", "
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                      << *MI);
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    return Hazard;
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  }
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  return NoHazard;
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}
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void HexagonHazardRecognizer::AdvanceCycle() {
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  LLVM_DEBUG(dbgs() << "Advance cycle, clear state\n");
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  Resources->clearResources();
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  if (DotCurPNum != -1 && 
DotCurPNum != (int)PacketNum34
) {
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    UsesDotCur = nullptr;
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    DotCurPNum = -1;
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  }
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  UsesLoad = false;
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  PrefVectorStoreNew = nullptr;
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  PacketNum++;
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  RegDefs.clear();
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}
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/// Handle the cases when we prefer one instruction over another. Case 1 - we
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/// prefer not to generate multiple loads in the packet to avoid a potential
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/// bank conflict. Case 2 - if a packet contains a dot cur instruction, then we
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/// prefer the instruction that can use the dot cur result. However, if the use
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/// is not scheduled in the same packet, then prefer other instructions in the
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/// subsequent packet. Case 3 - we prefer a vector store that can be converted
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/// to a .new store. The packetizer will not generate the .new store if the
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/// store doesn't have resources to fit in the packet (but the .new store may
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/// have resources). We attempt to schedule the store as soon as possible to
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/// help packetize the two instructions together.
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bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
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  if (PrefVectorStoreNew != nullptr && 
PrefVectorStoreNew != SU320
)
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    return true;
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  if (UsesLoad && 
SU->isInstr()1.91k
&&
SU->getInstr()->mayLoad()1.91k
)
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    return true;
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  return UsesDotCur && 
((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum))92
;
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}
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void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) {
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  MachineInstr *MI = SU->getInstr();
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  if (!MI)
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    return;
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  // Keep the set of definitions for each packet, which is used to determine
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  // if a .new can be used.
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  for (const MachineOperand &MO : MI->operands())
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    if (MO.isReg() && 
MO.isDef()51.3k
&&
!MO.isImplicit()20.0k
)
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      RegDefs.insert(MO.getReg());
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  if (TII->isZeroCost(MI->getOpcode()))
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    return;
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  if (!Resources->canReserveResources(*MI)) {
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    // It must be a .new store since other instructions must be able to be
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    // reserved at this point.
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    assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
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    MachineFunction *MF = MI->getParent()->getParent();
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    MachineInstr *NewMI =
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        MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
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                               MI->getDebugLoc());
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    assert(Resources->canReserveResources(*NewMI));
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    Resources->reserveResources(*NewMI);
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    MF->DeleteMachineInstr(NewMI);
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  }
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  else
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    Resources->reserveResources(*MI);
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  LLVM_DEBUG(dbgs() << " Add instruction " << *MI);
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  // When scheduling a dot cur instruction, check if there is an instruction
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  // that can use the dot cur in the same packet. If so, we'll attempt to
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  // schedule it before other instructions. We only do this if the load has a
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  // single zero-latency use.
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  if (TII->mayBeCurLoad(*MI))
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    for (auto &S : SU->Succs)
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      if (S.isAssignedRegDep() && 
S.getLatency() == 0571
&&
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S.getSUnit()->NumPredsLeft == 1328
) {
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        UsesDotCur = S.getSUnit();
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        DotCurPNum = PacketNum;
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        break;
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      }
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  if (SU == UsesDotCur) {
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    UsesDotCur = nullptr;
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    DotCurPNum = -1;
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  }
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  UsesLoad = MI->mayLoad();
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  if (TII->isHVXVec(*MI) && 
!MI->mayLoad()5.55k
&&
!MI->mayStore()4.83k
)
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    for (auto &S : SU->Succs)
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      if (S.isAssignedRegDep() && 
S.getLatency() == 03.30k
&&
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TII->mayBeNewStore(*S.getSUnit()->getInstr())250
&&
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Resources->canReserveResources(*S.getSUnit()->getInstr())244
) {
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        PrefVectorStoreNew = S.getSUnit();
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        break;
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      }
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}