Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
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//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Hexagon specific code to select Hexagon machine instructions for
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// SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/CodeGen.h"
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#include <vector>
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namespace llvm {
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class MachineFunction;
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class HexagonTargetLowering;
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class HexagonDAGToDAGISel : public SelectionDAGISel {
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  const HexagonSubtarget *HST;
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  const HexagonInstrInfo *HII;
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  const HexagonRegisterInfo *HRI;
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public:
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  explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
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                               CodeGenOpt::Level OptLevel)
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      : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
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        HRI(nullptr) {}
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  bool runOnMachineFunction(MachineFunction &MF) override {
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    // Reset the subtarget each time through.
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    HST = &MF.getSubtarget<HexagonSubtarget>();
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    HII = HST->getInstrInfo();
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    HRI = HST->getRegisterInfo();
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    SelectionDAGISel::runOnMachineFunction(MF);
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    return true;
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  }
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  bool ComplexPatternFuncMutatesDAG() const override {
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    return true;
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  }
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  void PreprocessISelDAG() override;
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  void EmitFunctionEntryCode() override;
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  void Select(SDNode *N) override;
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  // Complex Pattern Selectors.
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  inline bool SelectAddrGA(SDValue &N, SDValue &R);
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  inline bool SelectAddrGP(SDValue &N, SDValue &R);
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  inline bool SelectAnyImm(SDValue &N, SDValue &R);
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  inline bool SelectAnyInt(SDValue &N, SDValue &R);
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  bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
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  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
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                           uint32_t LogAlign);
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  bool SelectAddrFI(SDValue &N, SDValue &R);
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  bool DetectUseSxtw(SDValue &N, SDValue &R);
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  inline bool SelectAnyImm0(SDValue &N, SDValue &R);
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  inline bool SelectAnyImm1(SDValue &N, SDValue &R);
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  inline bool SelectAnyImm2(SDValue &N, SDValue &R);
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  inline bool SelectAnyImm3(SDValue &N, SDValue &R);
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  StringRef getPassName() const override {
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    return "Hexagon DAG->DAG Pattern Instruction Selection";
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  }
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  // Generate a machine instruction node corresponding to the circ/brev
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  // load intrinsic.
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  MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
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  // Given the circ/brev load intrinsic and the already generated machine
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  // instruction, generate the appropriate store (that is a part of the
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  // intrinsic's functionality).
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  SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
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  void SelectFrameIndex(SDNode *N);
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  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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  /// inline asm expressions.
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  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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                                    unsigned ConstraintID,
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                                    std::vector<SDValue> &OutOps) override;
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  bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
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  bool SelectBrevLdIntrinsic(SDNode *IntN);
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  bool SelectNewCircIntrinsic(SDNode *IntN);
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  void SelectLoad(SDNode *N);
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  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
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  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
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  void SelectStore(SDNode *N);
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  void SelectSHL(SDNode *N);
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  void SelectZeroExtend(SDNode *N);
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  void SelectIntrinsicWChain(SDNode *N);
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  void SelectIntrinsicWOChain(SDNode *N);
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  void SelectConstant(SDNode *N);
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  void SelectConstantFP(SDNode *N);
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  void SelectV65Gather(SDNode *N);
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  void SelectV65GatherPred(SDNode *N);
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  void SelectHVXDualOutput(SDNode *N);
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  void SelectAddSubCarry(SDNode *N);
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  void SelectVAlign(SDNode *N);
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  void SelectVAlignAddr(SDNode *N);
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  void SelectTypecast(SDNode *N);
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  void SelectP2D(SDNode *N);
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  void SelectD2P(SDNode *N);
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  void SelectQ2V(SDNode *N);
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  void SelectV2Q(SDNode *N);
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  // Include the declarations autogenerated from the selection patterns.
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  #define GET_DAGISEL_DECL
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  #include "HexagonGenDAGISel.inc"
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private:
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  // This is really only to get access to ReplaceNode (which is a protected
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  // member). Any other members used by HvxSelector can be moved around to
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  // make them accessible).
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  friend struct HvxSelector;
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  SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
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    SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
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    return SDValue(U, 0);
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  }
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  void SelectHvxShuffle(SDNode *N);
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  void SelectHvxRor(SDNode *N);
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  void SelectHvxVAlign(SDNode *N);
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  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
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  bool isAlignedMemNode(const MemSDNode *N) const;
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  bool isSmallStackStore(const StoreSDNode *N) const;
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  bool isPositiveHalfWord(const SDNode *N) const;
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  bool hasOneUse(const SDNode *N) const;
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  // DAG preprocessing functions.
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  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
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  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
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  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
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  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
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  SmallDenseMap<SDNode *,int> RootWeights;
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  SmallDenseMap<SDNode *,int> RootHeights;
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  SmallDenseMap<const Value *,int> GAUsesInFunction;
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  int getWeight(SDNode *N);
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  int getHeight(SDNode *N);
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  SDValue getMultiplierForSHL(SDNode *N);
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  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
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  unsigned getUsesInFunction(const Value *V);
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  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
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  void rebalanceAddressTrees();
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}; // end HexagonDAGToDAGISel
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}
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H