Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonISelLowering.h
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//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Hexagon uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#include "Hexagon.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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#include <utility>
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namespace llvm {
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namespace HexagonISD {
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    enum NodeType : unsigned {
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      OP_BEGIN = ISD::BUILTIN_OP_END,
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      CONST32 = OP_BEGIN,
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      CONST32_GP,  // For marking data present in GP.
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      ADDC,        // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
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      SUBC,        // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
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      ALLOCA,
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      AT_GOT,      // Index in GOT.
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      AT_PCREL,    // Offset relative to PC.
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      CALL,        // Function call.
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      CALLnr,      // Function call that does not return.
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      CALLR,
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      RET_FLAG,    // Return with a flag operand.
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      BARRIER,     // Memory barrier.
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      JT,          // Jump table.
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      CP,          // Constant pool.
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      COMBINE,
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      VSPLAT,      // Generic splat, selection depends on argument/return
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                   // types.
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      VASL,
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      VASR,
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      VLSR,
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      TSTBIT,
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      INSERT,
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      EXTRACTU,
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      VEXTRACTW,
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      VINSERTW0,
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      VROR,
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      TC_RETURN,
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      EH_RETURN,
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      DCFETCH,
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      READCYCLE,
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      D2P,         // Convert 8-byte value to 8-bit predicate register. [*]
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      P2D,         // Convert 8-bit predicate register to 8-byte value. [*]
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      V2Q,         // Convert HVX vector to a vector predicate reg. [*]
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      Q2V,         // Convert vector predicate to an HVX vector. [*]
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                   // [*] The equivalence is defined as "Q <=> (V != 0)",
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                   //     where the != operation compares bytes.
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                   // Note: V != 0 is implemented as V >u 0.
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      QCAT,
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      QTRUE,
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      QFALSE,
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      VZERO,
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      VSPLATW,     // HVX splat of a 32-bit word with an arbitrary result type.
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      TYPECAST,    // No-op that's used to convert between different legal
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                   // types in a register.
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      VALIGN,      // Align two vectors (in Op0, Op1) to one that would have
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                   // been loaded from address in Op2.
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      VALIGNADDR,  // Align vector address: Op0 & -Op1, except when it is
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                   // an address in a vector load, then it's a no-op.
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      OP_END
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    };
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} // end namespace HexagonISD
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  class HexagonSubtarget;
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  class HexagonTargetLowering : public TargetLowering {
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    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
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    const HexagonTargetMachine &HTM;
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    const HexagonSubtarget &Subtarget;
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    bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
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        const;
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  public:
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    explicit HexagonTargetLowering(const TargetMachine &TM,
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                                   const HexagonSubtarget &ST);
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    bool isHVXVectorType(MVT Ty) const;
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    /// IsEligibleForTailCallOptimization - Check whether the call is eligible
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    /// for tail call optimization. Targets which want to do tail call
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    /// optimization should implement this function.
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    bool IsEligibleForTailCallOptimization(SDValue Callee,
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        CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
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        bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
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        const SmallVectorImpl<SDValue> &OutVals,
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        const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
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    bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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                            MachineFunction &MF,
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                            unsigned Intrinsic) const override;
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    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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    bool isTruncateFree(EVT VT1, EVT VT2) const override;
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10
    bool isCheapToSpeculateCttz() const override { return true; }
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10
    bool isCheapToSpeculateCtlz() const override { return true; }
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0
    bool isCtlzFast() const override { return true; }
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    bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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    /// Return true if an FMA operation is faster than a pair of mul and add
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    /// instructions. fmuladd intrinsics will be expanded to FMAs when this
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    /// method returns true (and FMAs are legal), otherwise fmuladd is
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    /// expanded to mul + add.
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    bool isFMAFasterThanFMulAndFAdd(EVT) const override;
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    // Should we expand the build vector with shuffles?
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    bool shouldExpandBuildVectorWithShuffles(EVT VT,
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        unsigned DefinedValues) const override;
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    bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
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    TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
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        const override;
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    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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    void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
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                               SelectionDAG &DAG) const override;
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    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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                            SelectionDAG &DAG) const override;
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    const char *getTargetNodeName(unsigned Opcode) const override;
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    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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    SDValue
180
    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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                         const SmallVectorImpl<ISD::InputArg> &Ins,
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                         const SDLoc &dl, SelectionDAG &DAG,
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                         SmallVectorImpl<SDValue> &InVals) const override;
184
    SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
187
    SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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        SelectionDAG &DAG) const;
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    SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
190
        SelectionDAG &DAG) const;
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    SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
192
        SelectionDAG &DAG) const;
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    SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
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        GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
195
        unsigned ReturnReg, unsigned char OperandFlags) const;
196
    SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
197
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    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
199
        SmallVectorImpl<SDValue> &InVals) const override;
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    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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                            CallingConv::ID CallConv, bool isVarArg,
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                            const SmallVectorImpl<ISD::InputArg> &Ins,
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                            const SDLoc &dl, SelectionDAG &DAG,
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                            SmallVectorImpl<SDValue> &InVals,
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                            const SmallVectorImpl<SDValue> &OutVals,
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                            SDValue Callee) const;
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    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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    bool CanLowerReturn(CallingConv::ID CallConv,
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                        MachineFunction &MF, bool isVarArg,
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                        const SmallVectorImpl<ISD::OutputArg> &Outs,
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                        LLVMContext &Context) const override;
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    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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                        const SmallVectorImpl<ISD::OutputArg> &Outs,
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                        const SmallVectorImpl<SDValue> &OutVals,
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                        const SDLoc &dl, SelectionDAG &DAG) const override;
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    bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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    unsigned getRegisterByName(const char* RegName, EVT VT,
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                               SelectionDAG &DAG) const override;
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    /// If a physical register, this returns the register that receives the
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    /// exception address on entry to an EH pad.
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    unsigned
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17.8k
    getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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      return Hexagon::R0;
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17.8k
    }
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    /// If a physical register, this returns the register that receives the
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    /// exception typeid on entry to a landing pad.
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    unsigned
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17.8k
    getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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17.8k
      return Hexagon::R1;
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17.8k
    }
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    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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    EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
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901
                           EVT VT) const override {
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901
      if (!VT.isVector())
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766
        return MVT::i1;
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      else
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        return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
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901
    }
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    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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                                    SDValue &Base, SDValue &Offset,
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                                    ISD::MemIndexedMode &AM,
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                                    SelectionDAG &DAG) const override;
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    ConstraintType getConstraintType(StringRef Constraint) const override;
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    std::pair<unsigned, const TargetRegisterClass *>
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    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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                                 StringRef Constraint, MVT VT) const override;
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    unsigned
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    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
268
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      if (ConstraintCode == "o")
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        return InlineAsm::Constraint_o;
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      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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    }
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    // Intrinsics
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    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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    SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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    /// isLegalAddressingMode - Return true if the addressing mode represented
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    /// by AM is legal for this target, for a load/store of the specified type.
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    /// The type may be VoidTy, in which case only return true if the addressing
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    /// mode is legal for a load/store of any legal type.
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    /// TODO: Handle pre/postinc as well.
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    bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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                               Type *Ty, unsigned AS,
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                               Instruction *I = nullptr) const override;
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    /// Return true if folding a constant offset with the given GlobalAddress
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    /// is legal.  It is frequently not legal in PIC relocation models.
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    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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    bool isFPImmLegal(const APFloat &Imm, EVT VT,
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                      bool ForCodeSize) const override;
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    /// isLegalICmpImmediate - Return true if the specified immediate is legal
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    /// icmp immediate, that is the target has icmp instructions which can
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    /// compare a register against the immediate without having to materialize
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    /// the immediate into a register.
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    bool isLegalICmpImmediate(int64_t Imm) const override;
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    EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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        unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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        const AttributeList &FuncAttributes) const override;
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    bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
302
        unsigned Align, MachineMemOperand::Flags Flags, bool *Fast) const override;
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    /// Returns relocation base for the given PIC jumptable.
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    SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
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                                     const override;
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    bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
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                               EVT NewVT) const override;
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    // Handling of atomic RMW instructions.
312
    Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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        AtomicOrdering Ord) const override;
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    Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
315
        Value *Addr, AtomicOrdering Ord) const override;
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    AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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    bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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    AtomicExpansionKind
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    shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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    AtomicExpansionKind
322
98
    shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
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      return AtomicExpansionKind::LLSC;
324
98
    }
325
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  private:
327
    void initializeHVXLowering();
328
    void validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
329
                                   unsigned NeedAlign) const;
330
331
    std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
332
333
    bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
334
                                 SelectionDAG &DAG,
335
                                 MutableArrayRef<ConstantInt*> Consts) const;
336
    SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
337
                          SelectionDAG &DAG) const;
338
    SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
339
                          SelectionDAG &DAG) const;
340
    SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
341
                          MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
342
    SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
343
                         const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
344
    SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
345
                            SelectionDAG &DAG) const;
346
    SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
347
                              SelectionDAG &DAG) const;
348
    SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
349
350
7.67k
    bool isUndef(SDValue Op) const {
351
7.67k
      if (Op.isMachineOpcode())
352
69
        return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
353
7.60k
      return Op.getOpcode() == ISD::UNDEF;
354
7.60k
    }
355
    SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
356
254
                     ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
357
254
      SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
358
254
      return SDValue(N, 0);
359
254
    }
360
    SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
361
362
    using VectorPair = std::pair<SDValue, SDValue>;
363
    using TypePair = std::pair<MVT, MVT>;
364
365
    SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
366
                   const SDLoc &dl, SelectionDAG &DAG) const;
367
368
69.4k
    MVT ty(SDValue Op) const {
369
69.4k
      return Op.getValueType().getSimpleVT();
370
69.4k
    }
371
0
    TypePair ty(const VectorPair &Ops) const {
372
0
      return { Ops.first.getValueType().getSimpleVT(),
373
0
               Ops.second.getValueType().getSimpleVT() };
374
0
    }
375
632
    MVT tyScalar(MVT Ty) const {
376
632
      if (!Ty.isVector())
377
363
        return Ty;
378
269
      return MVT::getIntegerVT(Ty.getSizeInBits());
379
269
    }
380
210
    MVT tyVector(MVT Ty, MVT ElemTy) const {
381
210
      if (Ty.isVector() && 
Ty.getVectorElementType() == ElemTy4
)
382
2
        return Ty;
383
208
      unsigned TyWidth = Ty.getSizeInBits();
384
208
      unsigned ElemWidth = ElemTy.getSizeInBits();
385
208
      assert((TyWidth % ElemWidth) == 0);
386
208
      return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
387
208
    }
388
389
    MVT typeJoin(const TypePair &Tys) const;
390
    TypePair typeSplit(MVT Ty) const;
391
    MVT typeExtElem(MVT VecTy, unsigned Factor) const;
392
    MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
393
394
    SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
395
                   SelectionDAG &DAG) const;
396
    VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
397
    SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
398
399
    bool isHvxSingleTy(MVT Ty) const;
400
    bool isHvxPairTy(MVT Ty) const;
401
    SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
402
                               SelectionDAG &DAG) const;
403
    SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
404
    SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
405
                           ArrayRef<int> Mask, SelectionDAG &DAG) const;
406
407
    SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
408
                              MVT VecTy, SelectionDAG &DAG) const;
409
    SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
410
                               MVT VecTy, SelectionDAG &DAG) const;
411
    SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
412
                                unsigned BitBytes, bool ZeroFill,
413
                                SelectionDAG &DAG) const;
414
    SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
415
                                 MVT ResTy, SelectionDAG &DAG) const;
416
    SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
417
                                  MVT ResTy, SelectionDAG &DAG) const;
418
    SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
419
                                const SDLoc &dl, SelectionDAG &DAG) const;
420
    SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
421
                                 const SDLoc &dl, SelectionDAG &DAG) const;
422
    SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
423
                                   MVT ResTy, SelectionDAG &DAG) const;
424
    SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
425
                                    MVT ResTy, SelectionDAG &DAG) const;
426
    SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
427
                                  const SDLoc &dl, SelectionDAG &DAG) const;
428
    SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
429
                                   const SDLoc &dl, SelectionDAG &DAG) const;
430
    SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
431
                                bool ZeroExt, SelectionDAG &DAG) const;
432
433
    SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
434
    SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
435
    SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
436
    SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
437
    SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
438
    SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
439
440
    SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
441
    SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
442
    SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
443
    SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
444
    SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
445
    SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
446
    SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
447
    SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
448
    SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
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    SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
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    SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
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    std::pair<const TargetRegisterClass*, uint8_t>
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    findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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        const override;
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    bool isHvxOperation(SDValue Op) const;
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    SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
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  };
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H