/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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1 | | //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file contains the Hexagon implementation of the TargetInstrInfo class. |
10 | | // |
11 | | //===----------------------------------------------------------------------===// |
12 | | |
13 | | #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H |
14 | | #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H |
15 | | |
16 | | #include "MCTargetDesc/HexagonBaseInfo.h" |
17 | | #include "llvm/ADT/ArrayRef.h" |
18 | | #include "llvm/ADT/SmallVector.h" |
19 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
20 | | #include "llvm/CodeGen/TargetInstrInfo.h" |
21 | | #include "llvm/CodeGen/ValueTypes.h" |
22 | | #include "llvm/Support/MachineValueType.h" |
23 | | #include <cstdint> |
24 | | #include <vector> |
25 | | |
26 | | #define GET_INSTRINFO_HEADER |
27 | | #include "HexagonGenInstrInfo.inc" |
28 | | |
29 | | namespace llvm { |
30 | | |
31 | | class HexagonSubtarget; |
32 | | class MachineBranchProbabilityInfo; |
33 | | class MachineFunction; |
34 | | class MachineInstr; |
35 | | class MachineOperand; |
36 | | class TargetRegisterInfo; |
37 | | |
38 | | class HexagonInstrInfo : public HexagonGenInstrInfo { |
39 | | const HexagonSubtarget &Subtarget; |
40 | | |
41 | | enum BundleAttribute { |
42 | | memShufDisabledMask = 0x4 |
43 | | }; |
44 | | |
45 | | virtual void anchor(); |
46 | | |
47 | | public: |
48 | | explicit HexagonInstrInfo(HexagonSubtarget &ST); |
49 | | |
50 | | /// TargetInstrInfo overrides. |
51 | | |
52 | | /// If the specified machine instruction is a direct |
53 | | /// load from a stack slot, return the virtual or physical register number of |
54 | | /// the destination along with the FrameIndex of the loaded stack slot. If |
55 | | /// not, return 0. This predicate must return 0 if the instruction has |
56 | | /// any side effects other than loading from the stack slot. |
57 | | unsigned isLoadFromStackSlot(const MachineInstr &MI, |
58 | | int &FrameIndex) const override; |
59 | | |
60 | | /// If the specified machine instruction is a direct |
61 | | /// store to a stack slot, return the virtual or physical register number of |
62 | | /// the source reg along with the FrameIndex of the loaded stack slot. If |
63 | | /// not, return 0. This predicate must return 0 if the instruction has |
64 | | /// any side effects other than storing to the stack slot. |
65 | | unsigned isStoreToStackSlot(const MachineInstr &MI, |
66 | | int &FrameIndex) const override; |
67 | | |
68 | | /// Check if the instruction or the bundle of instructions has |
69 | | /// load from stack slots. Return the frameindex and machine memory operand |
70 | | /// if true. |
71 | | bool hasLoadFromStackSlot( |
72 | | const MachineInstr &MI, |
73 | | SmallVectorImpl<const MachineMemOperand *> &Accesses) const override; |
74 | | |
75 | | /// Check if the instruction or the bundle of instructions has |
76 | | /// store to stack slots. Return the frameindex and machine memory operand |
77 | | /// if true. |
78 | | bool hasStoreToStackSlot( |
79 | | const MachineInstr &MI, |
80 | | SmallVectorImpl<const MachineMemOperand *> &Accesses) const override; |
81 | | |
82 | | /// Analyze the branching code at the end of MBB, returning |
83 | | /// true if it cannot be understood (e.g. it's a switch dispatch or isn't |
84 | | /// implemented for a target). Upon success, this returns false and returns |
85 | | /// with the following information in various cases: |
86 | | /// |
87 | | /// 1. If this block ends with no branches (it just falls through to its succ) |
88 | | /// just return false, leaving TBB/FBB null. |
89 | | /// 2. If this block ends with only an unconditional branch, it sets TBB to be |
90 | | /// the destination block. |
91 | | /// 3. If this block ends with a conditional branch and it falls through to a |
92 | | /// successor block, it sets TBB to be the branch destination block and a |
93 | | /// list of operands that evaluate the condition. These operands can be |
94 | | /// passed to other TargetInstrInfo methods to create new branches. |
95 | | /// 4. If this block ends with a conditional branch followed by an |
96 | | /// unconditional branch, it returns the 'true' destination in TBB, the |
97 | | /// 'false' destination in FBB, and a list of operands that evaluate the |
98 | | /// condition. These operands can be passed to other TargetInstrInfo |
99 | | /// methods to create new branches. |
100 | | /// |
101 | | /// Note that removeBranch and insertBranch must be implemented to support |
102 | | /// cases where this method returns success. |
103 | | /// |
104 | | /// If AllowModify is true, then this routine is allowed to modify the basic |
105 | | /// block (e.g. delete instructions after the unconditional branch). |
106 | | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
107 | | MachineBasicBlock *&FBB, |
108 | | SmallVectorImpl<MachineOperand> &Cond, |
109 | | bool AllowModify) const override; |
110 | | |
111 | | /// Remove the branching code at the end of the specific MBB. |
112 | | /// This is only invoked in cases where AnalyzeBranch returns success. It |
113 | | /// returns the number of instructions that were removed. |
114 | | unsigned removeBranch(MachineBasicBlock &MBB, |
115 | | int *BytesRemoved = nullptr) const override; |
116 | | |
117 | | /// Insert branch code into the end of the specified MachineBasicBlock. |
118 | | /// The operands to this method are the same as those |
119 | | /// returned by AnalyzeBranch. This is only invoked in cases where |
120 | | /// AnalyzeBranch returns success. It returns the number of instructions |
121 | | /// inserted. |
122 | | /// |
123 | | /// It is also invoked by tail merging to add unconditional branches in |
124 | | /// cases where AnalyzeBranch doesn't apply because there was no original |
125 | | /// branch to analyze. At least this much must be implemented, else tail |
126 | | /// merging needs to be disabled. |
127 | | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
128 | | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
129 | | const DebugLoc &DL, |
130 | | int *BytesAdded = nullptr) const override; |
131 | | |
132 | | /// Analyze the loop code, return true if it cannot be understood. Upon |
133 | | /// success, this function returns false and returns information about the |
134 | | /// induction variable and compare instruction used at the end. |
135 | | bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, |
136 | | MachineInstr *&CmpInst) const override; |
137 | | |
138 | | /// Generate code to reduce the loop iteration by one and check if the loop |
139 | | /// is finished. Return the value/register of the new loop count. We need |
140 | | /// this function when peeling off one or more iterations of a loop. This |
141 | | /// function assumes the nth iteration is peeled first. |
142 | | unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, |
143 | | MachineInstr *IndVar, MachineInstr &Cmp, |
144 | | SmallVectorImpl<MachineOperand> &Cond, |
145 | | SmallVectorImpl<MachineInstr *> &PrevInsts, |
146 | | unsigned Iter, unsigned MaxIter) const override; |
147 | | |
148 | | /// Return true if it's profitable to predicate |
149 | | /// instructions with accumulated instruction latency of "NumCycles" |
150 | | /// of the specified basic block, where the probability of the instructions |
151 | | /// being executed is given by Probability, and Confidence is a measure |
152 | | /// of our confidence that it will be properly predicted. |
153 | | bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, |
154 | | unsigned ExtraPredCycles, |
155 | | BranchProbability Probability) const override; |
156 | | |
157 | | /// Second variant of isProfitableToIfCvt. This one |
158 | | /// checks for the case where two basic blocks from true and false path |
159 | | /// of a if-then-else (diamond) are predicated on mutally exclusive |
160 | | /// predicates, where the probability of the true path being taken is given |
161 | | /// by Probability, and Confidence is a measure of our confidence that it |
162 | | /// will be properly predicted. |
163 | | bool isProfitableToIfCvt(MachineBasicBlock &TMBB, |
164 | | unsigned NumTCycles, unsigned ExtraTCycles, |
165 | | MachineBasicBlock &FMBB, |
166 | | unsigned NumFCycles, unsigned ExtraFCycles, |
167 | | BranchProbability Probability) const override; |
168 | | |
169 | | /// Return true if it's profitable for if-converter to duplicate instructions |
170 | | /// of specified accumulated instruction latencies in the specified MBB to |
171 | | /// enable if-conversion. |
172 | | /// The probability of the instructions being executed is given by |
173 | | /// Probability, and Confidence is a measure of our confidence that it |
174 | | /// will be properly predicted. |
175 | | bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, |
176 | | BranchProbability Probability) const override; |
177 | | |
178 | | /// Emit instructions to copy a pair of physical registers. |
179 | | /// |
180 | | /// This function should support copies within any legal register class as |
181 | | /// well as any cross-class copies created during instruction selection. |
182 | | /// |
183 | | /// The source and destination registers may overlap, which may require a |
184 | | /// careful implementation when multiple copy instructions are required for |
185 | | /// large registers. See for example the ARM target. |
186 | | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
187 | | const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, |
188 | | bool KillSrc) const override; |
189 | | |
190 | | /// Store the specified register of the given register class to the specified |
191 | | /// stack frame index. The store instruction is to be added to the given |
192 | | /// machine basic block before the specified machine instruction. If isKill |
193 | | /// is true, the register operand is the last use and must be marked kill. |
194 | | void storeRegToStackSlot(MachineBasicBlock &MBB, |
195 | | MachineBasicBlock::iterator MBBI, |
196 | | unsigned SrcReg, bool isKill, int FrameIndex, |
197 | | const TargetRegisterClass *RC, |
198 | | const TargetRegisterInfo *TRI) const override; |
199 | | |
200 | | /// Load the specified register of the given register class from the specified |
201 | | /// stack frame index. The load instruction is to be added to the given |
202 | | /// machine basic block before the specified machine instruction. |
203 | | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
204 | | MachineBasicBlock::iterator MBBI, |
205 | | unsigned DestReg, int FrameIndex, |
206 | | const TargetRegisterClass *RC, |
207 | | const TargetRegisterInfo *TRI) const override; |
208 | | |
209 | | /// This function is called for all pseudo instructions |
210 | | /// that remain after register allocation. Many pseudo instructions are |
211 | | /// created to help register allocation. This is the place to convert them |
212 | | /// into real instructions. The target can edit MI in place, or it can insert |
213 | | /// new instructions and erase MI. The function should return true if |
214 | | /// anything was changed. |
215 | | bool expandPostRAPseudo(MachineInstr &MI) const override; |
216 | | |
217 | | /// Get the base register and byte offset of a load/store instr. |
218 | | bool getMemOperandWithOffset(const MachineInstr &LdSt, |
219 | | const MachineOperand *&BaseOp, |
220 | | int64_t &Offset, |
221 | | const TargetRegisterInfo *TRI) const override; |
222 | | |
223 | | /// Reverses the branch condition of the specified condition list, |
224 | | /// returning false on success and true if it cannot be reversed. |
225 | | bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) |
226 | | const override; |
227 | | |
228 | | /// Insert a noop into the instruction stream at the specified point. |
229 | | void insertNoop(MachineBasicBlock &MBB, |
230 | | MachineBasicBlock::iterator MI) const override; |
231 | | |
232 | | /// Returns true if the instruction is already predicated. |
233 | | bool isPredicated(const MachineInstr &MI) const override; |
234 | | |
235 | | /// Return true for post-incremented instructions. |
236 | | bool isPostIncrement(const MachineInstr &MI) const override; |
237 | | |
238 | | /// Convert the instruction into a predicated instruction. |
239 | | /// It returns true if the operation was successful. |
240 | | bool PredicateInstruction(MachineInstr &MI, |
241 | | ArrayRef<MachineOperand> Cond) const override; |
242 | | |
243 | | /// Returns true if the first specified predicate |
244 | | /// subsumes the second, e.g. GE subsumes GT. |
245 | | bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, |
246 | | ArrayRef<MachineOperand> Pred2) const override; |
247 | | |
248 | | /// If the specified instruction defines any predicate |
249 | | /// or condition code register(s) used for predication, returns true as well |
250 | | /// as the definition predicate(s) by reference. |
251 | | bool DefinesPredicate(MachineInstr &MI, |
252 | | std::vector<MachineOperand> &Pred) const override; |
253 | | |
254 | | /// Return true if the specified instruction can be predicated. |
255 | | /// By default, this returns true for every instruction with a |
256 | | /// PredicateOperand. |
257 | | bool isPredicable(const MachineInstr &MI) const override; |
258 | | |
259 | | /// Test if the given instruction should be considered a scheduling boundary. |
260 | | /// This primarily includes labels and terminators. |
261 | | bool isSchedulingBoundary(const MachineInstr &MI, |
262 | | const MachineBasicBlock *MBB, |
263 | | const MachineFunction &MF) const override; |
264 | | |
265 | | /// Measure the specified inline asm to determine an approximation of its |
266 | | /// length. |
267 | | unsigned getInlineAsmLength( |
268 | | const char *Str, |
269 | | const MCAsmInfo &MAI, |
270 | | const TargetSubtargetInfo *STI = nullptr) const override; |
271 | | |
272 | | /// Allocate and return a hazard recognizer to use for this target when |
273 | | /// scheduling the machine instructions after register allocation. |
274 | | ScheduleHazardRecognizer* |
275 | | CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, |
276 | | const ScheduleDAG *DAG) const override; |
277 | | |
278 | | /// For a comparison instruction, return the source registers |
279 | | /// in SrcReg and SrcReg2 if having two register operands, and the value it |
280 | | /// compares against in CmpValue. Return true if the comparison instruction |
281 | | /// can be analyzed. |
282 | | bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, |
283 | | unsigned &SrcReg2, int &Mask, int &Value) const override; |
284 | | |
285 | | /// Compute the instruction latency of a given instruction. |
286 | | /// If the instruction has higher cost when predicated, it's returned via |
287 | | /// PredCost. |
288 | | unsigned getInstrLatency(const InstrItineraryData *ItinData, |
289 | | const MachineInstr &MI, |
290 | | unsigned *PredCost = nullptr) const override; |
291 | | |
292 | | /// Create machine specific model for scheduling. |
293 | | DFAPacketizer * |
294 | | CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; |
295 | | |
296 | | // Sometimes, it is possible for the target |
297 | | // to tell, even without aliasing information, that two MIs access different |
298 | | // memory addresses. This function returns true if two MIs access different |
299 | | // memory addresses and false otherwise. |
300 | | bool |
301 | | areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, |
302 | | const MachineInstr &MIb, |
303 | | AliasAnalysis *AA = nullptr) const override; |
304 | | |
305 | | /// For instructions with a base and offset, return the position of the |
306 | | /// base register and offset operands. |
307 | | bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, |
308 | | unsigned &OffsetPos) const override; |
309 | | |
310 | | /// If the instruction is an increment of a constant value, return the amount. |
311 | | bool getIncrementValue(const MachineInstr &MI, int &Value) const override; |
312 | | |
313 | | /// getOperandLatency - Compute and return the use operand latency of a given |
314 | | /// pair of def and use. |
315 | | /// In most cases, the static scheduling itinerary was enough to determine the |
316 | | /// operand latency. But it may not be possible for instructions with variable |
317 | | /// number of defs / uses. |
318 | | /// |
319 | | /// This is a raw interface to the itinerary that may be directly overriden by |
320 | | /// a target. Use computeOperandLatency to get the best estimate of latency. |
321 | | int getOperandLatency(const InstrItineraryData *ItinData, |
322 | | const MachineInstr &DefMI, unsigned DefIdx, |
323 | | const MachineInstr &UseMI, |
324 | | unsigned UseIdx) const override; |
325 | | |
326 | | /// Decompose the machine operand's target flags into two values - the direct |
327 | | /// target flag value and any of bit flags that are applied. |
328 | | std::pair<unsigned, unsigned> |
329 | | decomposeMachineOperandsTargetFlags(unsigned TF) const override; |
330 | | |
331 | | /// Return an array that contains the direct target flag values and their |
332 | | /// names. |
333 | | /// |
334 | | /// MIR Serialization is able to serialize only the target flags that are |
335 | | /// defined by this method. |
336 | | ArrayRef<std::pair<unsigned, const char *>> |
337 | | getSerializableDirectMachineOperandTargetFlags() const override; |
338 | | |
339 | | /// Return an array that contains the bitmask target flag values and their |
340 | | /// names. |
341 | | /// |
342 | | /// MIR Serialization is able to serialize only the target flags that are |
343 | | /// defined by this method. |
344 | | ArrayRef<std::pair<unsigned, const char *>> |
345 | | getSerializableBitmaskMachineOperandTargetFlags() const override; |
346 | | |
347 | | bool isTailCall(const MachineInstr &MI) const override; |
348 | | |
349 | | /// HexagonInstrInfo specifics. |
350 | | |
351 | | unsigned createVR(MachineFunction *MF, MVT VT) const; |
352 | | MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, |
353 | | MachineBasicBlock *TargetBB, |
354 | | SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; |
355 | | |
356 | | bool isBaseImmOffset(const MachineInstr &MI) const; |
357 | | bool isAbsoluteSet(const MachineInstr &MI) const; |
358 | | bool isAccumulator(const MachineInstr &MI) const; |
359 | | bool isAddrModeWithOffset(const MachineInstr &MI) const; |
360 | | bool isComplex(const MachineInstr &MI) const; |
361 | | bool isCompoundBranchInstr(const MachineInstr &MI) const; |
362 | | bool isConstExtended(const MachineInstr &MI) const; |
363 | | bool isDeallocRet(const MachineInstr &MI) const; |
364 | | bool isDependent(const MachineInstr &ProdMI, |
365 | | const MachineInstr &ConsMI) const; |
366 | | bool isDotCurInst(const MachineInstr &MI) const; |
367 | | bool isDotNewInst(const MachineInstr &MI) const; |
368 | | bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const; |
369 | | bool isEarlySourceInstr(const MachineInstr &MI) const; |
370 | | bool isEndLoopN(unsigned Opcode) const; |
371 | | bool isExpr(unsigned OpType) const; |
372 | | bool isExtendable(const MachineInstr &MI) const; |
373 | | bool isExtended(const MachineInstr &MI) const; |
374 | | bool isFloat(const MachineInstr &MI) const; |
375 | | bool isHVXMemWithAIndirect(const MachineInstr &I, |
376 | | const MachineInstr &J) const; |
377 | | bool isIndirectCall(const MachineInstr &MI) const; |
378 | | bool isIndirectL4Return(const MachineInstr &MI) const; |
379 | | bool isJumpR(const MachineInstr &MI) const; |
380 | | bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const; |
381 | | bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, |
382 | | const MachineInstr &ESMI) const; |
383 | | bool isLateResultInstr(const MachineInstr &MI) const; |
384 | | bool isLateSourceInstr(const MachineInstr &MI) const; |
385 | | bool isLoopN(const MachineInstr &MI) const; |
386 | | bool isMemOp(const MachineInstr &MI) const; |
387 | | bool isNewValue(const MachineInstr &MI) const; |
388 | | bool isNewValue(unsigned Opcode) const; |
389 | | bool isNewValueInst(const MachineInstr &MI) const; |
390 | | bool isNewValueJump(const MachineInstr &MI) const; |
391 | | bool isNewValueJump(unsigned Opcode) const; |
392 | | bool isNewValueStore(const MachineInstr &MI) const; |
393 | | bool isNewValueStore(unsigned Opcode) const; |
394 | | bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const; |
395 | | bool isPredicatedNew(const MachineInstr &MI) const; |
396 | | bool isPredicatedNew(unsigned Opcode) const; |
397 | | bool isPredicatedTrue(const MachineInstr &MI) const; |
398 | | bool isPredicatedTrue(unsigned Opcode) const; |
399 | | bool isPredicated(unsigned Opcode) const; |
400 | | bool isPredicateLate(unsigned Opcode) const; |
401 | | bool isPredictedTaken(unsigned Opcode) const; |
402 | | bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const; |
403 | | bool isSignExtendingLoad(const MachineInstr &MI) const; |
404 | | bool isSolo(const MachineInstr &MI) const; |
405 | | bool isSpillPredRegOp(const MachineInstr &MI) const; |
406 | | bool isTC1(const MachineInstr &MI) const; |
407 | | bool isTC2(const MachineInstr &MI) const; |
408 | | bool isTC2Early(const MachineInstr &MI) const; |
409 | | bool isTC4x(const MachineInstr &MI) const; |
410 | | bool isToBeScheduledASAP(const MachineInstr &MI1, |
411 | | const MachineInstr &MI2) const; |
412 | | bool isHVXVec(const MachineInstr &MI) const; |
413 | | bool isValidAutoIncImm(const EVT VT, const int Offset) const; |
414 | | bool isValidOffset(unsigned Opcode, int Offset, |
415 | | const TargetRegisterInfo *TRI, bool Extend = true) const; |
416 | | bool isVecAcc(const MachineInstr &MI) const; |
417 | | bool isVecALU(const MachineInstr &MI) const; |
418 | | bool isVecUsableNextPacket(const MachineInstr &ProdMI, |
419 | | const MachineInstr &ConsMI) const; |
420 | | bool isZeroExtendingLoad(const MachineInstr &MI) const; |
421 | | |
422 | | bool addLatencyToSchedule(const MachineInstr &MI1, |
423 | | const MachineInstr &MI2) const; |
424 | | bool canExecuteInBundle(const MachineInstr &First, |
425 | | const MachineInstr &Second) const; |
426 | | bool doesNotReturn(const MachineInstr &CallMI) const; |
427 | | bool hasEHLabel(const MachineBasicBlock *B) const; |
428 | | bool hasNonExtEquivalent(const MachineInstr &MI) const; |
429 | | bool hasPseudoInstrPair(const MachineInstr &MI) const; |
430 | | bool hasUncondBranch(const MachineBasicBlock *B) const; |
431 | | bool mayBeCurLoad(const MachineInstr &MI) const; |
432 | | bool mayBeNewStore(const MachineInstr &MI) const; |
433 | | bool producesStall(const MachineInstr &ProdMI, |
434 | | const MachineInstr &ConsMI) const; |
435 | | bool producesStall(const MachineInstr &MI, |
436 | | MachineBasicBlock::const_instr_iterator MII) const; |
437 | | bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const; |
438 | | bool PredOpcodeHasJMP_c(unsigned Opcode) const; |
439 | | bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; |
440 | | |
441 | | unsigned getAddrMode(const MachineInstr &MI) const; |
442 | | MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, |
443 | | unsigned &AccessSize) const; |
444 | | SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const; |
445 | | unsigned getCExtOpNum(const MachineInstr &MI) const; |
446 | | HexagonII::CompoundGroup |
447 | | getCompoundCandidateGroup(const MachineInstr &MI) const; |
448 | | unsigned getCompoundOpcode(const MachineInstr &GA, |
449 | | const MachineInstr &GB) const; |
450 | | int getCondOpcode(int Opc, bool sense) const; |
451 | | int getDotCurOp(const MachineInstr &MI) const; |
452 | | int getNonDotCurOp(const MachineInstr &MI) const; |
453 | | int getDotNewOp(const MachineInstr &MI) const; |
454 | | int getDotNewPredJumpOp(const MachineInstr &MI, |
455 | | const MachineBranchProbabilityInfo *MBPI) const; |
456 | | int getDotNewPredOp(const MachineInstr &MI, |
457 | | const MachineBranchProbabilityInfo *MBPI) const; |
458 | | int getDotOldOp(const MachineInstr &MI) const; |
459 | | HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) |
460 | | const; |
461 | | short getEquivalentHWInstr(const MachineInstr &MI) const; |
462 | | unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, |
463 | | const MachineInstr &MI) const; |
464 | | bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; |
465 | | unsigned getInvertedPredicatedOpcode(const int Opc) const; |
466 | | int getMaxValue(const MachineInstr &MI) const; |
467 | | unsigned getMemAccessSize(const MachineInstr &MI) const; |
468 | | int getMinValue(const MachineInstr &MI) const; |
469 | | short getNonExtOpcode(const MachineInstr &MI) const; |
470 | | bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg, |
471 | | unsigned &PredRegPos, unsigned &PredRegFlags) const; |
472 | | short getPseudoInstrPair(const MachineInstr &MI) const; |
473 | | short getRegForm(const MachineInstr &MI) const; |
474 | | unsigned getSize(const MachineInstr &MI) const; |
475 | | uint64_t getType(const MachineInstr &MI) const; |
476 | | unsigned getUnits(const MachineInstr &MI) const; |
477 | | |
478 | | MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const; |
479 | | |
480 | | /// getInstrTimingClassLatency - Compute the instruction latency of a given |
481 | | /// instruction using Timing Class information, if available. |
482 | | unsigned nonDbgBBSize(const MachineBasicBlock *BB) const; |
483 | | unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const; |
484 | | |
485 | | void immediateExtend(MachineInstr &MI) const; |
486 | | bool invertAndChangeJumpTarget(MachineInstr &MI, |
487 | | MachineBasicBlock *NewTarget) const; |
488 | | void genAllInsnTimingClasses(MachineFunction &MF) const; |
489 | | bool reversePredSense(MachineInstr &MI) const; |
490 | | unsigned reversePrediction(unsigned Opcode) const; |
491 | | bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; |
492 | | |
493 | | void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const; |
494 | | bool getBundleNoShuf(const MachineInstr &MIB) const; |
495 | | // Addressing mode relations. |
496 | | short changeAddrMode_abs_io(short Opc) const; |
497 | | short changeAddrMode_io_abs(short Opc) const; |
498 | | short changeAddrMode_io_pi(short Opc) const; |
499 | | short changeAddrMode_io_rr(short Opc) const; |
500 | | short changeAddrMode_pi_io(short Opc) const; |
501 | | short changeAddrMode_rr_io(short Opc) const; |
502 | | short changeAddrMode_rr_ur(short Opc) const; |
503 | | short changeAddrMode_ur_rr(short Opc) const; |
504 | | |
505 | 0 | short changeAddrMode_abs_io(const MachineInstr &MI) const { |
506 | 0 | return changeAddrMode_abs_io(MI.getOpcode()); |
507 | 0 | } |
508 | 1.37k | short changeAddrMode_io_abs(const MachineInstr &MI) const { |
509 | 1.37k | return changeAddrMode_io_abs(MI.getOpcode()); |
510 | 1.37k | } |
511 | 4 | short changeAddrMode_io_rr(const MachineInstr &MI) const { |
512 | 4 | return changeAddrMode_io_rr(MI.getOpcode()); |
513 | 4 | } |
514 | 1 | short changeAddrMode_rr_io(const MachineInstr &MI) const { |
515 | 1 | return changeAddrMode_rr_io(MI.getOpcode()); |
516 | 1 | } |
517 | 28 | short changeAddrMode_rr_ur(const MachineInstr &MI) const { |
518 | 28 | return changeAddrMode_rr_ur(MI.getOpcode()); |
519 | 28 | } |
520 | 0 | short changeAddrMode_ur_rr(const MachineInstr &MI) const { |
521 | 0 | return changeAddrMode_ur_rr(MI.getOpcode()); |
522 | 0 | } |
523 | | }; |
524 | | |
525 | | } // end namespace llvm |
526 | | |
527 | | #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H |