Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
Line
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Source (jump to first uncovered line)
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//===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements NewValueJump pass in Hexagon.
10
// Ideally, we should merge this as a Peephole pass prior to register
11
// allocation, but because we have a spill in between the feeder and new value
12
// jump instructions, we are forced to write after register allocation.
13
// Having said that, we should re-attempt to pull this earlier at some point
14
// in future.
15
16
// The basic approach looks for sequence of predicated jump, compare instruciton
17
// that genereates the predicate and, the feeder to the predicate. Once it finds
18
// all, it collapses compare and jump instruction into a new value jump
19
// intstructions.
20
//
21
//===----------------------------------------------------------------------===//
22
23
#include "Hexagon.h"
24
#include "HexagonInstrInfo.h"
25
#include "HexagonRegisterInfo.h"
26
#include "HexagonSubtarget.h"
27
#include "llvm/ADT/Statistic.h"
28
#include "llvm/CodeGen/MachineBasicBlock.h"
29
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
30
#include "llvm/CodeGen/MachineFunction.h"
31
#include "llvm/CodeGen/MachineFunctionPass.h"
32
#include "llvm/CodeGen/MachineInstr.h"
33
#include "llvm/CodeGen/MachineInstrBuilder.h"
34
#include "llvm/CodeGen/MachineOperand.h"
35
#include "llvm/CodeGen/MachineRegisterInfo.h"
36
#include "llvm/CodeGen/TargetOpcodes.h"
37
#include "llvm/CodeGen/TargetRegisterInfo.h"
38
#include "llvm/CodeGen/TargetSubtargetInfo.h"
39
#include "llvm/IR/DebugLoc.h"
40
#include "llvm/MC/MCInstrDesc.h"
41
#include "llvm/Pass.h"
42
#include "llvm/Support/BranchProbability.h"
43
#include "llvm/Support/CommandLine.h"
44
#include "llvm/Support/Debug.h"
45
#include "llvm/Support/ErrorHandling.h"
46
#include "llvm/Support/MathExtras.h"
47
#include "llvm/Support/raw_ostream.h"
48
#include <cassert>
49
#include <cstdint>
50
#include <iterator>
51
52
using namespace llvm;
53
54
#define DEBUG_TYPE "hexagon-nvj"
55
56
STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
57
58
static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
59
    cl::desc("Maximum number of predicated jumps to be converted to "
60
    "New Value Jump"));
61
62
static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
63
    cl::ZeroOrMore, cl::init(false),
64
    cl::desc("Disable New Value Jumps"));
65
66
namespace llvm {
67
68
FunctionPass *createHexagonNewValueJump();
69
void initializeHexagonNewValueJumpPass(PassRegistry&);
70
71
} // end namespace llvm
72
73
namespace {
74
75
  struct HexagonNewValueJump : public MachineFunctionPass {
76
    static char ID;
77
78
866
    HexagonNewValueJump() : MachineFunctionPass(ID) {}
79
80
862
    void getAnalysisUsage(AnalysisUsage &AU) const override {
81
862
      AU.addRequired<MachineBranchProbabilityInfo>();
82
862
      MachineFunctionPass::getAnalysisUsage(AU);
83
862
    }
84
85
4.23k
    StringRef getPassName() const override { return "Hexagon NewValueJump"; }
86
87
    bool runOnMachineFunction(MachineFunction &Fn) override;
88
89
862
    MachineFunctionProperties getRequiredProperties() const override {
90
862
      return MachineFunctionProperties().set(
91
862
          MachineFunctionProperties::Property::NoVRegs);
92
862
    }
93
94
  private:
95
    const HexagonInstrInfo *QII;
96
    const HexagonRegisterInfo *QRI;
97
98
    /// A handle to the branch probability pass.
99
    const MachineBranchProbabilityInfo *MBPI;
100
101
    bool isNewValueJumpCandidate(const MachineInstr &MI) const;
102
  };
103
104
} // end anonymous namespace
105
106
char HexagonNewValueJump::ID = 0;
107
108
101k
INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
109
101k
                      "Hexagon NewValueJump", false, false)
110
101k
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
111
101k
INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
112
                    "Hexagon NewValueJump", false, false)
113
114
// We have identified this II could be feeder to NVJ,
115
// verify that it can be.
116
static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
117
                                      const TargetRegisterInfo *TRI,
118
                                      MachineBasicBlock::iterator II,
119
                                      MachineBasicBlock::iterator end,
120
                                      MachineBasicBlock::iterator skip,
121
137
                                      MachineFunction &MF) {
122
137
  // Predicated instruction can not be feeder to NVJ.
123
137
  if (QII->isPredicated(*II))
124
0
    return false;
125
137
126
137
  // Bail out if feederReg is a paired register (double regs in
127
137
  // our case). One would think that we can check to see if a given
128
137
  // register cmpReg1 or cmpReg2 is a sub register of feederReg
129
137
  // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
130
137
  // before the callsite of this function
131
137
  // But we can not as it comes in the following fashion.
132
137
  //    %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
133
137
  //    %r0 = KILL %r0, implicit killed %d0
134
137
  //    %p0 = CMPEQri killed %r0, 0
135
137
  // Hence, we need to check if it's a KILL instruction.
136
137
  if (II->getOpcode() == TargetOpcode::KILL)
137
0
    return false;
138
137
139
137
  if (II->isImplicitDef())
140
0
    return false;
141
137
142
137
  if (QII->isSolo(*II))
143
1
    return false;
144
136
145
136
  if (QII->isFloat(*II))
146
2
    return false;
147
134
148
134
  // Make sure that the (unique) def operand is a register from IntRegs.
149
134
  bool HadDef = false;
150
406
  for (const MachineOperand &Op : II->operands()) {
151
406
    if (!Op.isReg() || 
!Op.isDef()291
)
152
270
      continue;
153
136
    if (HadDef)
154
2
      return false;
155
134
    HadDef = true;
156
134
    if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
157
0
      return false;
158
134
  }
159
134
  assert(HadDef);
160
132
161
132
  // Make sure there is no 'def' or 'use' of any of the uses of
162
132
  // feeder insn between its definition, this MI and jump, jmpInst
163
132
  // skipping compare, cmpInst.
164
132
  // Here's the example.
165
132
  //    r21=memub(r22+r24<<#0)
166
132
  //    p0 = cmp.eq(r21, #0)
167
132
  //    r4=memub(r3+r21<<#0)
168
132
  //    if (p0.new) jump:t .LBB29_45
169
132
  // Without this check, it will be converted into
170
132
  //    r4=memub(r3+r21<<#0)
171
132
  //    r21=memub(r22+r24<<#0)
172
132
  //    p0 = cmp.eq(r21, #0)
173
132
  //    if (p0.new) jump:t .LBB29_45
174
132
  // and result WAR hazards if converted to New Value Jump.
175
481
  for (unsigned i = 0; i < II->getNumOperands(); 
++i349
) {
176
369
    if (II->getOperand(i).isReg() &&
177
369
        
(267
II->getOperand(i).isUse()267
||
II->getOperand(i).isDef()132
)) {
178
267
      MachineBasicBlock::iterator localII = II;
179
267
      ++localII;
180
267
      unsigned Reg = II->getOperand(i).getReg();
181
699
      for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
182
452
           
++localBegin432
) {
183
452
        if (localBegin == skip)
184
253
          continue;
185
199
        // Check for Subregisters too.
186
199
        if (localBegin->modifiesRegister(Reg, TRI) ||
187
199
            
localBegin->readsRegister(Reg, TRI)195
)
188
20
          return false;
189
199
      }
190
267
    }
191
369
  }
192
132
  
return true112
;
193
132
}
194
195
// These are the common checks that need to performed
196
// to determine if
197
// 1. compare instruction can be moved before jump.
198
// 2. feeder to the compare instruction can be moved before jump.
199
static bool commonChecksToProhibitNewValueJump(bool afterRA,
200
921
                          MachineBasicBlock::iterator MII) {
201
921
  // If store in path, bail out.
202
921
  if (MII->mayStore())
203
48
    return false;
204
873
205
873
  // if call in path, bail out.
206
873
  if (MII->isCall())
207
20
    return false;
208
853
209
853
  // if NVJ is running prior to RA, do the following checks.
210
853
  if (!afterRA) {
211
0
    // The following Target Opcode instructions are spurious
212
0
    // to new value jump. If they are in the path, bail out.
213
0
    // KILL sets kill flag on the opcode. It also sets up a
214
0
    // single register, out of pair.
215
0
    //    %d0 = S2_lsr_r_p killed %d0, killed %r2
216
0
    //    %r0 = KILL %r0, implicit killed %d0
217
0
    //    %p0 = C2_cmpeqi killed %r0, 0
218
0
    // PHI can be anything after RA.
219
0
    // COPY can remateriaze things in between feeder, compare and nvj.
220
0
    if (MII->getOpcode() == TargetOpcode::KILL ||
221
0
        MII->getOpcode() == TargetOpcode::PHI ||
222
0
        MII->getOpcode() == TargetOpcode::COPY)
223
0
      return false;
224
0
225
0
    // The following pseudo Hexagon instructions sets "use" and "def"
226
0
    // of registers by individual passes in the backend. At this time,
227
0
    // we don't know the scope of usage and definitions of these
228
0
    // instructions.
229
0
    if (MII->getOpcode() == Hexagon::LDriw_pred ||
230
0
        MII->getOpcode() == Hexagon::STriw_pred)
231
0
      return false;
232
853
  }
233
853
234
853
  return true;
235
853
}
236
237
static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
238
                                     const TargetRegisterInfo *TRI,
239
                                     MachineBasicBlock::iterator II,
240
                                     unsigned pReg,
241
                                     bool secondReg,
242
                                     bool optLocation,
243
                                     MachineBasicBlock::iterator end,
244
407
                                     MachineFunction &MF) {
245
407
  MachineInstr &MI = *II;
246
407
247
407
  // If the second operand of the compare is an imm, make sure it's in the
248
407
  // range specified by the arch.
249
407
  if (!secondReg) {
250
334
    const MachineOperand &Op2 = MI.getOperand(2);
251
334
    if (!Op2.isImm())
252
0
      return false;
253
334
254
334
    int64_t v = Op2.getImm();
255
334
    bool Valid = false;
256
334
257
334
    switch (MI.getOpcode()) {
258
334
      case Hexagon::C2_cmpeqi:
259
184
      case Hexagon::C4_cmpneqi:
260
184
      case Hexagon::C2_cmpgti:
261
184
      case Hexagon::C4_cmpltei:
262
184
        Valid = (isUInt<5>(v) || 
v == -121
);
263
184
        break;
264
184
      case Hexagon::C2_cmpgtui:
265
150
      case Hexagon::C4_cmplteui:
266
150
        Valid = isUInt<5>(v);
267
150
        break;
268
150
      case Hexagon::S2_tstbit_i:
269
0
      case Hexagon::S4_ntstbit_i:
270
0
        Valid = (v == 0);
271
0
        break;
272
334
    }
273
334
274
334
    if (!Valid)
275
18
      return false;
276
389
  }
277
389
278
389
  unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
279
389
  cmpReg1 = MI.getOperand(1).getReg();
280
389
281
389
  if (secondReg) {
282
73
    cmpOp2 = MI.getOperand(2).getReg();
283
73
284
73
    // If the same register appears as both operands, we cannot generate a new
285
73
    // value compare. Only one operand may use the .new suffix.
286
73
    if (cmpReg1 == cmpOp2)
287
1
      return false;
288
72
289
72
    // Make sure that the second register is not from COPY
290
72
    // at machine code level, we don't need this, but if we decide
291
72
    // to move new value jump prior to RA, we would be needing this.
292
72
    MachineRegisterInfo &MRI = MF.getRegInfo();
293
72
    if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
294
0
      MachineInstr *def = MRI.getVRegDef(cmpOp2);
295
0
      if (def->getOpcode() == TargetOpcode::COPY)
296
0
        return false;
297
388
    }
298
72
  }
299
388
300
388
  // Walk the instructions after the compare (predicate def) to the jump,
301
388
  // and satisfy the following conditions.
302
388
  ++II;
303
785
  for (MachineBasicBlock::iterator localII = II; localII != end; 
++localII397
) {
304
541
    if (localII->isDebugInstr())
305
0
      continue;
306
541
307
541
    // Check 1.
308
541
    // If "common" checks fail, bail out.
309
541
    if (!commonChecksToProhibitNewValueJump(optLocation, localII))
310
34
      return false;
311
507
312
507
    // Check 2.
313
507
    // If there is a def or use of predicate (result of compare), bail out.
314
507
    if (localII->modifiesRegister(pReg, TRI) ||
315
507
        localII->readsRegister(pReg, TRI))
316
3
      return false;
317
504
318
504
    // Check 3.
319
504
    // If there is a def of any of the use of the compare (operands of compare),
320
504
    // bail out.
321
504
    // Eg.
322
504
    //    p0 = cmp.eq(r2, r0)
323
504
    //    r2 = r4
324
504
    //    if (p0.new) jump:t .LBB28_3
325
504
    if (localII->modifiesRegister(cmpReg1, TRI) ||
326
504
        
(403
secondReg403
&&
localII->modifiesRegister(cmpOp2, TRI)65
))
327
107
      return false;
328
504
  }
329
388
  
return true244
;
330
388
}
331
332
// Given a compare operator, return a matching New Value Jump compare operator.
333
// Make sure that MI here is included in isNewValueJumpCandidate.
334
static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
335
                                      bool secondRegNewified,
336
                                      MachineBasicBlock *jmpTarget,
337
                                      const MachineBranchProbabilityInfo
338
112
                                      *MBPI) {
339
112
  bool taken = false;
340
112
  MachineBasicBlock *Src = MI->getParent();
341
112
  const BranchProbability Prediction =
342
112
    MBPI->getEdgeProbability(Src, jmpTarget);
343
112
344
112
  if (Prediction >= BranchProbability(1,2))
345
53
    taken = true;
346
112
347
112
  switch (MI->getOpcode()) {
348
112
    case Hexagon::C2_cmpeq:
349
11
      return taken ? 
Hexagon::J4_cmpeq_t_jumpnv_t7
350
11
                   : 
Hexagon::J4_cmpeq_t_jumpnv_nt4
;
351
112
352
112
    case Hexagon::C2_cmpeqi:
353
43
      if (reg >= 0)
354
42
        return taken ? 
Hexagon::J4_cmpeqi_t_jumpnv_t16
355
42
                     : 
Hexagon::J4_cmpeqi_t_jumpnv_nt26
;
356
1
      return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
357
1
                   : 
Hexagon::J4_cmpeqn1_t_jumpnv_nt0
;
358
1
359
1
    case Hexagon::C4_cmpneqi:
360
1
      if (reg >= 0)
361
1
        return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
362
1
                     : 
Hexagon::J4_cmpeqi_f_jumpnv_nt0
;
363
0
      return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
364
0
                     Hexagon::J4_cmpeqn1_f_jumpnv_nt;
365
0
366
15
    case Hexagon::C2_cmpgt:
367
15
      if (secondRegNewified)
368
7
        return taken ? 
Hexagon::J4_cmplt_t_jumpnv_t3
369
7
                     : 
Hexagon::J4_cmplt_t_jumpnv_nt4
;
370
8
      return taken ? 
Hexagon::J4_cmpgt_t_jumpnv_t4
371
8
                   : 
Hexagon::J4_cmpgt_t_jumpnv_nt4
;
372
8
373
23
    case Hexagon::C2_cmpgti:
374
23
      if (reg >= 0)
375
23
        return taken ? 
Hexagon::J4_cmpgti_t_jumpnv_t8
376
23
                     : 
Hexagon::J4_cmpgti_t_jumpnv_nt15
;
377
0
      return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
378
0
                   : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
379
0
380
10
    case Hexagon::C2_cmpgtu:
381
10
      if (secondRegNewified)
382
5
        return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
383
5
                     : 
Hexagon::J4_cmpltu_t_jumpnv_nt0
;
384
5
      return taken ? 
Hexagon::J4_cmpgtu_t_jumpnv_t2
385
5
                   : 
Hexagon::J4_cmpgtu_t_jumpnv_nt3
;
386
5
387
7
    case Hexagon::C2_cmpgtui:
388
7
      return taken ? 
Hexagon::J4_cmpgtui_t_jumpnv_t4
389
7
                   : 
Hexagon::J4_cmpgtui_t_jumpnv_nt3
;
390
5
391
5
    case Hexagon::C4_cmpneq:
392
0
      return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
393
0
                   : Hexagon::J4_cmpeq_f_jumpnv_nt;
394
5
395
5
    case Hexagon::C4_cmplte:
396
0
      if (secondRegNewified)
397
0
        return taken ? Hexagon::J4_cmplt_f_jumpnv_t
398
0
                     : Hexagon::J4_cmplt_f_jumpnv_nt;
399
0
      return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
400
0
                   : Hexagon::J4_cmpgt_f_jumpnv_nt;
401
0
402
0
    case Hexagon::C4_cmplteu:
403
0
      if (secondRegNewified)
404
0
        return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
405
0
                     : Hexagon::J4_cmpltu_f_jumpnv_nt;
406
0
      return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
407
0
                   : Hexagon::J4_cmpgtu_f_jumpnv_nt;
408
0
409
1
    case Hexagon::C4_cmpltei:
410
1
      if (reg >= 0)
411
1
        return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
412
1
                     : 
Hexagon::J4_cmpgti_f_jumpnv_nt0
;
413
0
      return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
414
0
                   : Hexagon::J4_cmpgtn1_f_jumpnv_nt;
415
0
416
1
    case Hexagon::C4_cmplteui:
417
1
      return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
418
1
                   : 
Hexagon::J4_cmpgtui_f_jumpnv_nt0
;
419
0
420
0
    default:
421
0
       llvm_unreachable("Could not find matching New Value Jump instruction.");
422
0
  }
423
0
  // return *some value* to avoid compiler warning
424
0
  return 0;
425
0
}
426
427
bool HexagonNewValueJump::isNewValueJumpCandidate(
428
558
    const MachineInstr &MI) const {
429
558
  switch (MI.getOpcode()) {
430
558
  case Hexagon::C2_cmpeq:
431
407
  case Hexagon::C2_cmpeqi:
432
407
  case Hexagon::C2_cmpgt:
433
407
  case Hexagon::C2_cmpgti:
434
407
  case Hexagon::C2_cmpgtu:
435
407
  case Hexagon::C2_cmpgtui:
436
407
  case Hexagon::C4_cmpneq:
437
407
  case Hexagon::C4_cmpneqi:
438
407
  case Hexagon::C4_cmplte:
439
407
  case Hexagon::C4_cmplteu:
440
407
  case Hexagon::C4_cmpltei:
441
407
  case Hexagon::C4_cmplteui:
442
407
    return true;
443
407
444
407
  default:
445
151
    return false;
446
558
  }
447
558
}
448
449
3.37k
bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
450
3.37k
  LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
451
3.37k
                    << "********** Function: " << MF.getName() << "\n");
452
3.37k
453
3.37k
  if (skipFunction(MF.getFunction()))
454
10
    return false;
455
3.36k
456
3.36k
  // If we move NewValueJump before register allocation we'll need live variable
457
3.36k
  // analysis here too.
458
3.36k
459
3.36k
  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
460
3.36k
  QRI = static_cast<const HexagonRegisterInfo *>(
461
3.36k
      MF.getSubtarget().getRegisterInfo());
462
3.36k
  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
463
3.36k
464
3.36k
  if (DisableNewValueJumps ||
465
3.36k
      !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
466
84
    return false;
467
3.27k
468
3.27k
  int nvjCount = DbgNVJCount;
469
3.27k
  int nvjGenerated = 0;
470
3.27k
471
3.27k
  // Loop through all the bb's of the function
472
3.27k
  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
473
8.19k
       MBBb != MBBe; 
++MBBb4.92k
) {
474
4.92k
    MachineBasicBlock *MBB = &*MBBb;
475
4.92k
476
4.92k
    LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
477
4.92k
    LLVM_DEBUG(MBB->dump());
478
4.92k
    LLVM_DEBUG(dbgs() << "\n"
479
4.92k
                      << "********** dumping instr bottom up **********\n");
480
4.92k
    bool foundJump    = false;
481
4.92k
    bool foundCompare = false;
482
4.92k
    bool invertPredicate = false;
483
4.92k
    unsigned predReg = 0; // predicate reg of the jump.
484
4.92k
    unsigned cmpReg1 = 0;
485
4.92k
    int cmpOp2 = 0;
486
4.92k
    MachineBasicBlock::iterator jmpPos;
487
4.92k
    MachineBasicBlock::iterator cmpPos;
488
4.92k
    MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
489
4.92k
    MachineBasicBlock *jmpTarget = nullptr;
490
4.92k
    bool afterRA = false;
491
4.92k
    bool isSecondOpReg = false;
492
4.92k
    bool isSecondOpNewified = false;
493
4.92k
    // Traverse the basic block - bottom up
494
4.92k
    for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
495
31.1k
         MII != E;) {
496
26.5k
      MachineInstr &MI = *--MII;
497
26.5k
      if (MI.isDebugInstr()) {
498
21
        continue;
499
21
      }
500
26.5k
501
26.5k
      if ((nvjCount == 0) || (nvjCount > -1 && 
nvjCount <= nvjGenerated0
))
502
0
        break;
503
26.5k
504
26.5k
      LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
505
26.5k
506
26.5k
      if (!foundJump && 
(23.8k
MI.getOpcode() == Hexagon::J2_jumpt23.8k
||
507
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumptpt23.6k
||
508
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumpf23.6k
||
509
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumpfpt23.2k
||
510
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumptnewpt23.2k
||
511
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumptnew23.2k
||
512
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumpfnewpt23.2k
||
513
23.8k
                         
MI.getOpcode() == Hexagon::J2_jumpfnew23.2k
)) {
514
621
        // This is where you would insert your compare and
515
621
        // instr that feeds compare
516
621
        jmpPos = MII;
517
621
        jmpInstr = &MI;
518
621
        predReg = MI.getOperand(0).getReg();
519
621
        afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
520
621
521
621
        // If ifconverter had not messed up with the kill flags of the
522
621
        // operands, the following check on the kill flag would suffice.
523
621
        // if(!jmpInstr->getOperand(0).isKill()) break;
524
621
525
621
        // This predicate register is live out of BB
526
621
        // this would only work if we can actually use Live
527
621
        // variable analysis on phy regs - but LLVM does not
528
621
        // provide LV analysis on phys regs.
529
621
        //if(LVs.isLiveOut(predReg, *MBB)) break;
530
621
531
621
        // Get all the successors of this block - which will always
532
621
        // be 2. Check if the predicate register is live-in in those
533
621
        // successor. If yes, we can not delete the predicate -
534
621
        // I am doing this only because LLVM does not provide LiveOut
535
621
        // at the BB level.
536
621
        bool predLive = false;
537
621
        for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
538
621
                                                    SIE = MBB->succ_end();
539
1.85k
             SI != SIE; 
++SI1.23k
) {
540
1.23k
          MachineBasicBlock *succMBB = *SI;
541
1.23k
          if (succMBB->isLiveIn(predReg))
542
63
            predLive = true;
543
1.23k
        }
544
621
        if (predLive)
545
33
          break;
546
588
547
588
        if (!MI.getOperand(1).isMBB())
548
0
          continue;
549
588
        jmpTarget = MI.getOperand(1).getMBB();
550
588
        foundJump = true;
551
588
        if (MI.getOpcode() == Hexagon::J2_jumpf ||
552
588
            
MI.getOpcode() == Hexagon::J2_jumpfnewpt192
||
553
588
            
MI.getOpcode() == Hexagon::J2_jumpfnew192
) {
554
396
          invertPredicate = true;
555
396
        }
556
588
        continue;
557
588
      }
558
25.9k
559
25.9k
      // No new value jump if there is a barrier. A barrier has to be in its
560
25.9k
      // own packet. A barrier has zero operands. We conservatively bail out
561
25.9k
      // here if we see any instruction with zero operands.
562
25.9k
      if (foundJump && 
MI.getNumOperands() == 02.71k
)
563
0
        break;
564
25.9k
565
25.9k
      if (foundJump && 
!foundCompare2.71k
&&
MI.getOperand(0).isReg()2.33k
&&
566
25.9k
          
MI.getOperand(0).getReg() == predReg2.15k
) {
567
558
        // Not all compares can be new value compare. Arch Spec: 7.6.1.1
568
558
        if (isNewValueJumpCandidate(MI)) {
569
407
          assert(
570
407
              (MI.getDesc().isCompare()) &&
571
407
              "Only compare instruction can be collapsed into New Value Jump");
572
407
          isSecondOpReg = MI.getOperand(2).isReg();
573
407
574
407
          if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
575
407
                                        afterRA, jmpPos, MF))
576
163
            break;
577
244
578
244
          cmpInstr = &MI;
579
244
          cmpPos = MII;
580
244
          foundCompare = true;
581
244
582
244
          // We need cmpReg1 and cmpOp2(imm or reg) while building
583
244
          // new value jump instruction.
584
244
          cmpReg1 = MI.getOperand(1).getReg();
585
244
586
244
          if (isSecondOpReg)
587
55
            cmpOp2 = MI.getOperand(2).getReg();
588
189
          else
589
189
            cmpOp2 = MI.getOperand(2).getImm();
590
244
          continue;
591
244
        }
592
558
      }
593
25.5k
594
25.5k
      if (foundCompare && 
foundJump380
) {
595
380
        // If "common" checks fail, bail out on this BB.
596
380
        if (!commonChecksToProhibitNewValueJump(afterRA, MII))
597
34
          break;
598
346
599
346
        bool foundFeeder = false;
600
346
        MachineBasicBlock::iterator feederPos = MII;
601
346
        if (MI.getOperand(0).isReg() && 
MI.getOperand(0).isDef()342
&&
602
346
            
(342
MI.getOperand(0).getReg() == cmpReg1342
||
603
342
             
(226
isSecondOpReg226
&&
604
226
              
MI.getOperand(0).getReg() == (unsigned)cmpOp254
))) {
605
137
606
137
          unsigned feederReg = MI.getOperand(0).getReg();
607
137
608
137
          // First try to see if we can get the feeder from the first operand
609
137
          // of the compare. If we can not, and if secondOpReg is true
610
137
          // (second operand of the compare is also register), try that one.
611
137
          // TODO: Try to come up with some heuristic to figure out which
612
137
          // feeder would benefit.
613
137
614
137
          if (feederReg == cmpReg1) {
615
116
            if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
616
22
              if (!isSecondOpReg)
617
19
                break;
618
3
              else
619
3
                continue;
620
94
            } else
621
94
              foundFeeder = true;
622
116
          }
623
137
624
137
          
if (115
!foundFeeder115
&&
isSecondOpReg21
&&
feederReg == (unsigned)cmpOp221
)
625
21
            if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
626
3
              break;
627
112
628
112
          if (isSecondOpReg) {
629
36
            // In case of CMPLT, or CMPLTU, or EQ with the second register
630
36
            // to newify, swap the operands.
631
36
            unsigned COp = cmpInstr->getOpcode();
632
36
            if ((COp == Hexagon::C2_cmpeq || 
COp == Hexagon::C4_cmpneq25
) &&
633
36
                
(feederReg == (unsigned)cmpOp2)11
) {
634
6
              unsigned tmp = cmpReg1;
635
6
              cmpReg1 = cmpOp2;
636
6
              cmpOp2 = tmp;
637
6
            }
638
36
639
36
            // Now we have swapped the operands, all we need to check is,
640
36
            // if the second operand (after swap) is the feeder.
641
36
            // And if it is, make a note.
642
36
            if (feederReg == (unsigned)cmpOp2)
643
12
              isSecondOpNewified = true;
644
36
          }
645
112
646
112
          // Now that we are moving feeder close the jump,
647
112
          // make sure we are respecting the kill values of
648
112
          // the operands of the feeder.
649
112
650
224
          auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
651
675
            for (MachineOperand &MO : MI.operands()) {
652
675
              if (!MO.isReg() || 
!MO.isUse()497
)
653
402
                continue;
654
273
              unsigned UseR = MO.getReg();
655
434
              for (auto I = std::next(MI.getIterator()); I != jmpPos; 
++I161
) {
656
162
                if (I == cmpPos)
657
125
                  continue;
658
105
                
for (MachineOperand &Op : I->operands())37
{
659
105
                  if (!Op.isReg() || 
!Op.isUse()78
||
!Op.isKill()41
)
660
71
                    continue;
661
34
                  if (Op.getReg() != UseR)
662
33
                    continue;
663
1
                  // We found that there is kill of a use register
664
1
                  // Set up a kill flag on the register
665
1
                  Op.setIsKill(false);
666
1
                  MO.setIsKill(true);
667
1
                  return;
668
1
                }
669
37
              }
670
273
            }
671
224
          };
672
112
673
112
          TransferKills(*feederPos);
674
112
          TransferKills(*cmpPos);
675
112
          bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
676
112
          bool MO2IsKill = isSecondOpReg && 
cmpPos->killsRegister(cmpOp2, QRI)36
;
677
112
678
112
          MBB->splice(jmpPos, MI.getParent(), MI);
679
112
          MBB->splice(jmpPos, MI.getParent(), cmpInstr);
680
112
          DebugLoc dl = MI.getDebugLoc();
681
112
          MachineInstr *NewMI;
682
112
683
112
          assert((isNewValueJumpCandidate(*cmpInstr)) &&
684
112
                 "This compare is not a New Value Jump candidate.");
685
112
          unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
686
112
                                               isSecondOpNewified,
687
112
                                               jmpTarget, MBPI);
688
112
          if (invertPredicate)
689
54
            opc = QII->getInvertedPredicatedOpcode(opc);
690
112
691
112
          if (isSecondOpReg)
692
36
            NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
693
36
                        .addReg(cmpReg1, getKillRegState(MO1IsKill))
694
36
                        .addReg(cmpOp2, getKillRegState(MO2IsKill))
695
36
                        .addMBB(jmpTarget);
696
76
697
76
          else
698
76
            NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
699
76
                        .addReg(cmpReg1, getKillRegState(MO1IsKill))
700
76
                        .addImm(cmpOp2)
701
76
                        .addMBB(jmpTarget);
702
112
703
112
          assert(NewMI && "New Value Jump Instruction Not created!");
704
112
          (void)NewMI;
705
112
          if (cmpInstr->getOperand(0).isReg() &&
706
112
              cmpInstr->getOperand(0).isKill())
707
0
            cmpInstr->getOperand(0).setIsKill(false);
708
112
          if (cmpInstr->getOperand(1).isReg() &&
709
112
              cmpInstr->getOperand(1).isKill())
710
65
            cmpInstr->getOperand(1).setIsKill(false);
711
112
          cmpInstr->eraseFromParent();
712
112
          jmpInstr->eraseFromParent();
713
112
          ++nvjGenerated;
714
112
          ++NumNVJGenerated;
715
112
          break;
716
112
        }
717
346
      }
718
25.5k
    }
719
4.92k
  }
720
3.27k
721
3.27k
  return true;
722
3.27k
}
723
724
862
FunctionPass *llvm::createHexagonNewValueJump() {
725
862
  return new HexagonNewValueJump();
726
862
}