Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
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//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Hexagon target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "HexagonTargetTransformInfo.h"
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#include "TargetInfo/HexagonTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
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  cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
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static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
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  cl::init(true), cl::desc("Enable RDF-based optimizations"));
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static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
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  cl::Hidden, cl::ZeroOrMore, cl::init(false),
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  cl::desc("Disable Hexagon Addressing Mode Optimization"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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  cl::Hidden, cl::ZeroOrMore, cl::init(false),
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  cl::desc("Disable Hexagon CFG Optimization"));
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static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
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  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
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static cl::opt<bool> DisableStoreWidening("disable-store-widen",
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  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
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static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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  cl::init(true), cl::Hidden, cl::ZeroOrMore,
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  cl::desc("Early expansion of MUX"));
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static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
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  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
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  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
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static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
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  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
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static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
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  cl::desc("Enable converting conditional transfers into MUX instructions"));
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static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
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  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
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  "predicate instructions"));
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static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
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  cl::init(false), cl::Hidden, cl::ZeroOrMore,
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  cl::desc("Enable loop data prefetch on Hexagon"));
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static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
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  cl::desc("Disable splitting double registers"));
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static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
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  cl::Hidden, cl::desc("Bit simplification"));
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static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
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  cl::Hidden, cl::desc("Loop rescheduling"));
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static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
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  cl::Hidden, cl::desc("Disable backend optimizations"));
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static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
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  cl::Hidden, cl::ZeroOrMore, cl::init(false),
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  cl::desc("Enable Hexagon Vector print instr pass"));
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static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
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  cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
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static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
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  cl::Hidden, cl::ZeroOrMore, cl::init(true),
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  cl::desc("Simplify the CFG after atomic expansion pass"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library.  In particular, it seems that it is not possible to get
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/// things to work on Win32 without this.  Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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3.34k
static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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3.34k
  ScheduleDAGMILive *DAG =
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3.34k
    new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
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3.34k
  DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
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3.34k
  DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
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  DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
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  DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
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  return DAG;
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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                    createVLIWMachineSched);
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namespace llvm {
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  extern char &HexagonExpandCondsetsID;
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  void initializeHexagonBitSimplifyPass(PassRegistry&);
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  void initializeHexagonConstExtendersPass(PassRegistry&);
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  void initializeHexagonConstPropagationPass(PassRegistry&);
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  void initializeHexagonEarlyIfConversionPass(PassRegistry&);
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  void initializeHexagonExpandCondsetsPass(PassRegistry&);
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  void initializeHexagonGenMuxPass(PassRegistry&);
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  void initializeHexagonHardwareLoopsPass(PassRegistry&);
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  void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
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  void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
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  void initializeHexagonNewValueJumpPass(PassRegistry&);
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  void initializeHexagonOptAddrModePass(PassRegistry&);
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  void initializeHexagonPacketizerPass(PassRegistry&);
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  void initializeHexagonRDFOptPass(PassRegistry&);
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  void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
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  void initializeHexagonVExtractPass(PassRegistry&);
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  Pass *createHexagonLoopIdiomPass();
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  Pass *createHexagonVectorLoopCarriedReusePass();
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  FunctionPass *createHexagonBitSimplify();
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  FunctionPass *createHexagonBranchRelaxation();
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  FunctionPass *createHexagonCallFrameInformation();
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  FunctionPass *createHexagonCFGOptimizer();
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  FunctionPass *createHexagonCommonGEP();
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  FunctionPass *createHexagonConstExtenders();
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  FunctionPass *createHexagonConstPropagationPass();
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  FunctionPass *createHexagonCopyToCombine();
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  FunctionPass *createHexagonEarlyIfConversion();
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  FunctionPass *createHexagonFixupHwLoops();
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  FunctionPass *createHexagonGenExtract();
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  FunctionPass *createHexagonGenInsert();
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  FunctionPass *createHexagonGenMux();
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  FunctionPass *createHexagonGenPredicate();
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  FunctionPass *createHexagonHardwareLoops();
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  FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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                                     CodeGenOpt::Level OptLevel);
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  FunctionPass *createHexagonLoopRescheduling();
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  FunctionPass *createHexagonNewValueJump();
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  FunctionPass *createHexagonOptimizeSZextends();
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  FunctionPass *createHexagonOptAddrMode();
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  FunctionPass *createHexagonPacketizer(bool Minimal);
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  FunctionPass *createHexagonPeephole();
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  FunctionPass *createHexagonRDFOpt();
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  FunctionPass *createHexagonSplitConst32AndConst64();
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  FunctionPass *createHexagonSplitDoubleRegs();
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  FunctionPass *createHexagonStoreWidening();
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  FunctionPass *createHexagonVectorPrint();
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  FunctionPass *createHexagonVExtract();
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} // end namespace llvm;
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1.02k
static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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1.02k
  if (!RM.hasValue())
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987
    return Reloc::Static;
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34
  return *RM;
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34
}
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extern "C" void LLVMInitializeHexagonTarget() {
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139k
  // Register the target.
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  RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
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  PassRegistry &PR = *PassRegistry::getPassRegistry();
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139k
  initializeHexagonBitSimplifyPass(PR);
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139k
  initializeHexagonConstExtendersPass(PR);
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  initializeHexagonConstPropagationPass(PR);
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  initializeHexagonEarlyIfConversionPass(PR);
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139k
  initializeHexagonGenMuxPass(PR);
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139k
  initializeHexagonHardwareLoopsPass(PR);
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139k
  initializeHexagonLoopIdiomRecognizePass(PR);
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139k
  initializeHexagonVectorLoopCarriedReusePass(PR);
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139k
  initializeHexagonNewValueJumpPass(PR);
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139k
  initializeHexagonOptAddrModePass(PR);
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139k
  initializeHexagonPacketizerPass(PR);
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139k
  initializeHexagonRDFOptPass(PR);
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139k
  initializeHexagonSplitDoubleRegsPass(PR);
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  initializeHexagonVExtractPass(PR);
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}
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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                                           StringRef CPU, StringRef FS,
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                                           const TargetOptions &Options,
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                                           Optional<Reloc::Model> RM,
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                                           Optional<CodeModel::Model> CM,
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                                           CodeGenOpt::Level OL, bool JIT)
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    // Specify the vector alignment explicitly. For v512x1, the calculated
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    // alignment would be 512*alignment(i1), which is 512 bytes, instead of
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    // the required minimum of 64 bytes.
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    : LLVMTargetMachine(
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          T,
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          "e-m:e-p:32:32:32-a:0-n16:32-"
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          "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
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          "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
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          TT, CPU, FS, Options, getEffectiveRelocModel(RM),
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          getEffectiveCodeModel(CM, CodeModel::Small),
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          (HexagonNoOpt ? CodeGenOpt::None : OL)),
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1.02k
      TLOF(make_unique<HexagonTargetObjectFile>()) {
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1.02k
  initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
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1.02k
  initAsmInfo();
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1.02k
}
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const HexagonSubtarget *
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62.4k
HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
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62.4k
  AttributeList FnAttrs = F.getAttributes();
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62.4k
  Attribute CPUAttr =
230
62.4k
      FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
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62.4k
  Attribute FSAttr =
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62.4k
      FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
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62.4k
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62.4k
  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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62.4k
                        ? 
CPUAttr.getValueAsString().str()41.4k
236
62.4k
                        : 
TargetCPU21.0k
;
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62.4k
  std::string FS = !FSAttr.hasAttribute(Attribute::None)
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62.4k
                       ? 
FSAttr.getValueAsString().str()29.8k
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62.4k
                       : 
TargetFS32.6k
;
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62.4k
241
62.4k
  auto &I = SubtargetMap[CPU + FS];
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62.4k
  if (!I) {
243
1.01k
    // This needs to be done before we create a new subtarget since any
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1.01k
    // creation will depend on the TM and the code generation flags on the
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1.01k
    // function that reside in TargetOptions.
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1.01k
    resetTargetOptions(F);
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1.01k
    I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
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1.01k
  }
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62.4k
  return I.get();
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}
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void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
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23
  PMB.addExtension(
254
23
    PassManagerBuilder::EP_LateLoopOptimizations,
255
23
    [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
256
12
      PM.add(createHexagonLoopIdiomPass());
257
12
    });
258
23
  PMB.addExtension(
259
23
    PassManagerBuilder::EP_LoopOptimizerEnd,
260
23
    [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
261
12
      PM.add(createHexagonVectorLoopCarriedReusePass());
262
12
    });
263
23
}
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TargetTransformInfo
266
30.6k
HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
267
30.6k
  return TargetTransformInfo(HexagonTTIImpl(this, F));
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30.6k
}
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270
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1.01k
HexagonTargetMachine::~HexagonTargetMachine() {}
272
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
275
class HexagonPassConfig : public TargetPassConfig {
276
public:
277
  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
278
1.00k
    : TargetPassConfig(TM, PM) {}
279
280
919
  HexagonTargetMachine &getHexagonTargetMachine() const {
281
919
    return getTM<HexagonTargetMachine>();
282
919
  }
283
284
  ScheduleDAGInstrs *
285
3.34k
  createMachineScheduler(MachineSchedContext *C) const override {
286
3.34k
    return createVLIWMachineSched(C);
287
3.34k
  }
288
289
  void addIRPasses() override;
290
  bool addInstSelector() override;
291
  void addPreRegAlloc() override;
292
  void addPostRegAlloc() override;
293
  void addPreSched2() override;
294
  void addPreEmitPass() override;
295
};
296
} // namespace
297
298
1.00k
TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
299
1.00k
  return new HexagonPassConfig(*this, PM);
300
1.00k
}
301
302
919
void HexagonPassConfig::addIRPasses() {
303
919
  TargetPassConfig::addIRPasses();
304
919
  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
305
919
306
919
  if (!NoOpt) {
307
862
    addPass(createConstantPropagationPass());
308
862
    addPass(createDeadCodeEliminationPass());
309
862
  }
310
919
311
919
  addPass(createAtomicExpandPass());
312
919
313
919
  if (!NoOpt) {
314
862
    if (EnableInitialCFGCleanup)
315
833
      addPass(createCFGSimplificationPass(1, true, true, false, true));
316
862
    if (EnableLoopPrefetch)
317
1
      addPass(createLoopDataPrefetchPass());
318
862
    if (EnableCommGEP)
319
862
      addPass(createHexagonCommonGEP());
320
862
    // Replace certain combinations of shifts and ands with extracts.
321
862
    if (EnableGenExtract)
322
861
      addPass(createHexagonGenExtract());
323
862
  }
324
919
}
325
326
919
bool HexagonPassConfig::addInstSelector() {
327
919
  HexagonTargetMachine &TM = getHexagonTargetMachine();
328
919
  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
329
919
330
919
  if (!NoOpt)
331
862
    addPass(createHexagonOptimizeSZextends());
332
919
333
919
  addPass(createHexagonISelDag(TM, getOptLevel()));
334
919
335
919
  if (!NoOpt) {
336
862
    if (EnableVExtractOpt)
337
862
      addPass(createHexagonVExtract());
338
862
    // Create logical operations on predicate registers.
339
862
    if (EnableGenPred)
340
862
      addPass(createHexagonGenPredicate());
341
862
    // Rotate loops to expose bit-simplification opportunities.
342
862
    if (EnableLoopResched)
343
862
      addPass(createHexagonLoopRescheduling());
344
862
    // Split double registers.
345
862
    if (!DisableHSDR)
346
848
      addPass(createHexagonSplitDoubleRegs());
347
862
    // Bit simplification.
348
862
    if (EnableBitSimplify)
349
856
      addPass(createHexagonBitSimplify());
350
862
    addPass(createHexagonPeephole());
351
862
    // Constant propagation.
352
862
    if (!DisableHCP) {
353
860
      addPass(createHexagonConstPropagationPass());
354
860
      addPass(&UnreachableMachineBlockElimID);
355
860
    }
356
862
    if (EnableGenInsert)
357
862
      addPass(createHexagonGenInsert());
358
862
    if (EnableEarlyIf)
359
858
      addPass(createHexagonEarlyIfConversion());
360
862
  }
361
919
362
919
  return false;
363
919
}
364
365
919
void HexagonPassConfig::addPreRegAlloc() {
366
919
  if (getOptLevel() != CodeGenOpt::None) {
367
862
    if (EnableCExtOpt)
368
861
      addPass(createHexagonConstExtenders());
369
862
    if (EnableExpandCondsets)
370
857
      insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
371
862
    if (!DisableStoreWidening)
372
862
      addPass(createHexagonStoreWidening());
373
862
    if (!DisableHardwareLoops)
374
862
      addPass(createHexagonHardwareLoops());
375
862
  }
376
919
  if (TM->getOptLevel() >= CodeGenOpt::Default)
377
861
    addPass(&MachinePipelinerID);
378
919
}
379
380
919
void HexagonPassConfig::addPostRegAlloc() {
381
919
  if (getOptLevel() != CodeGenOpt::None) {
382
862
    if (EnableRDFOpt)
383
858
      addPass(createHexagonRDFOpt());
384
862
    if (!DisableHexagonCFGOpt)
385
862
      addPass(createHexagonCFGOptimizer());
386
862
    if (!DisableAModeOpt)
387
859
      addPass(createHexagonOptAddrMode());
388
862
  }
389
919
}
390
391
919
void HexagonPassConfig::addPreSched2() {
392
919
  addPass(createHexagonCopyToCombine());
393
919
  if (getOptLevel() != CodeGenOpt::None)
394
862
    addPass(&IfConverterID);
395
919
  addPass(createHexagonSplitConst32AndConst64());
396
919
}
397
398
919
void HexagonPassConfig::addPreEmitPass() {
399
919
  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
400
919
401
919
  if (!NoOpt)
402
862
    addPass(createHexagonNewValueJump());
403
919
404
919
  addPass(createHexagonBranchRelaxation());
405
919
406
919
  if (!NoOpt) {
407
862
    if (!DisableHardwareLoops)
408
862
      addPass(createHexagonFixupHwLoops());
409
862
    // Generate MUX from pairs of conditional transfers.
410
862
    if (EnableGenMux)
411
862
      addPass(createHexagonGenMux());
412
862
  }
413
919
414
919
  // Packetization is mandatory: it handles gather/scatter at all opt levels.
415
919
  addPass(createHexagonPacketizer(NoOpt), false);
416
919
417
919
  if (EnableVectorPrint)
418
2
    addPass(createHexagonVectorPrint(), false);
419
919
420
919
  // Add CFI instructions if necessary.
421
919
  addPass(createHexagonCallFrameInformation(), false);
422
919
}