Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
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//===- HexagonVExtract.cpp ------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This pass will replace multiple occurrences of V6_extractw from the same
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// vector register with a combination of a vector store and scalar loads.
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/PassSupport.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include <map>
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using namespace llvm;
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static cl::opt<unsigned> VExtractThreshold("hexagon-vextract-threshold",
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  cl::Hidden, cl::ZeroOrMore, cl::init(1),
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  cl::desc("Threshold for triggering vextract replacement"));
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namespace llvm {
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  void initializeHexagonVExtractPass(PassRegistry& Registry);
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  FunctionPass *createHexagonVExtract();
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}
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namespace {
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  class HexagonVExtract : public MachineFunctionPass {
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  public:
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    static char ID;
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    HexagonVExtract() : MachineFunctionPass(ID) {}
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    StringRef getPassName() const override {
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      return "Hexagon optimize vextract";
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    }
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    void getAnalysisUsage(AnalysisUsage &AU) const override {
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      MachineFunctionPass::getAnalysisUsage(AU);
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    }
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    bool runOnMachineFunction(MachineFunction &MF) override;
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  private:
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    const HexagonSubtarget *HST = nullptr;
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    const HexagonInstrInfo *HII = nullptr;
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    unsigned genElemLoad(MachineInstr *ExtI, unsigned BaseR,
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                         MachineRegisterInfo &MRI);
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  };
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  char HexagonVExtract::ID = 0;
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}
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INITIALIZE_PASS(HexagonVExtract, "hexagon-vextract",
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  "Hexagon optimize vextract", false, false)
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unsigned HexagonVExtract::genElemLoad(MachineInstr *ExtI, unsigned BaseR,
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                                      MachineRegisterInfo &MRI) {
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  MachineBasicBlock &ExtB = *ExtI->getParent();
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  DebugLoc DL = ExtI->getDebugLoc();
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  unsigned ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
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  unsigned ExtIdxR = ExtI->getOperand(2).getReg();
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  unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
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  // Simplified check for a compile-time constant value of ExtIdxR.
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  if (ExtIdxS == 0) {
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    MachineInstr *DI = MRI.getVRegDef(ExtIdxR);
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    if (DI->getOpcode() == Hexagon::A2_tfrsi) {
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      unsigned V = DI->getOperand(1).getImm();
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      V &= (HST->getVectorLength()-1) & -4u;
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      BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
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        .addReg(BaseR)
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        .addImm(V);
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      return ElemR;
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    }
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  }
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  unsigned IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
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  BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
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    .add(ExtI->getOperand(2))
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    .addImm(-4);
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  BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
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    .addReg(BaseR)
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    .addReg(IdxR)
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    .addImm(0);
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  return ElemR;
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}
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bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
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  HST = &MF.getSubtarget<HexagonSubtarget>();
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  HII = HST->getInstrInfo();
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  const auto &HRI = *HST->getRegisterInfo();
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  MachineRegisterInfo &MRI = MF.getRegInfo();
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  MachineFrameInfo &MFI = MF.getFrameInfo();
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  std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap;
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  bool Changed = false;
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  for (MachineBasicBlock &MBB : MF) {
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    for (MachineInstr &MI : MBB) {
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      unsigned Opc = MI.getOpcode();
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      if (Opc != Hexagon::V6_extractw)
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        continue;
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      unsigned VecR = MI.getOperand(1).getReg();
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      VExtractMap[VecR].push_back(&MI);
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    }
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  }
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  for (auto &P : VExtractMap) {
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    unsigned VecR = P.first;
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    if (P.second.size() <= VExtractThreshold)
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      continue;
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    const auto &VecRC = *MRI.getRegClass(VecR);
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    int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC),
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                                        HRI.getSpillAlignment(VecRC));
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    MachineInstr *DefI = MRI.getVRegDef(VecR);
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    MachineBasicBlock::iterator At = std::next(DefI->getIterator());
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    MachineBasicBlock &DefB = *DefI->getParent();
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    unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
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                          ? Hexagon::V6_vS32b_ai
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                          : 
Hexagon::PS_vstorerw_ai0
;
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    BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
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      .addFrameIndex(FI)
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      .addImm(0)
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      .addReg(VecR);
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    unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
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    for (MachineInstr *ExtI : P.second) {
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      assert(ExtI->getOpcode() == Hexagon::V6_extractw);
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      unsigned SR = ExtI->getOperand(1).getSubReg();
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      assert(ExtI->getOperand(1).getReg() == VecR);
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      MachineBasicBlock &ExtB = *ExtI->getParent();
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      DebugLoc DL = ExtI->getDebugLoc();
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      unsigned BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
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      BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::PS_fi), BaseR)
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        .addFrameIndex(FI)
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        .addImm(SR == 0 ? 0 : 
VecSize/20
);
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      unsigned ElemR = genElemLoad(ExtI, BaseR, MRI);
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      unsigned ExtR = ExtI->getOperand(0).getReg();
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      MRI.replaceRegWith(ExtR, ElemR);
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      ExtB.erase(ExtI);
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      Changed = true;
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    }
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  }
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  return Changed;
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}
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FunctionPass *llvm::createHexagonVExtract() {
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  return new HexagonVExtract();
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}