Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
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//===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include <vector>
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namespace llvm {
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class MachineBranchProbabilityInfo;
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class MachineFunction;
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class MachineInstr;
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class MachineLoopInfo;
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class TargetRegisterClass;
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class HexagonPacketizerList : public VLIWPacketizerList {
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  // Vector of instructions assigned to the packet that has just been created.
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  std::vector<MachineInstr *> OldPacketMIs;
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  // Has the instruction been promoted to a dot-new instruction.
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  bool PromotedToDotNew;
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  // Has the instruction been glued to allocframe.
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  bool GlueAllocframeStore;
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  // Has the feeder instruction been glued to new value jump.
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  bool GlueToNewValueJump;
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  // This holds the offset value, when pruning the dependences.
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  int64_t ChangedOffset;
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  // Check if there is a dependence between some instruction already in this
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  // packet and this instruction.
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  bool Dependence;
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  // Only check for dependence if there are resources available to
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  // schedule this instruction.
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  bool FoundSequentialDependence;
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  bool MemShufDisabled = false;
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  // Track MIs with ignored dependence.
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  std::vector<MachineInstr*> IgnoreDepMIs;
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  // Set to true if the packet contains an instruction that stalls with an
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  // instruction from the previous packet.
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  bool PacketStalls = false;
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protected:
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  /// A handle to the branch probability pass.
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  const MachineBranchProbabilityInfo *MBPI;
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  const MachineLoopInfo *MLI;
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private:
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  const HexagonInstrInfo *HII;
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  const HexagonRegisterInfo *HRI;
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  const bool Minimal;
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public:
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  HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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                        AliasAnalysis *AA,
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                        const MachineBranchProbabilityInfo *MBPI,
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                        bool Minimal);
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  // initPacketizerState - initialize some internal flags.
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  void initPacketizerState() override;
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  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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  bool ignorePseudoInstruction(const MachineInstr &MI,
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                               const MachineBasicBlock *MBB) override;
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  // isSoloInstruction - return true if instruction MI can not be packetized
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  // with any other instruction, which means that MI itself is a packet.
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  bool isSoloInstruction(const MachineInstr &MI) override;
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  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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  // together.
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  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
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  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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  // and SUJ.
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  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
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  bool foundLSInPacket();
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  MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
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  void endPacket(MachineBasicBlock *MBB,
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                 MachineBasicBlock::iterator MI) override;
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  bool shouldAddToPacket(const MachineInstr &MI) override;
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  void unpacketizeSoloInstrs(MachineFunction &MF);
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protected:
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  bool getmemShufDisabled() {
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    return MemShufDisabled;
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  };
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  void setmemShufDisabled(bool val) {
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    MemShufDisabled = val;
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  };
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  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
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                       unsigned DepReg);
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  bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
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                       MachineBasicBlock::iterator &MII,
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                       const TargetRegisterClass *RC);
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  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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                          unsigned DepReg, MachineBasicBlock::iterator &MII,
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                          const TargetRegisterClass *RC);
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  void cleanUpDotCur();
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  bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
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                       MachineBasicBlock::iterator &MII,
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                       const TargetRegisterClass *RC);
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  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
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                          unsigned DepReg, MachineBasicBlock::iterator &MII,
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                          const TargetRegisterClass *RC);
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  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
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                            unsigned DepReg, MachineBasicBlock::iterator &MII);
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  bool canPromoteToNewValueStore(const MachineInstr &MI,
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                                 const MachineInstr &PacketMI, unsigned DepReg);
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  bool demoteToDotOld(MachineInstr &MI);
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  bool useCallersSP(MachineInstr &MI);
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  void useCalleesSP(MachineInstr &MI);
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  bool updateOffset(SUnit *SUI, SUnit *SUJ);
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  void undoChangedOffset(MachineInstr &MI);
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  bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
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  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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  bool isCurifiable(MachineInstr &MI);
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  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
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  bool isPromotedToDotNew() const {
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    return PromotedToDotNew;
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  }
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  bool tryAllocateResourcesForConstExt(bool Reserve);
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  bool canReserveResourcesForConstExt();
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  void reserveResourcesForConstExt();
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  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
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  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
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  bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
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  bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
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  bool producesStall(const MachineInstr &MI);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H