Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
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//===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
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//===----------------------------------------------------------------------===//
8
9
#include "HexagonFixupKinds.h"
10
#include "MCTargetDesc/HexagonBaseInfo.h"
11
#include "MCTargetDesc/HexagonMCChecker.h"
12
#include "MCTargetDesc/HexagonMCCodeEmitter.h"
13
#include "MCTargetDesc/HexagonMCInstrInfo.h"
14
#include "MCTargetDesc/HexagonMCShuffler.h"
15
#include "MCTargetDesc/HexagonMCTargetDesc.h"
16
#include "llvm/MC/MCAsmBackend.h"
17
#include "llvm/MC/MCAsmLayout.h"
18
#include "llvm/MC/MCAssembler.h"
19
#include "llvm/MC/MCContext.h"
20
#include "llvm/MC/MCELFObjectWriter.h"
21
#include "llvm/MC/MCFixupKindInfo.h"
22
#include "llvm/MC/MCInstrInfo.h"
23
#include "llvm/MC/MCObjectWriter.h"
24
#include "llvm/Support/Debug.h"
25
#include "llvm/Support/TargetRegistry.h"
26
27
#include <sstream>
28
29
using namespace llvm;
30
using namespace Hexagon;
31
32
#define DEBUG_TYPE "hexagon-asm-backend"
33
34
static cl::opt<bool> DisableFixup
35
  ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
36
37
namespace {
38
39
class HexagonAsmBackend : public MCAsmBackend {
40
  uint8_t OSABI;
41
  StringRef CPU;
42
  mutable uint64_t relaxedCnt;
43
  std::unique_ptr <MCInstrInfo> MCII;
44
  std::unique_ptr <MCInst *> RelaxTarget;
45
  MCInst * Extender;
46
47
  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
48
24
                          MCInst &HMB) const {
49
24
    SmallVector<MCFixup, 4> Fixups;
50
24
    SmallString<256> Code;
51
24
    raw_svector_ostream VecOS(Code);
52
24
    E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo());
53
24
54
24
    // Update the fragment.
55
24
    RF.setInst(HMB);
56
24
    RF.getContents() = Code;
57
24
    RF.getFixups() = Fixups;
58
24
  }
59
60
public:
61
  HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
62
                    StringRef CPU)
63
      : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU),
64
        MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
65
1.05k
        Extender(nullptr) {}
66
67
  std::unique_ptr<MCObjectTargetWriter>
68
1.05k
  createObjectTargetWriter() const override {
69
1.05k
    return createHexagonELFObjectWriter(OSABI, CPU);
70
1.05k
  }
71
72
5
  void setExtender(MCContext &Context) const {
73
5
    if (Extender == nullptr)
74
5
      const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
75
5
  }
76
77
5
  MCInst *takeExtender() const {
78
5
    assert(Extender != nullptr);
79
5
    MCInst * Result = Extender;
80
5
    const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
81
5
    return Result;
82
5
  }
83
84
0
  unsigned getNumFixupKinds() const override {
85
0
    return Hexagon::NumTargetFixupKinds;
86
0
  }
87
88
1.84k
  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
89
1.84k
    const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
90
1.84k
      // This table *must* be in same the order of fixup_* kinds in
91
1.84k
      // HexagonFixupKinds.h.
92
1.84k
      //
93
1.84k
      // namei                          offset  bits    flags
94
1.84k
      { "fixup_Hexagon_B22_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
95
1.84k
      { "fixup_Hexagon_B15_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
96
1.84k
      { "fixup_Hexagon_B7_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
97
1.84k
      { "fixup_Hexagon_LO16",           0,      32,     0 },
98
1.84k
      { "fixup_Hexagon_HI16",           0,      32,     0 },
99
1.84k
      { "fixup_Hexagon_32",             0,      32,     0 },
100
1.84k
      { "fixup_Hexagon_16",             0,      32,     0 },
101
1.84k
      { "fixup_Hexagon_8",              0,      32,     0 },
102
1.84k
      { "fixup_Hexagon_GPREL16_0",      0,      32,     0 },
103
1.84k
      { "fixup_Hexagon_GPREL16_1",      0,      32,     0 },
104
1.84k
      { "fixup_Hexagon_GPREL16_2",      0,      32,     0 },
105
1.84k
      { "fixup_Hexagon_GPREL16_3",      0,      32,     0 },
106
1.84k
      { "fixup_Hexagon_HL16",           0,      32,     0 },
107
1.84k
      { "fixup_Hexagon_B13_PCREL",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
108
1.84k
      { "fixup_Hexagon_B9_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
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1.84k
      { "fixup_Hexagon_B32_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
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1.84k
      { "fixup_Hexagon_32_6_X",         0,      32,     0 },
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1.84k
      { "fixup_Hexagon_B22_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
112
1.84k
      { "fixup_Hexagon_B15_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
113
1.84k
      { "fixup_Hexagon_B13_PCREL_X",    0,      32,     MCFixupKindInfo::FKF_IsPCRel },
114
1.84k
      { "fixup_Hexagon_B9_PCREL_X",     0,      32,     MCFixupKindInfo::FKF_IsPCRel },
115
1.84k
      { "fixup_Hexagon_B7_PCREL_X",     0,      32,     MCFixupKindInfo::FKF_IsPCRel },
116
1.84k
      { "fixup_Hexagon_16_X",           0,      32,     0 },
117
1.84k
      { "fixup_Hexagon_12_X",           0,      32,     0 },
118
1.84k
      { "fixup_Hexagon_11_X",           0,      32,     0 },
119
1.84k
      { "fixup_Hexagon_10_X",           0,      32,     0 },
120
1.84k
      { "fixup_Hexagon_9_X",            0,      32,     0 },
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1.84k
      { "fixup_Hexagon_8_X",            0,      32,     0 },
122
1.84k
      { "fixup_Hexagon_7_X",            0,      32,     0 },
123
1.84k
      { "fixup_Hexagon_6_X",            0,      32,     0 },
124
1.84k
      { "fixup_Hexagon_32_PCREL",       0,      32,     MCFixupKindInfo::FKF_IsPCRel },
125
1.84k
      { "fixup_Hexagon_COPY",           0,      32,     0 },
126
1.84k
      { "fixup_Hexagon_GLOB_DAT",       0,      32,     0 },
127
1.84k
      { "fixup_Hexagon_JMP_SLOT",       0,      32,     0 },
128
1.84k
      { "fixup_Hexagon_RELATIVE",       0,      32,     0 },
129
1.84k
      { "fixup_Hexagon_PLT_B22_PCREL",  0,      32,     MCFixupKindInfo::FKF_IsPCRel },
130
1.84k
      { "fixup_Hexagon_GOTREL_LO16",    0,      32,     0 },
131
1.84k
      { "fixup_Hexagon_GOTREL_HI16",    0,      32,     0 },
132
1.84k
      { "fixup_Hexagon_GOTREL_32",      0,      32,     0 },
133
1.84k
      { "fixup_Hexagon_GOT_LO16",       0,      32,     0 },
134
1.84k
      { "fixup_Hexagon_GOT_HI16",       0,      32,     0 },
135
1.84k
      { "fixup_Hexagon_GOT_32",         0,      32,     0 },
136
1.84k
      { "fixup_Hexagon_GOT_16",         0,      32,     0 },
137
1.84k
      { "fixup_Hexagon_DTPMOD_32",      0,      32,     0 },
138
1.84k
      { "fixup_Hexagon_DTPREL_LO16",    0,      32,     0 },
139
1.84k
      { "fixup_Hexagon_DTPREL_HI16",    0,      32,     0 },
140
1.84k
      { "fixup_Hexagon_DTPREL_32",      0,      32,     0 },
141
1.84k
      { "fixup_Hexagon_DTPREL_16",      0,      32,     0 },
142
1.84k
      { "fixup_Hexagon_GD_PLT_B22_PCREL",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
143
1.84k
      { "fixup_Hexagon_LD_PLT_B22_PCREL",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
144
1.84k
      { "fixup_Hexagon_GD_GOT_LO16",    0,      32,     0 },
145
1.84k
      { "fixup_Hexagon_GD_GOT_HI16",    0,      32,     0 },
146
1.84k
      { "fixup_Hexagon_GD_GOT_32",      0,      32,     0 },
147
1.84k
      { "fixup_Hexagon_GD_GOT_16",      0,      32,     0 },
148
1.84k
      { "fixup_Hexagon_LD_GOT_LO16",    0,      32,     0 },
149
1.84k
      { "fixup_Hexagon_LD_GOT_HI16",    0,      32,     0 },
150
1.84k
      { "fixup_Hexagon_LD_GOT_32",      0,      32,     0 },
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1.84k
      { "fixup_Hexagon_LD_GOT_16",      0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_LO16",        0,      32,     0 },
153
1.84k
      { "fixup_Hexagon_IE_HI16",        0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_32",          0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_16",          0,      32,     0 },
156
1.84k
      { "fixup_Hexagon_IE_GOT_LO16",    0,      32,     0 },
157
1.84k
      { "fixup_Hexagon_IE_GOT_HI16",    0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_GOT_32",      0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_GOT_16",      0,      32,     0 },
160
1.84k
      { "fixup_Hexagon_TPREL_LO16",     0,      32,     0 },
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1.84k
      { "fixup_Hexagon_TPREL_HI16",     0,      32,     0 },
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1.84k
      { "fixup_Hexagon_TPREL_32",       0,      32,     0 },
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1.84k
      { "fixup_Hexagon_TPREL_16",       0,      32,     0 },
164
1.84k
      { "fixup_Hexagon_6_PCREL_X",      0,      32,     MCFixupKindInfo::FKF_IsPCRel },
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1.84k
      { "fixup_Hexagon_GOTREL_32_6_X",  0,      32,     0 },
166
1.84k
      { "fixup_Hexagon_GOTREL_16_X",    0,      32,     0 },
167
1.84k
      { "fixup_Hexagon_GOTREL_11_X",    0,      32,     0 },
168
1.84k
      { "fixup_Hexagon_GOT_32_6_X",     0,      32,     0 },
169
1.84k
      { "fixup_Hexagon_GOT_16_X",       0,      32,     0 },
170
1.84k
      { "fixup_Hexagon_GOT_11_X",       0,      32,     0 },
171
1.84k
      { "fixup_Hexagon_DTPREL_32_6_X",  0,      32,     0 },
172
1.84k
      { "fixup_Hexagon_DTPREL_16_X",    0,      32,     0 },
173
1.84k
      { "fixup_Hexagon_DTPREL_11_X",    0,      32,     0 },
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1.84k
      { "fixup_Hexagon_GD_GOT_32_6_X",  0,      32,     0 },
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1.84k
      { "fixup_Hexagon_GD_GOT_16_X",    0,      32,     0 },
176
1.84k
      { "fixup_Hexagon_GD_GOT_11_X",    0,      32,     0 },
177
1.84k
      { "fixup_Hexagon_LD_GOT_32_6_X",  0,      32,     0 },
178
1.84k
      { "fixup_Hexagon_LD_GOT_16_X",    0,      32,     0 },
179
1.84k
      { "fixup_Hexagon_LD_GOT_11_X",    0,      32,     0 },
180
1.84k
      { "fixup_Hexagon_IE_32_6_X",      0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_16_X",        0,      32,     0 },
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1.84k
      { "fixup_Hexagon_IE_GOT_32_6_X",  0,      32,     0 },
183
1.84k
      { "fixup_Hexagon_IE_GOT_16_X",    0,      32,     0 },
184
1.84k
      { "fixup_Hexagon_IE_GOT_11_X",    0,      32,     0 },
185
1.84k
      { "fixup_Hexagon_TPREL_32_6_X",   0,      32,     0 },
186
1.84k
      { "fixup_Hexagon_TPREL_16_X",     0,      32,     0 },
187
1.84k
      { "fixup_Hexagon_TPREL_11_X",     0,      32,     0 },
188
1.84k
      { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
189
1.84k
      { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
190
1.84k
      { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel },
191
1.84k
      { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0,     32,     MCFixupKindInfo::FKF_IsPCRel }
192
1.84k
    };
193
1.84k
194
1.84k
    if (Kind < FirstTargetFixupKind)
195
534
      return MCAsmBackend::getFixupKindInfo(Kind);
196
1.30k
197
1.30k
    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
198
1.30k
           "Invalid kind!");
199
1.30k
    return Infos[Kind - FirstTargetFixupKind];
200
1.30k
  }
201
202
  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
203
184
                             const MCValue &Target) override {
204
184
    MCFixupKind Kind = Fixup.getKind();
205
184
206
184
    switch((unsigned)Kind) {
207
184
      default:
208
0
        llvm_unreachable("Unknown Fixup Kind!");
209
184
210
184
      case fixup_Hexagon_LO16:
211
2
      case fixup_Hexagon_HI16:
212
2
      case fixup_Hexagon_16:
213
2
      case fixup_Hexagon_8:
214
2
      case fixup_Hexagon_GPREL16_0:
215
2
      case fixup_Hexagon_GPREL16_1:
216
2
      case fixup_Hexagon_GPREL16_2:
217
2
      case fixup_Hexagon_GPREL16_3:
218
2
      case fixup_Hexagon_HL16:
219
2
      case fixup_Hexagon_32_6_X:
220
2
      case fixup_Hexagon_16_X:
221
2
      case fixup_Hexagon_12_X:
222
2
      case fixup_Hexagon_11_X:
223
2
      case fixup_Hexagon_10_X:
224
2
      case fixup_Hexagon_9_X:
225
2
      case fixup_Hexagon_8_X:
226
2
      case fixup_Hexagon_7_X:
227
2
      case fixup_Hexagon_6_X:
228
2
      case fixup_Hexagon_COPY:
229
2
      case fixup_Hexagon_GLOB_DAT:
230
2
      case fixup_Hexagon_JMP_SLOT:
231
2
      case fixup_Hexagon_RELATIVE:
232
2
      case fixup_Hexagon_PLT_B22_PCREL:
233
2
      case fixup_Hexagon_GOTREL_LO16:
234
2
      case fixup_Hexagon_GOTREL_HI16:
235
2
      case fixup_Hexagon_GOTREL_32:
236
2
      case fixup_Hexagon_GOT_LO16:
237
2
      case fixup_Hexagon_GOT_HI16:
238
2
      case fixup_Hexagon_GOT_32:
239
2
      case fixup_Hexagon_GOT_16:
240
2
      case fixup_Hexagon_DTPMOD_32:
241
2
      case fixup_Hexagon_DTPREL_LO16:
242
2
      case fixup_Hexagon_DTPREL_HI16:
243
2
      case fixup_Hexagon_DTPREL_32:
244
2
      case fixup_Hexagon_DTPREL_16:
245
2
      case fixup_Hexagon_GD_PLT_B22_PCREL:
246
2
      case fixup_Hexagon_LD_PLT_B22_PCREL:
247
2
      case fixup_Hexagon_GD_GOT_LO16:
248
2
      case fixup_Hexagon_GD_GOT_HI16:
249
2
      case fixup_Hexagon_GD_GOT_32:
250
2
      case fixup_Hexagon_GD_GOT_16:
251
2
      case fixup_Hexagon_LD_GOT_LO16:
252
2
      case fixup_Hexagon_LD_GOT_HI16:
253
2
      case fixup_Hexagon_LD_GOT_32:
254
2
      case fixup_Hexagon_LD_GOT_16:
255
2
      case fixup_Hexagon_IE_LO16:
256
2
      case fixup_Hexagon_IE_HI16:
257
2
      case fixup_Hexagon_IE_32:
258
2
      case fixup_Hexagon_IE_16:
259
2
      case fixup_Hexagon_IE_GOT_LO16:
260
2
      case fixup_Hexagon_IE_GOT_HI16:
261
2
      case fixup_Hexagon_IE_GOT_32:
262
2
      case fixup_Hexagon_IE_GOT_16:
263
2
      case fixup_Hexagon_TPREL_LO16:
264
2
      case fixup_Hexagon_TPREL_HI16:
265
2
      case fixup_Hexagon_TPREL_32:
266
2
      case fixup_Hexagon_TPREL_16:
267
2
      case fixup_Hexagon_GOTREL_32_6_X:
268
2
      case fixup_Hexagon_GOTREL_16_X:
269
2
      case fixup_Hexagon_GOTREL_11_X:
270
2
      case fixup_Hexagon_GOT_32_6_X:
271
2
      case fixup_Hexagon_GOT_16_X:
272
2
      case fixup_Hexagon_GOT_11_X:
273
2
      case fixup_Hexagon_DTPREL_32_6_X:
274
2
      case fixup_Hexagon_DTPREL_16_X:
275
2
      case fixup_Hexagon_DTPREL_11_X:
276
2
      case fixup_Hexagon_GD_GOT_32_6_X:
277
2
      case fixup_Hexagon_GD_GOT_16_X:
278
2
      case fixup_Hexagon_GD_GOT_11_X:
279
2
      case fixup_Hexagon_LD_GOT_32_6_X:
280
2
      case fixup_Hexagon_LD_GOT_16_X:
281
2
      case fixup_Hexagon_LD_GOT_11_X:
282
2
      case fixup_Hexagon_IE_32_6_X:
283
2
      case fixup_Hexagon_IE_16_X:
284
2
      case fixup_Hexagon_IE_GOT_32_6_X:
285
2
      case fixup_Hexagon_IE_GOT_16_X:
286
2
      case fixup_Hexagon_IE_GOT_11_X:
287
2
      case fixup_Hexagon_TPREL_32_6_X:
288
2
      case fixup_Hexagon_TPREL_16_X:
289
2
      case fixup_Hexagon_TPREL_11_X:
290
2
      case fixup_Hexagon_32_PCREL:
291
2
      case fixup_Hexagon_6_PCREL_X:
292
2
      case fixup_Hexagon_23_REG:
293
2
      case fixup_Hexagon_27_REG:
294
2
      case fixup_Hexagon_GD_PLT_B22_PCREL_X:
295
2
      case fixup_Hexagon_GD_PLT_B32_PCREL_X:
296
2
      case fixup_Hexagon_LD_PLT_B22_PCREL_X:
297
2
      case fixup_Hexagon_LD_PLT_B32_PCREL_X:
298
2
        // These relocations should always have a relocation recorded
299
2
        return true;
300
2
301
3
      case fixup_Hexagon_B22_PCREL:
302
3
        //IsResolved = false;
303
3
        break;
304
2
305
26
      case fixup_Hexagon_B13_PCREL:
306
26
      case fixup_Hexagon_B13_PCREL_X:
307
26
      case fixup_Hexagon_B32_PCREL_X:
308
26
      case fixup_Hexagon_B22_PCREL_X:
309
26
      case fixup_Hexagon_B15_PCREL:
310
26
      case fixup_Hexagon_B15_PCREL_X:
311
26
      case fixup_Hexagon_B9_PCREL:
312
26
      case fixup_Hexagon_B9_PCREL_X:
313
26
      case fixup_Hexagon_B7_PCREL:
314
26
      case fixup_Hexagon_B7_PCREL_X:
315
26
        if (DisableFixup)
316
0
          return true;
317
26
        break;
318
26
319
153
      case FK_Data_1:
320
153
      case FK_Data_2:
321
153
      case FK_Data_4:
322
153
      case FK_PCRel_4:
323
153
      case fixup_Hexagon_32:
324
153
        // Leave these relocations alone as they are used for EH.
325
153
        return false;
326
29
    }
327
29
    return false;
328
29
  }
329
330
  /// getFixupKindNumBytes - The number of bytes the fixup may change.
331
161
  static unsigned getFixupKindNumBytes(unsigned Kind) {
332
161
    switch (Kind) {
333
161
    default:
334
0
        return 0;
335
161
336
161
      case FK_Data_1:
337
0
        return 1;
338
161
      case FK_Data_2:
339
0
        return 2;
340
161
      case FK_Data_4:         // this later gets mapped to R_HEX_32
341
161
      case FK_PCRel_4:        // this later gets mapped to R_HEX_32_PCREL
342
161
      case fixup_Hexagon_32:
343
161
      case fixup_Hexagon_B32_PCREL_X:
344
161
      case fixup_Hexagon_B22_PCREL:
345
161
      case fixup_Hexagon_B22_PCREL_X:
346
161
      case fixup_Hexagon_B15_PCREL:
347
161
      case fixup_Hexagon_B15_PCREL_X:
348
161
      case fixup_Hexagon_B13_PCREL:
349
161
      case fixup_Hexagon_B13_PCREL_X:
350
161
      case fixup_Hexagon_B9_PCREL:
351
161
      case fixup_Hexagon_B9_PCREL_X:
352
161
      case fixup_Hexagon_B7_PCREL:
353
161
      case fixup_Hexagon_B7_PCREL_X:
354
161
      case fixup_Hexagon_GD_PLT_B32_PCREL_X:
355
161
      case fixup_Hexagon_LD_PLT_B32_PCREL_X:
356
161
        return 4;
357
161
    }
358
161
  }
359
360
  // Make up for left shift when encoding the operand.
361
161
  static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
362
161
    switch((unsigned)Kind) {
363
161
      default:
364
153
        break;
365
161
366
161
      case fixup_Hexagon_B7_PCREL:
367
4
      case fixup_Hexagon_B9_PCREL:
368
4
      case fixup_Hexagon_B13_PCREL:
369
4
      case fixup_Hexagon_B15_PCREL:
370
4
      case fixup_Hexagon_B22_PCREL:
371
4
        Value >>= 2;
372
4
        break;
373
4
374
4
      case fixup_Hexagon_B7_PCREL_X:
375
2
      case fixup_Hexagon_B9_PCREL_X:
376
2
      case fixup_Hexagon_B13_PCREL_X:
377
2
      case fixup_Hexagon_B15_PCREL_X:
378
2
      case fixup_Hexagon_B22_PCREL_X:
379
2
        Value &= 0x3f;
380
2
        break;
381
2
382
2
      case fixup_Hexagon_B32_PCREL_X:
383
2
      case fixup_Hexagon_GD_PLT_B32_PCREL_X:
384
2
      case fixup_Hexagon_LD_PLT_B32_PCREL_X:
385
2
        Value >>= 6;
386
2
        break;
387
161
    }
388
161
    return (Value);
389
161
  }
390
391
  void HandleFixupError(const int bits, const int align_bits,
392
0
    const int64_t FixupValue, const char *fixupStr) const {
393
0
    // Error: value 1124 out of range: -1024-1023 when resolving
394
0
    // symbol in file xprtsock.S
395
0
    const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
396
0
    const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
397
0
    std::stringstream errStr;
398
0
    errStr << "\nError: value " <<
399
0
      FixupValue <<
400
0
      " out of range: " <<
401
0
      IntMin.getSExtValue() <<
402
0
      "-" <<
403
0
      IntMax.getSExtValue() <<
404
0
      " when resolving " <<
405
0
      fixupStr <<
406
0
      " fixup\n";
407
0
    llvm_unreachable(errStr.str().c_str());
408
0
  }
409
410
  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
411
  /// data fragment, at the offset specified by the fixup and following the
412
  /// fixup kind as appropriate.
413
  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
414
                  const MCValue &Target, MutableArrayRef<char> Data,
415
                  uint64_t FixupValue, bool IsResolved,
416
481
                  const MCSubtargetInfo *STI) const override {
417
481
418
481
    // When FixupValue is 0 the relocation is external and there
419
481
    // is nothing for us to do.
420
481
    if (!FixupValue) 
return320
;
421
161
422
161
    MCFixupKind Kind = Fixup.getKind();
423
161
    uint64_t Value;
424
161
    uint32_t InstMask;
425
161
    uint32_t Reloc;
426
161
427
161
    // LLVM gives us an encoded value, we have to convert it back
428
161
    // to a real offset before we can use it.
429
161
    uint32_t Offset = Fixup.getOffset();
430
161
    unsigned NumBytes = getFixupKindNumBytes(Kind);
431
161
    assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
432
161
    char *InstAddr = Data.data() + Offset;
433
161
434
161
    Value = adjustFixupValue(Kind, FixupValue);
435
161
    if(!Value)
436
0
      return;
437
161
    int sValue = (int)Value;
438
161
439
161
    switch((unsigned)Kind) {
440
161
      default:
441
0
        return;
442
161
443
161
      case fixup_Hexagon_B7_PCREL:
444
0
        if (!(isIntN(7, sValue)))
445
0
          HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
446
0
        LLVM_FALLTHROUGH;
447
0
      case fixup_Hexagon_B7_PCREL_X:
448
0
        InstMask = 0x00001f18;  // Word32_B7
449
0
        Reloc = (((Value >> 2) & 0x1f) << 8) |    // Value 6-2 = Target 12-8
450
0
                ((Value & 0x3) << 3);             // Value 1-0 = Target 4-3
451
0
        break;
452
0
453
2
      case fixup_Hexagon_B9_PCREL:
454
2
        if (!(isIntN(9, sValue)))
455
0
          HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
456
2
        LLVM_FALLTHROUGH;
457
4
      case fixup_Hexagon_B9_PCREL_X:
458
4
        InstMask = 0x003000fe;  // Word32_B9
459
4
        Reloc = (((Value >> 7) & 0x3) << 20) |    // Value 8-7 = Target 21-20
460
4
                ((Value & 0x7f) << 1);            // Value 6-0 = Target 7-1
461
4
        break;
462
2
463
2
        // Since the existing branches that use this relocation cannot be
464
2
        // extended, they should only be fixed up if the target is within range.
465
2
      case fixup_Hexagon_B13_PCREL:
466
0
        if (!(isIntN(13, sValue)))
467
0
          HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
468
0
        LLVM_FALLTHROUGH;
469
0
      case fixup_Hexagon_B13_PCREL_X:
470
0
        InstMask = 0x00202ffe;  // Word32_B13
471
0
        Reloc = (((Value >> 12) & 0x1) << 21) |    // Value 12   = Target 21
472
0
                (((Value >> 11) & 0x1) << 13) |    // Value 11   = Target 13
473
0
                ((Value & 0x7ff) << 1);            // Value 10-0 = Target 11-1
474
0
        break;
475
0
476
1
      case fixup_Hexagon_B15_PCREL:
477
1
        if (!(isIntN(15, sValue)))
478
0
          HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
479
1
        LLVM_FALLTHROUGH;
480
1
      case fixup_Hexagon_B15_PCREL_X:
481
1
        InstMask = 0x00df20fe;  // Word32_B15
482
1
        Reloc = (((Value >> 13) & 0x3) << 22) |    // Value 14-13 = Target 23-22
483
1
                (((Value >> 8) & 0x1f) << 16) |    // Value 12-8  = Target 20-16
484
1
                (((Value >> 7) & 0x1)  << 13) |    // Value 7     = Target 13
485
1
                ((Value & 0x7f) << 1);             // Value 6-0   = Target 7-1
486
1
        break;
487
1
488
1
      case fixup_Hexagon_B22_PCREL:
489
1
        if (!(isIntN(22, sValue)))
490
0
          HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
491
1
        LLVM_FALLTHROUGH;
492
1
      case fixup_Hexagon_B22_PCREL_X:
493
1
        InstMask = 0x01ff3ffe;  // Word32_B22
494
1
        Reloc = (((Value >> 13) & 0x1ff) << 16) |  // Value 21-13 = Target 24-16
495
1
                ((Value & 0x1fff) << 1);           // Value 12-0  = Target 13-1
496
1
        break;
497
1
498
2
      case fixup_Hexagon_B32_PCREL_X:
499
2
        InstMask = 0x0fff3fff;  // Word32_X26
500
2
        Reloc = (((Value >> 14) & 0xfff) << 16) |  // Value 25-14 = Target 27-16
501
2
                (Value & 0x3fff);                  // Value 13-0  = Target 13-0
502
2
        break;
503
1
504
153
      case FK_Data_1:
505
153
      case FK_Data_2:
506
153
      case FK_Data_4:
507
153
      case fixup_Hexagon_32:
508
153
        InstMask = 0xffffffff;  // Word32
509
153
        Reloc = Value;
510
153
        break;
511
161
    }
512
161
513
161
    LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
514
161
                      << (unsigned)Kind << ")\n");
515
161
    LLVM_DEBUG(
516
161
        uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
517
161
                              (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
518
161
        dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
519
161
        dbgs().write_hex(FixupValue)
520
161
        << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
521
161
        dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
522
161
523
161
    // For each byte of the fragment that the fixup touches, mask in the
524
161
    // bits from the fixup value. The Value has been "split up" into the
525
161
    // appropriate bitfields above.
526
805
    for (unsigned i = 0; i < NumBytes; 
i++644
){
527
644
      InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
528
644
      InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff;     // Apply new reloc
529
644
    }
530
161
531
161
    LLVM_DEBUG(uint32_t NewData = 0;
532
161
               for (unsigned i = 0; i < NumBytes; i++) NewData |=
533
161
               (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
534
161
               dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
535
161
  }
536
537
279
  bool isInstRelaxable(MCInst const &HMI) const {
538
279
    const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
539
279
    bool Relaxable = false;
540
279
    // Branches and loop-setup insns are handled as necessary by relaxation.
541
279
    if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
542
279
        
(237
llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ237
&&
543
237
         
MCID.isBranch()4
) ||
544
279
        
(233
llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ233
&&
545
233
         
MCID.isBranch()10
) ||
546
279
        
(223
llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR223
&&
547
223
         
HMI.getOpcode() != Hexagon::C4_addipc11
))
548
60
      if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
549
58
        Relaxable = true;
550
58
        MCOperand const &Operand =
551
58
            HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI));
552
58
        if (HexagonMCInstrInfo::mustNotExtend(*Operand.getExpr()))
553
7
          Relaxable = false;
554
58
      }
555
279
556
279
    return Relaxable;
557
279
  }
558
559
  /// MayNeedRelaxation - Check whether the given instruction may need
560
  /// relaxation.
561
  ///
562
  /// \param Inst - The instruction to test.
563
  bool mayNeedRelaxation(MCInst const &Inst,
564
5.32k
                         const MCSubtargetInfo &STI) const override {
565
5.32k
    return true;
566
5.32k
  }
567
568
  /// fixupNeedsRelaxation - Target specific predicate for whether a given
569
  /// fixup requires the associated instruction to be relaxed.
570
  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
571
                                    uint64_t Value,
572
                                    const MCRelaxableFragment *DF,
573
                                    const MCAsmLayout &Layout,
574
279
                                    const bool WasForced) const override {
575
279
    MCInst const &MCB = DF->getInst();
576
279
    assert(HexagonMCInstrInfo::isBundle(MCB));
577
279
578
279
    *RelaxTarget = nullptr;
579
279
    MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
580
279
        MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
581
279
    bool Relaxable = isInstRelaxable(MCI);
582
279
    if (Relaxable == false)
583
228
      return false;
584
51
    // If we cannot resolve the fixup value, it requires relaxation.
585
51
    if (!Resolved) {
586
37
      switch ((unsigned)Fixup.getKind()) {
587
37
      case fixup_Hexagon_B22_PCREL:
588
8
        // GetFixupCount assumes B22 won't relax
589
8
        LLVM_FALLTHROUGH;
590
32
      default:
591
32
        return false;
592
8
        
break0
;
593
8
      case fixup_Hexagon_B13_PCREL:
594
5
      case fixup_Hexagon_B15_PCREL:
595
5
      case fixup_Hexagon_B9_PCREL:
596
5
      case fixup_Hexagon_B7_PCREL: {
597
5
        if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
598
4
          ++relaxedCnt;
599
4
          *RelaxTarget = &MCI;
600
4
          setExtender(Layout.getAssembler().getContext());
601
4
          return true;
602
4
        } else {
603
1
          return false;
604
1
        }
605
0
        break;
606
0
      }
607
37
      }
608
37
    }
609
14
610
14
    MCFixupKind Kind = Fixup.getKind();
611
14
    int64_t sValue = Value;
612
14
    int64_t maxValue;
613
14
614
14
    switch ((unsigned)Kind) {
615
14
    case fixup_Hexagon_B7_PCREL:
616
0
      maxValue = 1 << 8;
617
0
      break;
618
14
    case fixup_Hexagon_B9_PCREL:
619
6
      maxValue = 1 << 10;
620
6
      break;
621
14
    case fixup_Hexagon_B15_PCREL:
622
2
      maxValue = 1 << 16;
623
2
      break;
624
14
    case fixup_Hexagon_B22_PCREL:
625
2
      maxValue = 1 << 23;
626
2
      break;
627
14
    default:
628
4
      maxValue = INT64_MAX;
629
4
      break;
630
14
    }
631
14
632
14
    bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
633
14
634
14
    if (isFarAway) {
635
1
      if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
636
1
        ++relaxedCnt;
637
1
        *RelaxTarget = &MCI;
638
1
        setExtender(Layout.getAssembler().getContext());
639
1
        return true;
640
1
      }
641
13
    }
642
13
643
13
    return false;
644
13
  }
645
646
  /// Simple predicate for targets where !Resolved implies requiring relaxation
647
  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
648
                            const MCRelaxableFragment *DF,
649
0
                            const MCAsmLayout &Layout) const override {
650
0
    llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
651
0
  }
652
653
  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
654
5
                        MCInst &Res) const override {
655
5
    assert(HexagonMCInstrInfo::isBundle(Inst) &&
656
5
           "Hexagon relaxInstruction only works on bundles");
657
5
658
5
    Res.setOpcode(Hexagon::BUNDLE);
659
5
    Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm()));
660
5
    // Copy the results into the bundle.
661
5
    bool Update = false;
662
10
    for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
663
10
      MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
664
10
665
10
      // if immediate extender needed, add it in
666
10
      if (*RelaxTarget == &CrntHMI) {
667
5
        Update = true;
668
5
        assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) &&
669
5
               "No room to insert extender for relaxation");
670
5
671
5
        MCInst *HMIx = takeExtender();
672
5
        *HMIx = HexagonMCInstrInfo::deriveExtender(
673
5
                *MCII, CrntHMI,
674
5
                HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI));
675
5
        Res.addOperand(MCOperand::createInst(HMIx));
676
5
        *RelaxTarget = nullptr;
677
5
      }
678
10
      // now copy over the original instruction(the one we may have extended)
679
10
      Res.addOperand(MCOperand::createInst(I.getInst()));
680
10
    }
681
5
    (void)Update;
682
5
    assert(Update && "Didn't find relaxation target");
683
5
  }
684
685
210
  bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
686
210
    static const uint32_t Nopcode  = 0x7f000000, // Hard-coded NOP.
687
210
                          ParseIn  = 0x00004000, // In packet parse-bits.
688
210
                          ParseEnd = 0x0000c000; // End of packet parse-bits.
689
210
690
210
    while(Count % HEXAGON_INSTR_SIZE) {
691
0
      LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
692
0
                        << Count % HEXAGON_INSTR_SIZE << "/"
693
0
                        << HEXAGON_INSTR_SIZE << "\n");
694
0
      --Count;
695
0
      OS << '\0';
696
0
    }
697
210
698
230
    while(Count) {
699
20
      Count -= HEXAGON_INSTR_SIZE;
700
20
      // Close the packet whenever a multiple of the maximum packet size remains
701
20
      uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
702
13
                           ParseIn: 
ParseEnd7
;
703
20
      support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
704
20
    }
705
210
    return true;
706
210
  }
707
708
  void finishLayout(MCAssembler const &Asm,
709
126
                    MCAsmLayout &Layout) const override {
710
213
    for (auto I : Layout.getSectionOrder()) {
711
213
      auto &Fragments = I->getFragmentList();
712
3.31k
      for (auto &J : Fragments) {
713
3.31k
        switch (J.getKind()) {
714
3.31k
        default:
715
3.03k
          break;
716
3.31k
        case MCFragment::FT_Align: {
717
286
          auto Size = Asm.computeFragmentSize(Layout, J);
718
286
          for (auto K = J.getIterator();
719
310
               K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
720
24
            --K;
721
24
            switch (K->getKind()) {
722
24
            default:
723
0
              break;
724
24
            case MCFragment::FT_Align: {
725
0
              // Don't pad before other alignments
726
0
              Size = 0;
727
0
              break;
728
24
            }
729
24
            case MCFragment::FT_Relaxable: {
730
24
              MCContext &Context = Asm.getContext();
731
24
              auto &RF = cast<MCRelaxableFragment>(*K);
732
24
              auto &Inst = const_cast<MCInst &>(RF.getInst());
733
70
              while (Size > 0 && 
HexagonMCInstrInfo::bundleSize(Inst) < 449
) {
734
46
                MCInst *Nop = new (Context) MCInst;
735
46
                Nop->setOpcode(Hexagon::A2_nop);
736
46
                Inst.addOperand(MCOperand::createInst(Nop));
737
46
                Size -= 4;
738
46
                if (!HexagonMCChecker(
739
46
                         Context, *MCII, *RF.getSubtargetInfo(), Inst,
740
46
                         *Context.getRegisterInfo(), false)
741
46
                         .check()) {
742
1
                  Inst.erase(Inst.end() - 1);
743
1
                  Size = 0;
744
1
                }
745
46
              }
746
24
              bool Error = HexagonMCShuffle(Context, true, *MCII,
747
24
                                            *RF.getSubtargetInfo(), Inst);
748
24
              //assert(!Error);
749
24
              (void)Error;
750
24
              ReplaceInstruction(Asm.getEmitter(), RF, Inst);
751
24
              Layout.invalidateFragmentsFrom(&RF);
752
24
              Size = 0; // Only look back one instruction
753
24
              break;
754
24
            }
755
24
            }
756
24
          }
757
286
        }
758
3.31k
        }
759
3.31k
      }
760
213
    }
761
126
  }
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}; // class HexagonAsmBackend
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} // namespace
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// MCAsmBackend
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MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
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                                            const MCSubtargetInfo &STI,
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                                            MCRegisterInfo const & /*MRI*/,
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1.05k
                                            const MCTargetOptions &Options) {
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  const Triple &TT = STI.getTargetTriple();
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  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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  StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
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  return new HexagonAsmBackend(T, TT, OSABI, CPUString);
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}