Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
Line
Count
Source (jump to first uncovered line)
1
//===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements the checking of insns inside a bundle according to the
10
// packet constraint rules of the Hexagon ISA.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "MCTargetDesc/HexagonMCChecker.h"
15
#include "MCTargetDesc/HexagonBaseInfo.h"
16
#include "MCTargetDesc/HexagonMCInstrInfo.h"
17
#include "MCTargetDesc/HexagonMCShuffler.h"
18
#include "MCTargetDesc/HexagonMCTargetDesc.h"
19
#include "llvm/ADT/Twine.h"
20
#include "llvm/MC/MCContext.h"
21
#include "llvm/MC/MCInst.h"
22
#include "llvm/MC/MCInstrDesc.h"
23
#include "llvm/MC/MCRegisterInfo.h"
24
#include "llvm/Support/CommandLine.h"
25
#include "llvm/Support/SourceMgr.h"
26
#include <cassert>
27
28
using namespace llvm;
29
30
static cl::opt<bool>
31
    RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore,
32
                  cl::Hidden, cl::desc("Relax checks of new-value validity"));
33
34
const HexagonMCChecker::PredSense
35
    HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
36
37
6.52k
void HexagonMCChecker::init() {
38
6.52k
  // Initialize read-only registers set.
39
6.52k
  ReadOnly.insert(Hexagon::PC);
40
6.52k
  ReadOnly.insert(Hexagon::C9_8);
41
6.52k
42
6.52k
  // Figure out the loop-registers definitions.
43
6.52k
  if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
44
22
    Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45
22
    Defs[Hexagon::LC0].insert(Unconditional);
46
22
  }
47
6.52k
  if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
48
19
    Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49
19
    Defs[Hexagon::LC1].insert(Unconditional);
50
19
  }
51
6.52k
52
6.52k
  if (HexagonMCInstrInfo::isBundle(MCB))
53
6.52k
    // Unfurl a bundle.
54
8.67k
    
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB))6.52k
{
55
8.67k
      MCInst const &Inst = *I.getInst();
56
8.67k
      if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
57
32
        init(*Inst.getOperand(0).getInst());
58
32
        init(*Inst.getOperand(1).getInst());
59
32
      } else
60
8.64k
        init(Inst);
61
8.67k
    }
62
0
  else
63
0
    init(MCB);
64
6.52k
}
65
66
void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
67
14.7k
                               bool &isTrue) {
68
14.7k
  if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && 
isPredicateRegister(R)3.91k
) {
69
1.51k
    // Note an used predicate register.
70
1.51k
    PredReg = R;
71
1.51k
    isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
72
1.51k
73
1.51k
    // Note use of new predicate register.
74
1.51k
    if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
75
769
      NewPreds.insert(PredReg);
76
1.51k
  } else
77
13.2k
    // Note register use.  Super-registers are not tracked directly,
78
13.2k
    // but their components.
79
13.2k
    for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
80
41.9k
         SRI.isValid(); 
++SRI28.6k
)
81
28.6k
      if (!MCSubRegIterator(*SRI, &RI).isValid())
82
16.3k
        // Skip super-registers used indirectly.
83
16.3k
        Uses.insert(*SRI);
84
14.7k
}
85
86
8.70k
void HexagonMCChecker::init(MCInst const &MCI) {
87
8.70k
  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
88
8.70k
  unsigned PredReg = Hexagon::NoRegister;
89
8.70k
  bool isTrue = false;
90
8.70k
91
8.70k
  // Get used registers.
92
27.0k
  for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); 
++i18.3k
)
93
18.3k
    if (MCI.getOperand(i).isReg())
94
13.8k
      initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
95
9.61k
  for (unsigned i = 0; i < MCID.getNumImplicitUses(); 
++i907
)
96
907
    initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);
97
8.70k
98
8.70k
  // Get implicit register definitions.
99
8.70k
  if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())
100
2.98k
    
for (; 1.30k
*ImpDef;
++ImpDef1.67k
) {
101
1.67k
      unsigned R = *ImpDef;
102
1.67k
103
1.67k
      if (Hexagon::R31 != R && 
MCID.isCall()1.62k
)
104
51
        // Any register other than the LR and the PC are actually volatile ones
105
51
        // as defined by the ABI, not modified implicitly by the call insn.
106
51
        continue;
107
1.62k
      if (Hexagon::PC == R)
108
621
        // Branches are the only insns that can change the PC,
109
621
        // otherwise a read-only register.
110
621
        continue;
111
1.00k
112
1.00k
      if (Hexagon::USR_OVF == R)
113
559
        // Many insns change the USR implicitly, but only one or another flag.
114
559
        // The instruction table models the USR.OVF flag, which can be
115
559
        // implicitly modified more than once, but cannot be modified in the
116
559
        // same packet with an instruction that modifies is explicitly. Deal
117
559
        // with such situations individually.
118
559
        SoftDefs.insert(R);
119
446
      else if (isPredicateRegister(R) &&
120
446
               
HexagonMCInstrInfo::isPredicateLate(MCII, MCI)168
)
121
23
        // Include implicit late predicates.
122
23
        LatePreds.insert(R);
123
423
      else
124
423
        Defs[R].insert(PredSense(PredReg, isTrue));
125
1.00k
    }
126
8.70k
127
8.70k
  // Figure out explicit register definitions.
128
15.3k
  for (unsigned i = 0; i < MCID.getNumDefs(); 
++i6.66k
) {
129
6.66k
    unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
130
6.66k
    // USR has subregisters (while C8 does not for technical reasons), so
131
6.66k
    // reset R to USR, since we know how to handle multiple defs of USR,
132
6.66k
    // taking into account its subregisters.
133
6.66k
    if (R == Hexagon::C8)
134
0
      R = Hexagon::USR;
135
6.66k
136
6.66k
    // Note register definitions, direct ones as well as indirect side-effects.
137
6.66k
    // Super-registers are not tracked directly, but their components.
138
6.66k
    for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
139
21.9k
         SRI.isValid(); 
++SRI15.2k
) {
140
15.2k
      if (MCSubRegIterator(*SRI, &RI).isValid())
141
5.92k
        // Skip super-registers defined indirectly.
142
5.92k
        continue;
143
9.31k
144
9.31k
      if (R == *SRI) {
145
4.97k
        if (S == R)
146
0
          // Avoid scoring the defined register multiple times.
147
0
          continue;
148
4.97k
        else
149
4.97k
          // Note that the defined register has already been scored.
150
4.97k
          S = R;
151
4.97k
      }
152
9.31k
153
9.31k
      if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
154
945
        // P3:0 is a special case, since multiple predicate register definitions
155
945
        // in a packet is allowed as the equivalent of their logical "and".
156
945
        // Only an explicit definition of P3:0 is noted as such; if a
157
945
        // side-effect, then note as a soft definition.
158
945
        SoftDefs.insert(*SRI);
159
8.36k
      else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) &&
160
8.36k
               
isPredicateRegister(*SRI)51
)
161
23
        // Some insns produce predicates too late to be used in the same packet.
162
23
        LatePreds.insert(*SRI);
163
8.34k
      else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
164
7.97k
                             HexagonII::TypeCVI_VM_TMP_LD)
165
38
        // Temporary loads should be used in the same packet, but don't commit
166
38
        // results, so it should be disregarded if another insn changes the same
167
38
        // register.
168
38
        // TODO: relies on the impossibility of a current and a temporary loads
169
38
        // in the same packet.
170
38
        TmpDefs.insert(*SRI);
171
8.30k
      else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
172
0
        // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
173
0
        // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
174
0
        Uses.insert(*SRI);
175
8.30k
      else
176
8.30k
        Defs[*SRI].insert(PredSense(PredReg, isTrue));
177
9.31k
    }
178
6.66k
  }
179
8.70k
180
8.70k
  // Figure out definitions of new predicate registers.
181
8.70k
  if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
182
3.25k
    
for (unsigned i = MCID.getNumDefs(); 796
i < MCID.getNumOperands();
++i2.45k
)
183
2.45k
      if (MCI.getOperand(i).isReg()) {
184
1.65k
        unsigned P = MCI.getOperand(i).getReg();
185
1.65k
186
1.65k
        if (isPredicateRegister(P))
187
622
          NewPreds.insert(P);
188
1.65k
      }
189
8.70k
}
190
191
HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
192
                                   MCSubtargetInfo const &STI, MCInst &mcb,
193
                                   MCRegisterInfo const &ri, bool ReportErrors)
194
    : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
195
6.52k
      ReportErrors(ReportErrors) {
196
6.52k
  init();
197
6.52k
}
198
199
HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
200
                                   MCSubtargetInfo const &STI,
201
                                   bool CopyReportErrors)
202
    : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
203
0
      STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {}
204
205
8.98k
bool HexagonMCChecker::check(bool FullCheck) {
206
8.98k
  bool chkP = checkPredicates();
207
8.98k
  bool chkNV = checkNewValues();
208
8.98k
  bool chkR = checkRegisters();
209
8.98k
  bool chkRRO = checkRegistersReadOnly();
210
8.98k
  checkRegisterCurDefs();
211
8.98k
  bool chkS = checkSolo();
212
8.98k
  bool chkSh = true;
213
8.98k
  if (FullCheck)
214
6.50k
    chkSh = checkShuffle();
215
8.98k
  bool chkSl = true;
216
8.98k
  if (FullCheck)
217
6.50k
    chkSl = checkSlots();
218
8.98k
  bool chkAXOK = checkAXOK();
219
8.98k
  bool chkCofMax1 = checkCOFMax1();
220
8.98k
  bool chkHWLoop = checkHWLoop();
221
8.98k
  bool chk = chkP && chkNV && 
chkR8.97k
&&
chkRRO8.97k
&&
chkS8.97k
&&
chkSh8.96k
&&
chkSl8.96k
&&
222
8.98k
             
chkAXOK8.96k
&&
chkCofMax18.96k
&&
chkHWLoop8.96k
;
223
8.98k
224
8.98k
  return chk;
225
8.98k
}
226
227
0
static bool isDuplexAGroup(unsigned Opcode) {
228
0
  switch (Opcode) {
229
0
  case Hexagon::SA1_addi:
230
0
  case Hexagon::SA1_addrx:
231
0
  case Hexagon::SA1_addsp:
232
0
  case Hexagon::SA1_and1:
233
0
  case Hexagon::SA1_clrf:
234
0
  case Hexagon::SA1_clrfnew:
235
0
  case Hexagon::SA1_clrt:
236
0
  case Hexagon::SA1_clrtnew:
237
0
  case Hexagon::SA1_cmpeqi:
238
0
  case Hexagon::SA1_combine0i:
239
0
  case Hexagon::SA1_combine1i:
240
0
  case Hexagon::SA1_combine2i:
241
0
  case Hexagon::SA1_combine3i:
242
0
  case Hexagon::SA1_combinerz:
243
0
  case Hexagon::SA1_combinezr:
244
0
  case Hexagon::SA1_dec:
245
0
  case Hexagon::SA1_inc:
246
0
  case Hexagon::SA1_seti:
247
0
  case Hexagon::SA1_setin1:
248
0
  case Hexagon::SA1_sxtb:
249
0
  case Hexagon::SA1_sxth:
250
0
  case Hexagon::SA1_tfr:
251
0
  case Hexagon::SA1_zxtb:
252
0
  case Hexagon::SA1_zxth:
253
0
    return true;
254
0
    break;
255
0
  default:
256
0
    return false;
257
0
  }
258
0
}
259
260
4
static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
261
4
  unsigned Result = 0;
262
4
  unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
263
4
  if (Type == HexagonII::TypeDUPLEX) {
264
0
    unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode();
265
0
    unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode();
266
0
    Result += !isDuplexAGroup(subInst0Opcode);
267
0
    Result += !isDuplexAGroup(subInst1Opcode);
268
0
  } else
269
4
    Result +=
270
4
        Type != HexagonII::TypeALU32_2op && 
Type != HexagonII::TypeALU32_3op3
&&
271
4
        
Type != HexagonII::TypeALU32_ADDI3
&&
Type != HexagonII::TypeS_2op3
&&
272
4
        
Type != HexagonII::TypeS_3op2
&&
273
4
        
(2
Type != HexagonII::TypeALU642
||
HexagonMCInstrInfo::isFloat(MCII, ID)1
);
274
4
  return Result != 0;
275
4
}
276
277
8.98k
bool HexagonMCChecker::checkAXOK() {
278
8.98k
  MCInst const *HasSoloAXInst = nullptr;
279
11.9k
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
280
11.9k
    if (HexagonMCInstrInfo::isSoloAX(MCII, I)) {
281
36
      HasSoloAXInst = &I;
282
36
    }
283
11.9k
  }
284
8.98k
  if (!HasSoloAXInst)
285
8.95k
    return true;
286
40
  
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))36
{
287
40
    if (&I != HasSoloAXInst && 
isNeitherAnorX(MCII, I)4
) {
288
2
      reportError(
289
2
          HasSoloAXInst->getLoc(),
290
2
          Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
291
2
                "instructions"));
292
2
      reportError(I.getLoc(),
293
2
                  Twine("Not an ALU or non-FPU XTYPE instruction"));
294
2
      return false;
295
2
    }
296
40
  }
297
36
  
return true34
;
298
36
}
299
300
6
void HexagonMCChecker::reportBranchErrors() {
301
12
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
302
12
    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
303
12
    if (Desc.isBranch() || 
Desc.isCall()7
||
Desc.isReturn()6
)
304
8
      reportNote(I.getLoc(), "Branching instruction");
305
12
  }
306
6
}
307
308
8.98k
bool HexagonMCChecker::checkHWLoop() {
309
8.98k
  if (!HexagonMCInstrInfo::isInnerLoop(MCB) &&
310
8.98k
      
!HexagonMCInstrInfo::isOuterLoop(MCB)8.95k
)
311
8.94k
    return true;
312
86
  
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))42
{
313
86
    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
314
86
    if (Desc.isBranch() || 
Desc.isCall()84
||
Desc.isReturn()83
) {
315
4
      reportError(MCB.getLoc(),
316
4
                  "Branches cannot be in a packet with hardware loops");
317
4
      reportBranchErrors();
318
4
      return false;
319
4
    }
320
86
  }
321
42
  
return true38
;
322
42
}
323
324
8.98k
bool HexagonMCChecker::checkCOFMax1() {
325
8.98k
  SmallVector<MCInst const *, 2> BranchLocations;
326
11.9k
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
327
11.9k
    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
328
11.9k
    if (Desc.isBranch() || 
Desc.isCall()11.2k
||
Desc.isReturn()11.1k
)
329
864
      BranchLocations.push_back(&I);
330
11.9k
  }
331
9.84k
  for (unsigned J = 0, N = BranchLocations.size(); J < N; 
++J861
) {
332
863
    MCInst const &I = *BranchLocations[J];
333
863
    if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
334
863
      bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
335
863
      bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
336
863
      if (N > 1 && 
!Relax115
&&
!Relax25
) {
337
2
        reportError(I.getLoc(),
338
2
                    "Instruction may not be in a packet with other branches");
339
2
        reportBranchErrors();
340
2
        return false;
341
2
      }
342
861
      if (N > 1 && 
J == 013
&&
!Relax17
) {
343
0
        reportError(I.getLoc(),
344
0
                    "Instruction may not be the first branch in packet");
345
0
        reportBranchErrors();
346
0
        return false;
347
0
      }
348
861
      if (N > 1 && 
J == 113
&&
!Relax26
) {
349
0
        reportError(I.getLoc(),
350
0
                    "Instruction may not be the second branch in packet");
351
0
        reportBranchErrors();
352
0
        return false;
353
0
      }
354
861
    }
355
863
  }
356
8.98k
  
return true8.98k
;
357
8.98k
}
358
359
6.50k
bool HexagonMCChecker::checkSlots() {
360
6.50k
  unsigned slotsUsed = 0;
361
8.56k
  for (auto HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
362
8.56k
    MCInst const &MCI = *HMI.getInst();
363
8.56k
    if (HexagonMCInstrInfo::isImmext(MCI))
364
536
      continue;
365
8.03k
    if (HexagonMCInstrInfo::isDuplex(MCII, MCI))
366
41
      slotsUsed += 2;
367
7.99k
    else
368
7.99k
      ++slotsUsed;
369
8.03k
  }
370
6.50k
371
6.50k
  if (slotsUsed > HEXAGON_PACKET_SIZE) {
372
0
    reportError("invalid instruction packet: out of slots");
373
0
    return false;
374
0
  }
375
6.50k
  return true;
376
6.50k
}
377
378
// Check legal use of predicate registers.
379
8.98k
bool HexagonMCChecker::checkPredicates() {
380
8.98k
  // Check for proper use of new predicate registers.
381
8.98k
  for (const auto &I : NewPreds) {
382
1.04k
    unsigned P = I;
383
1.04k
384
1.04k
    if (!Defs.count(P) || LatePreds.count(P)) {
385
0
      // Error out if the new predicate register is not defined,
386
0
      // or defined "late"
387
0
      // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
388
0
      reportErrorNewValue(P);
389
0
      return false;
390
0
    }
391
1.04k
  }
392
8.98k
393
8.98k
  // Check for proper use of auto-anded of predicate registers.
394
8.98k
  for (const auto &I : LatePreds) {
395
62
    unsigned P = I;
396
62
397
62
    if (LatePreds.count(P) > 1 || Defs.count(P)) {
398
0
      // Error out if predicate register defined "late" multiple times or
399
0
      // defined late and regularly defined
400
0
      // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
401
0
      reportErrorRegisters(P);
402
0
      return false;
403
0
    }
404
62
  }
405
8.98k
406
8.98k
  return true;
407
8.98k
}
408
409
// Check legal use of new values.
410
8.98k
bool HexagonMCChecker::checkNewValues() {
411
11.9k
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
412
11.9k
    if (!HexagonMCInstrInfo::isNewValue(MCII, I))
413
11.2k
      continue;
414
684
    auto Consumer = HexagonMCInstrInfo::predicateInfo(MCII, I);
415
684
    bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch();
416
684
    MCOperand const &Op = HexagonMCInstrInfo::getNewValueOperand(MCII, I);
417
684
    assert(Op.isReg());
418
684
    auto Producer = registerProducer(Op.getReg(), Consumer);
419
684
    if (std::get<0>(Producer) == nullptr) {
420
0
      reportError(I.getLoc(), "New value register consumer has no producer");
421
0
      return false;
422
0
    }
423
684
    if (!RelaxNVChecks) {
424
670
      // Checks that statically prove correct new value consumption
425
670
      if (std::get<2>(Producer).isPredicated() &&
426
670
          
(8
!Consumer.isPredicated()8
||
427
8
           
llvm::HexagonMCInstrInfo::getType(MCII, I) == HexagonII::TypeNCJ6
)) {
428
2
        reportNote(
429
2
            std::get<0>(Producer)->getLoc(),
430
2
            "Register producer is predicated and consumer is unconditional");
431
2
        reportError(I.getLoc(),
432
2
                    "Instruction does not have a valid new register producer");
433
2
        return false;
434
2
      }
435
668
      if (std::get<2>(Producer).Register != Hexagon::NoRegister &&
436
668
          
std::get<2>(Producer).Register != Consumer.Register6
) {
437
1
        reportNote(std::get<0>(Producer)->getLoc(),
438
1
                   "Register producer does not use the same predicate "
439
1
                   "register as the consumer");
440
1
        reportError(I.getLoc(),
441
1
                    "Instruction does not have a valid new register producer");
442
1
        return false;
443
1
      }
444
681
    }
445
681
    if (std::get<2>(Producer).Register == Consumer.Register &&
446
681
        
Consumer.PredicatedTrue != std::get<2>(Producer).PredicatedTrue413
) {
447
2
      reportNote(
448
2
          std::get<0>(Producer)->getLoc(),
449
2
          "Register producer has the opposite predicate sense as consumer");
450
2
      reportError(I.getLoc(),
451
2
                  "Instruction does not have a valid new register producer");
452
2
      return false;
453
2
    }
454
679
    MCInstrDesc const &Desc =
455
679
        HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer));
456
679
    if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
457
679
        Hexagon::DoubleRegsRegClassID) {
458
0
      reportNote(std::get<0>(Producer)->getLoc(),
459
0
                 "Double registers cannot be new-value producers");
460
0
      reportError(I.getLoc(),
461
0
                  "Instruction does not have a valid new register producer");
462
0
      return false;
463
0
    }
464
679
    if ((Desc.mayLoad() && 
std::get<1>(Producer) == 17
) ||
465
679
        (Desc.mayStore() && 
std::get<1>(Producer) == 00
)) {
466
0
      unsigned Mode =
467
0
          HexagonMCInstrInfo::getAddrMode(MCII, *std::get<0>(Producer));
468
0
      StringRef ModeError;
469
0
      if (Mode == HexagonII::AbsoluteSet)
470
0
        ModeError = "Absolute-set";
471
0
      if (Mode == HexagonII::PostInc)
472
0
        ModeError = "Auto-increment";
473
0
      if (!ModeError.empty()) {
474
0
        reportNote(std::get<0>(Producer)->getLoc(),
475
0
                   ModeError + " registers cannot be a new-value "
476
0
                               "producer");
477
0
        reportError(I.getLoc(),
478
0
                    "Instruction does not have a valid new register producer");
479
0
        return false;
480
0
      }
481
679
    }
482
679
    if (Branch && 
HexagonMCInstrInfo::isFloat(MCII, *std::get<0>(Producer))197
) {
483
2
      reportNote(std::get<0>(Producer)->getLoc(),
484
2
                 "FPU instructions cannot be new-value producers for jumps");
485
2
      reportError(I.getLoc(),
486
2
                  "Instruction does not have a valid new register producer");
487
2
      return false;
488
2
    }
489
679
  }
490
8.98k
  
return true8.97k
;
491
8.98k
}
492
493
8.98k
bool HexagonMCChecker::checkRegistersReadOnly() {
494
11.8k
  for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
495
11.8k
    MCInst const &Inst = *I.getInst();
496
11.8k
    unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
497
20.9k
    for (unsigned j = 0; j < Defs; 
++j9.05k
) {
498
9.06k
      MCOperand const &Operand = Inst.getOperand(j);
499
9.06k
      assert(Operand.isReg() && "Def is not a register");
500
9.06k
      unsigned Register = Operand.getReg();
501
9.06k
      if (ReadOnly.find(Register) != ReadOnly.end()) {
502
5
        reportError(Inst.getLoc(), "Cannot write to read-only register `" +
503
5
                                       Twine(RI.getName(Register)) + "'");
504
5
        return false;
505
5
      }
506
9.06k
    }
507
11.8k
  }
508
8.98k
  
return true8.98k
;
509
8.98k
}
510
511
54
bool HexagonMCChecker::registerUsed(unsigned Register) {
512
54
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
513
59
    for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
514
59
                  n = I.getNumOperands();
515
69
         j < n; 
++j10
) {
516
64
      MCOperand const &Operand = I.getOperand(j);
517
64
      if (Operand.isReg() && 
Operand.getReg() == Register61
)
518
54
        return true;
519
64
    }
520
54
  
return false0
;
521
54
}
522
523
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
524
HexagonMCChecker::registerProducer(
525
684
    unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
526
684
  std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
527
684
      WrongSense;
528
1.12k
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
529
1.12k
    MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
530
1.12k
    auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
531
1.58k
    for (unsigned J = 0, N = Desc.getNumDefs(); J < N; 
++J454
)
532
870
      for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
533
1.92k
           K.isValid(); 
++K1.05k
)
534
1.46k
        if (*K == Register) {
535
680
          if (RelaxNVChecks ||
536
680
              
(666
ProducerPredicate.Register == ConsumerPredicate.Register666
&&
537
666
               
(403
ProducerPredicate.Register == Hexagon::NoRegister403
||
538
403
                ProducerPredicate.PredicatedTrue ==
539
5
                    ConsumerPredicate.PredicatedTrue)))
540
416
            return std::make_tuple(&I, J, ProducerPredicate);
541
264
          std::get<0>(WrongSense) = &I;
542
264
          std::get<1>(WrongSense) = J;
543
264
          std::get<2>(WrongSense) = ProducerPredicate;
544
264
        }
545
1.12k
    
if (713
Register == Hexagon::VTMP713
&&
HexagonMCInstrInfo::hasTmpDst(MCII, I)8
)
546
4
      return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
547
713
  }
548
684
  
return WrongSense264
;
549
684
}
550
551
8.98k
void HexagonMCChecker::checkRegisterCurDefs() {
552
11.9k
  for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
553
11.9k
    if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
554
11.9k
        
HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()136
) {
555
54
      unsigned Register = I.getOperand(0).getReg();
556
54
      if (!registerUsed(Register))
557
0
        reportWarning("Register `" + Twine(RI.getName(Register)) +
558
0
                      "' used with `.cur' "
559
0
                      "but not used in the same packet");
560
54
    }
561
11.9k
  }
562
8.98k
}
563
564
// Check for legal register uses and definitions.
565
8.98k
bool HexagonMCChecker::checkRegisters() {
566
8.98k
  // Check for proper register definitions.
567
11.9k
  for (const auto &I : Defs) {
568
11.9k
    unsigned R = I.first;
569
11.9k
570
11.9k
    if (isLoopRegister(R) && 
Defs.count(R) > 1218
&&
571
11.9k
        
(0
HexagonMCInstrInfo::isInnerLoop(MCB)0
||
572
0
         HexagonMCInstrInfo::isOuterLoop(MCB))) {
573
0
      // Error out for definitions of loop registers at the end of a loop.
574
0
      reportError("loop-setup and some branch instructions "
575
0
                  "cannot be in the same packet");
576
0
      return false;
577
0
    }
578
11.9k
    if (SoftDefs.count(R)) {
579
0
      // Error out for explicit changes to registers also weakly defined
580
0
      // (e.g., "{ usr = r0; r0 = sfadd(...) }").
581
0
      unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
582
0
      unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
583
0
      reportErrorRegisters(BadR);
584
0
      return false;
585
0
    }
586
11.9k
    if (!isPredicateRegister(R) && 
Defs[R].size() > 110.5k
) {
587
14
      // Check for multiple register definitions.
588
14
      PredSet &PM = Defs[R];
589
14
590
14
      // Check for multiple unconditional register definitions.
591
14
      if (PM.count(Unconditional)) {
592
3
        // Error out on an unconditional change when there are any other
593
3
        // changes, conditional or not.
594
3
        unsigned UsrR = Hexagon::USR;
595
3
        unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? 
UsrR0
: R;
596
3
        reportErrorRegisters(BadR);
597
3
        return false;
598
3
      }
599
11
      // Check for multiple conditional register definitions.
600
21
      
for (const auto &J : PM)11
{
601
21
        PredSense P = J;
602
21
603
21
        // Check for multiple uses of the same condition.
604
21
        if (PM.count(P) > 1) {
605
1
          // Error out on conditional changes based on the same predicate
606
1
          // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
607
1
          reportErrorRegisters(R);
608
1
          return false;
609
1
        }
610
20
        // Check for the use of the complementary condition.
611
20
        P.second = !P.second;
612
20
        if (PM.count(P) && PM.size() > 2) {
613
0
          // Error out on conditional changes based on the same predicate
614
0
          // multiple times
615
0
          // (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
616
0
          reportErrorRegisters(R);
617
0
          return false;
618
0
        }
619
20
      }
620
11
    }
621
11.9k
  }
622
8.98k
623
8.98k
  // Check for use of temporary definitions.
624
8.98k
  
for (const auto &I : TmpDefs)8.98k
{
625
57
    unsigned R = I;
626
57
627
57
    if (!Uses.count(R)) {
628
0
      // special case for vhist
629
0
      bool vHistFound = false;
630
0
      for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
631
0
        if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
632
0
            HexagonII::TypeCVI_HIST) {
633
0
          vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
634
0
          break;
635
0
        }
636
0
      }
637
0
      // Warn on an unused temporary definition.
638
0
      if (!vHistFound) {
639
0
        reportWarning("register `" + Twine(RI.getName(R)) +
640
0
                      "' used with `.tmp' but not used in the same packet");
641
0
        return true;
642
0
      }
643
0
    }
644
57
  }
645
8.98k
646
8.98k
  return true;
647
8.98k
}
648
649
// Check for legal use of solo insns.
650
8.98k
bool HexagonMCChecker::checkSolo() {
651
8.98k
  if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
652
5.21k
    
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))2.28k
{
653
5.21k
      if (HexagonMCInstrInfo::isSolo(MCII, I)) {
654
4
        reportError(I.getLoc(), "Instruction is marked `isSolo' and "
655
4
                                "cannot have other instructions in "
656
4
                                "the same packet");
657
4
        return false;
658
4
      }
659
5.21k
    }
660
8.98k
661
8.98k
  
return true8.98k
;
662
8.98k
}
663
664
6.50k
bool HexagonMCChecker::checkShuffle() {
665
6.50k
  HexagonMCShuffler MCSDX(Context, ReportErrors, MCII, STI, MCB);
666
6.50k
  return MCSDX.check();
667
6.50k
}
668
669
void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
670
  switch (Register) {
671
  default:
672
    break;
673
  case Hexagon::R15:
674
    Register = Hexagon::R23;
675
    break;
676
  case Hexagon::R14:
677
    Register = Hexagon::R22;
678
    break;
679
  case Hexagon::R13:
680
    Register = Hexagon::R21;
681
    break;
682
  case Hexagon::R12:
683
    Register = Hexagon::R20;
684
    break;
685
  case Hexagon::R11:
686
    Register = Hexagon::R19;
687
    break;
688
  case Hexagon::R10:
689
    Register = Hexagon::R18;
690
    break;
691
  case Hexagon::R9:
692
    Register = Hexagon::R17;
693
    break;
694
  case Hexagon::R8:
695
    Register = Hexagon::R16;
696
    break;
697
  }
698
}
699
700
4
void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
701
4
  reportError("register `" + Twine(RI.getName(Register)) +
702
4
              "' modified more than once");
703
4
}
704
705
0
void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
706
0
  reportError("register `" + Twine(RI.getName(Register)) +
707
0
              "' used with `.new' "
708
0
              "but not validly modified in the same packet");
709
0
}
710
711
4
void HexagonMCChecker::reportError(Twine const &Msg) {
712
4
  reportError(MCB.getLoc(), Msg);
713
4
}
714
715
30
void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) {
716
30
  if (ReportErrors)
717
26
    Context.reportError(Loc, Msg);
718
30
}
719
720
15
void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) {
721
15
  if (ReportErrors) {
722
15
    auto SM = Context.getSourceManager();
723
15
    if (SM)
724
15
      SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
725
15
  }
726
15
}
727
728
0
void HexagonMCChecker::reportWarning(Twine const &Msg) {
729
0
  if (ReportErrors) {
730
0
    auto SM = Context.getSourceManager();
731
0
    if (SM)
732
0
      SM->PrintMessage(MCB.getLoc(), SourceMgr::DK_Warning, Msg);
733
0
  }
734
0
}